Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / plat-mxc / include / mach / irqs.h
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5 /*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #ifndef __ASM_ARCH_MXC_IRQS_H__
12 #define __ASM_ARCH_MXC_IRQS_H__
13
14 /*
15 * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64
16 */
17 #ifdef CONFIG_MXC_TZIC
18 #define MXC_INTERNAL_IRQS 128
19 #else
20 #define MXC_INTERNAL_IRQS 64
21 #endif
22
23 #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
24
25 /* these are ordered by size to support multi-SoC kernels */
26 #if defined CONFIG_ARCH_MX53
27 #define MXC_GPIO_IRQS (32 * 7)
28 #elif defined CONFIG_ARCH_MX2
29 #define MXC_GPIO_IRQS (32 * 6)
30 #elif defined CONFIG_ARCH_MX50
31 #define MXC_GPIO_IRQS (32 * 6)
32 #elif defined CONFIG_ARCH_MX1
33 #define MXC_GPIO_IRQS (32 * 4)
34 #elif defined CONFIG_ARCH_MX25
35 #define MXC_GPIO_IRQS (32 * 4)
36 #elif defined CONFIG_ARCH_MX51
37 #define MXC_GPIO_IRQS (32 * 4)
38 #elif defined CONFIG_ARCH_MXC91231
39 #define MXC_GPIO_IRQS (32 * 4)
40 #elif defined CONFIG_ARCH_MX3
41 #define MXC_GPIO_IRQS (32 * 3)
42 #endif
43
44 /*
45 * The next 16 interrupts are for board specific purposes. Since
46 * the kernel can only run on one machine at a time, we can re-use
47 * these. If you need more, increase MXC_BOARD_IRQS, but keep it
48 * within sensible limits.
49 */
50 #define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)
51
52 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
53 #define MXC_BOARD_IRQS 80
54 #else
55 #define MXC_BOARD_IRQS 16
56 #endif
57
58 #define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
59
60 #ifdef CONFIG_MX3_IPU_IRQS
61 #define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS
62 #else
63 #define MX3_IPU_IRQS 0
64 #endif
65 /* REVISIT: Add IPU irqs on IMX51 */
66
67 #define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
68
69 extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
70
71 /* all normal IRQs can be FIQs */
72 #define FIQ_START 0
73 /* switch betwean IRQ and FIQ */
74 extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type);
75
76 #endif /* __ASM_ARCH_MXC_IRQS_H__ */