arch/arm/mm/proc-sa110.S

   1 /*
   2  *  linux/arch/arm/mm/proc-sa110.S
   3  *
   4  *  Copyright (C) 1997-2002 Russell King
   5  *  hacked for non-paged-MM by Hyok S. Choi, 2003.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  *  MMU functions for SA110
  12  *
  13  *  These are the low level assembler for performing cache and TLB
  14  *  functions on the StrongARM-110.
  15  */
  16 #include <linux/linkage.h>
  17 #include <linux/init.h>
  18 #include <asm/assembler.h>
  19 #include <asm/asm-offsets.h>
  20 #include <asm/hwcap.h>
  21 #include <mach/hardware.h>
  22 #include <asm/pgtable-hwdef.h>
  23 #include <asm/pgtable.h>
  24 #include <asm/ptrace.h>
  25
  26 #include "proc-macros.S"
  27
  28 /*
  29  * the cache line size of the I and D cache
  30  */
  31 #define DCACHELINESIZE  32
  32
  33         .text
  34
  35 /*
  36  * cpu_sa110_proc_init()
  37  */
  38 ENTRY(cpu_sa110_proc_init)
  39         mov     r0, #0
  40         mcr     p15, 0, r0, c15, c1, 2          @ Enable clock switching
  41         mov     pc, lr
  42
  43 /*
  44  * cpu_sa110_proc_fin()
  45  */
  46 ENTRY(cpu_sa110_proc_fin)
  47         mov     r0, #0
  48         mcr     p15, 0, r0, c15, c2, 2          @ Disable clock switching
  49         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  50         bic     r0, r0, #0x1000                 @ ...i............
  51         bic     r0, r0, #0x000e                 @ ............wca.
  52         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  53         mov     pc, lr
  54
  55 /*
  56  * cpu_sa110_reset(loc)
  57  *
  58  * Perform a soft reset of the system.  Put the CPU into the
  59  * same state as it would be if it had been reset, and branch
  60  * to what would be the reset vector.
  61  *
  62  * loc: location to jump to for soft reset
  63  */
  64         .align  5
  65 ENTRY(cpu_sa110_reset)
  66         mov     ip, #0
  67         mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
  68         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
  69 #ifdef CONFIG_MMU
  70         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
  71 #endif
  72         mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
  73         bic     ip, ip, #0x000f                 @ ............wcam
  74         bic     ip, ip, #0x1100                 @ ...i...s........
  75         mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
  76         mov     pc, r0
  77
  78 /*
  79  * cpu_sa110_do_idle(type)
  80  *
  81  * Cause the processor to idle
  82  *
  83  * type: call type:
  84  *   0 = slow idle
  85  *   1 = fast idle
  86  *   2 = switch to slow processor clock
  87  *   3 = switch to fast processor clock
  88  */
  89         .align  5
  90
  91 ENTRY(cpu_sa110_do_idle)
  92         mcr     p15, 0, ip, c15, c2, 2          @ disable clock switching
  93         ldr     r1, =UNCACHEABLE_ADDR           @ load from uncacheable loc
  94         ldr     r1, [r1, #0]                    @ force switch to MCLK
  95         mov     r0, r0                          @ safety
  96         mov     r0, r0                          @ safety
  97         mov     r0, r0                          @ safety
  98         mcr     p15, 0, r0, c15, c8, 2          @ Wait for interrupt, cache aligned
  99         mov     r0, r0                          @ safety
 100         mov     r0, r0                          @ safety
 101         mov     r0, r0                          @ safety
 102         mcr     p15, 0, r0, c15, c1, 2          @ enable clock switching
 103         mov     pc, lr
 104
 105 /* ================================= CACHE ================================ */
 106
 107 /*
 108  * cpu_sa110_dcache_clean_area(addr,sz)
 109  *
 110  * Clean the specified entry of any caches such that the MMU
 111  * translation fetches will obtain correct data.
 112  *
 113  * addr: cache-unaligned virtual address
 114  */
 115         .align  5
 116 ENTRY(cpu_sa110_dcache_clean_area)
 117 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 118         add     r0, r0, #DCACHELINESIZE
 119         subs    r1, r1, #DCACHELINESIZE
 120         bhi     1b
 121         mov     pc, lr
 122
 123 /* =============================== PageTable ============================== */
 124
 125 /*
 126  * cpu_sa110_switch_mm(pgd)
 127  *
 128  * Set the translation base pointer to be as described by pgd.
 129  *
 130  * pgd: new page tables
 131  */
 132         .align  5
 133 ENTRY(cpu_sa110_switch_mm)
 134 #ifdef CONFIG_MMU
 135         str     lr, [sp, #-4]!
 136         bl      v4wb_flush_kern_cache_all       @ clears IP
 137         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
 138         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
 139         ldr     pc, [sp], #4
 140 #else
 141         mov     pc, lr
 142 #endif
 143
 144 /*
 145  * cpu_sa110_set_pte_ext(ptep, pte, ext)
 146  *
 147  * Set a PTE and flush it out
 148  */
 149         .align  5
 150 ENTRY(cpu_sa110_set_pte_ext)
 151 #ifdef CONFIG_MMU
 152         armv3_set_pte_ext wc_disable=0
 153         mov     r0, r0
 154         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 155         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 156 #endif
 157         mov     pc, lr
 158
 159         __CPUINIT
 160
 161         .type   __sa110_setup, #function
 162 __sa110_setup:
 163         mov     r10, #0
 164         mcr     p15, 0, r10, c7, c7             @ invalidate I,D caches on v4
 165         mcr     p15, 0, r10, c7, c10, 4         @ drain write buffer on v4
 166 #ifdef CONFIG_MMU
 167         mcr     p15, 0, r10, c8, c7             @ invalidate I,D TLBs on v4
 168 #endif
 169
 170         adr     r5, sa110_crval
 171         ldmia   r5, {r5, r6}
 172         mrc     p15, 0, r0, c1, c0              @ get control register v4
 173         bic     r0, r0, r5
 174         orr     r0, r0, r6
 175         mov     pc, lr
 176         .size   __sa110_setup, . - __sa110_setup
 177
 178         /*
 179          *  R
 180          * .RVI ZFRS BLDP WCAM
 181          * ..01 0001 ..11 1101
 182          *
 183          */
 184         .type   sa110_crval, #object
 185 sa110_crval:
 186         crval   clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
 187
 188         __INITDATA
 189
 190 /*
 191  * Purpose : Function pointers used to access above functions - all calls
 192  *           come through these
 193  */
 194
 195         .type   sa110_processor_functions, #object
 196 ENTRY(sa110_processor_functions)
 197         .word   v4_early_abort
 198         .word   legacy_pabort
 199         .word   cpu_sa110_proc_init
 200         .word   cpu_sa110_proc_fin
 201         .word   cpu_sa110_reset
 202         .word   cpu_sa110_do_idle
 203         .word   cpu_sa110_dcache_clean_area
 204         .word   cpu_sa110_switch_mm
 205         .word   cpu_sa110_set_pte_ext
 206         .word   0
 207         .word   0
 208         .word   0
 209         .size   sa110_processor_functions, . - sa110_processor_functions
 210
 211         .section ".rodata"
 212
 213         .type   cpu_arch_name, #object
 214 cpu_arch_name:
 215         .asciz  "armv4"
 216         .size   cpu_arch_name, . - cpu_arch_name
 217
 218         .type   cpu_elf_name, #object
 219 cpu_elf_name:
 220         .asciz  "v4"
 221         .size   cpu_elf_name, . - cpu_elf_name
 222
 223         .type   cpu_sa110_name, #object
 224 cpu_sa110_name:
 225         .asciz  "StrongARM-110"
 226         .size   cpu_sa110_name, . - cpu_sa110_name
 227
 228         .align
 229
 230         .section ".proc.info.init", #alloc, #execinstr
 231
 232         .type   __sa110_proc_info,#object
 233 __sa110_proc_info:
 234         .long   0x4401a100
 235         .long   0xfffffff0
 236         .long   PMD_TYPE_SECT | \
 237                 PMD_SECT_BUFFERABLE | \
 238                 PMD_SECT_CACHEABLE | \
 239                 PMD_SECT_AP_WRITE | \
 240                 PMD_SECT_AP_READ
 241         .long   PMD_TYPE_SECT | \
 242                 PMD_SECT_AP_WRITE | \
 243                 PMD_SECT_AP_READ
 244         b       __sa110_setup
 245         .long   cpu_arch_name
 246         .long   cpu_elf_name
 247         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
 248         .long   cpu_sa110_name
 249         .long   sa110_processor_functions
 250         .long   v4wb_tlb_fns
 251         .long   v4wb_user_fns
 252         .long   v4wb_cache_fns
 253         .size   __sa110_proc_info, . - __sa110_proc_info