arch/arm/mm/proc-arm1026.S

   1 /*
   2  *  linux/arch/arm/mm/proc-arm1026.S: MMU functions for ARM1026EJ-S
   3  *
   4  *  Copyright (C) 2000 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
   6  *  hacked for non-paged-MM by Hyok S. Choi, 2003.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  *
  14  * These are the low level assembler for performing cache and TLB
  15  * functions on the ARM1026EJ-S.
  16  */
  17 #include <linux/linkage.h>
  18 #include <linux/init.h>
  19 #include <asm/assembler.h>
  20 #include <asm/asm-offsets.h>
  21 #include <asm/hwcap.h>
  22 #include <asm/pgtable-hwdef.h>
  23 #include <asm/pgtable.h>
  24 #include <asm/ptrace.h>
  25
  26 #include "proc-macros.S"
  27
  28 /*
  29  * This is the maximum size of an area which will be invalidated
  30  * using the single invalidate entry instructions.  Anything larger
  31  * than this, and we go for the whole cache.
  32  *
  33  * This value should be chosen such that we choose the cheapest
  34  * alternative.
  35  */
  36 #define MAX_AREA_SIZE   32768
  37
  38 /*
  39  * The size of one data cache line.
  40  */
  41 #define CACHE_DLINESIZE 32
  42
  43 /*
  44  * The number of data cache segments.
  45  */
  46 #define CACHE_DSEGMENTS 16
  47
  48 /*
  49  * The number of lines in a cache segment.
  50  */
  51 #define CACHE_DENTRIES  64
  52
  53 /*
  54  * This is the size at which it becomes more efficient to
  55  * clean the whole cache, rather than using the individual
  56  * cache line maintenance instructions.
  57  */
  58 #define CACHE_DLIMIT    32768
  59
  60         .text
  61 /*
  62  * cpu_arm1026_proc_init()
  63  */
  64 ENTRY(cpu_arm1026_proc_init)
  65         mov     pc, lr
  66
  67 /*
  68  * cpu_arm1026_proc_fin()
  69  */
  70 ENTRY(cpu_arm1026_proc_fin)
  71         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  72         bic     r0, r0, #0x1000                 @ ...i............
  73         bic     r0, r0, #0x000e                 @ ............wca.
  74         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  75         mov     pc, lr
  76
  77 /*
  78  * cpu_arm1026_reset(loc)
  79  *
  80  * Perform a soft reset of the system.  Put the CPU into the
  81  * same state as it would be if it had been reset, and branch
  82  * to what would be the reset vector.
  83  *
  84  * loc: location to jump to for soft reset
  85  */
  86         .align  5
  87         .pushsection    .idmap.text, "ax"
  88 ENTRY(cpu_arm1026_reset)
  89         mov     ip, #0
  90         mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
  91         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
  92 #ifdef CONFIG_MMU
  93         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
  94 #endif
  95         mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
  96         bic     ip, ip, #0x000f                 @ ............wcam
  97         bic     ip, ip, #0x1100                 @ ...i...s........
  98         mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
  99         mov     pc, r0
 100 ENDPROC(cpu_arm1026_reset)
 101         .popsection
 102
 103 /*
 104  * cpu_arm1026_do_idle()
 105  */
 106         .align  5
 107 ENTRY(cpu_arm1026_do_idle)
 108         mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
 109         mov     pc, lr
 110
 111 /* ================================= CACHE ================================ */
 112
 113         .align  5
 114
 115 /*
 116  *      flush_icache_all()
 117  *
 118  *      Unconditionally clean and invalidate the entire icache.
 119  */
 120 ENTRY(arm1026_flush_icache_all)
 121 #ifndef CONFIG_CPU_ICACHE_DISABLE
 122         mov     r0, #0
 123         mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
 124 #endif
 125         mov     pc, lr
 126 ENDPROC(arm1026_flush_icache_all)
 127
 128 /*
 129  *      flush_user_cache_all()
 130  *
 131  *      Invalidate all cache entries in a particular address
 132  *      space.
 133  */
 134 ENTRY(arm1026_flush_user_cache_all)
 135         /* FALLTHROUGH */
 136 /*
 137  *      flush_kern_cache_all()
 138  *
 139  *      Clean and invalidate the entire cache.
 140  */
 141 ENTRY(arm1026_flush_kern_cache_all)
 142         mov     r2, #VM_EXEC
 143         mov     ip, #0
 144 __flush_whole_cache:
 145 #ifndef CONFIG_CPU_DCACHE_DISABLE
 146 1:      mrc     p15, 0, r15, c7, c14, 3         @ test, clean, invalidate
 147         bne     1b
 148 #endif
 149         tst     r2, #VM_EXEC
 150 #ifndef CONFIG_CPU_ICACHE_DISABLE
 151         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
 152 #endif
 153         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
 154         mov     pc, lr
 155
 156 /*
 157  *      flush_user_cache_range(start, end, flags)
 158  *
 159  *      Invalidate a range of cache entries in the specified
 160  *      address space.
 161  *
 162  *      - start - start address (inclusive)
 163  *      - end   - end address (exclusive)
 164  *      - flags - vm_flags for this space
 165  */
 166 ENTRY(arm1026_flush_user_cache_range)
 167         mov     ip, #0
 168         sub     r3, r1, r0                      @ calculate total size
 169         cmp     r3, #CACHE_DLIMIT
 170         bhs     __flush_whole_cache
 171
 172 #ifndef CONFIG_CPU_DCACHE_DISABLE
 173 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 174         add     r0, r0, #CACHE_DLINESIZE
 175         cmp     r0, r1
 176         blo     1b
 177 #endif
 178         tst     r2, #VM_EXEC
 179 #ifndef CONFIG_CPU_ICACHE_DISABLE
 180         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
 181 #endif
 182         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
 183         mov     pc, lr
 184
 185 /*
 186  *      coherent_kern_range(start, end)
 187  *
 188  *      Ensure coherency between the Icache and the Dcache in the
 189  *      region described by start.  If you have non-snooping
 190  *      Harvard caches, you need to implement this function.
 191  *
 192  *      - start - virtual start address
 193  *      - end   - virtual end address
 194  */
 195 ENTRY(arm1026_coherent_kern_range)
 196         /* FALLTHROUGH */
 197 /*
 198  *      coherent_user_range(start, end)
 199  *
 200  *      Ensure coherency between the Icache and the Dcache in the
 201  *      region described by start.  If you have non-snooping
 202  *      Harvard caches, you need to implement this function.
 203  *
 204  *      - start - virtual start address
 205  *      - end   - virtual end address
 206  */
 207 ENTRY(arm1026_coherent_user_range)
 208         mov     ip, #0
 209         bic     r0, r0, #CACHE_DLINESIZE - 1
 210 1:
 211 #ifndef CONFIG_CPU_DCACHE_DISABLE
 212         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 213 #endif
 214 #ifndef CONFIG_CPU_ICACHE_DISABLE
 215         mcr     p15, 0, r0, c7, c5, 1           @ invalidate I entry
 216 #endif
 217         add     r0, r0, #CACHE_DLINESIZE
 218         cmp     r0, r1
 219         blo     1b
 220         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 221         mov     r0, #0
 222         mov     pc, lr
 223
 224 /*
 225  *      flush_kern_dcache_area(void *addr, size_t size)
 226  *
 227  *      Ensure no D cache aliasing occurs, either with itself or
 228  *      the I cache
 229  *
 230  *      - addr  - kernel address
 231  *      - size  - region size
 232  */
 233 ENTRY(arm1026_flush_kern_dcache_area)
 234         mov     ip, #0
 235 #ifndef CONFIG_CPU_DCACHE_DISABLE
 236         add     r1, r0, r1
 237 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 238         add     r0, r0, #CACHE_DLINESIZE
 239         cmp     r0, r1
 240         blo     1b
 241 #endif
 242         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 243         mov     pc, lr
 244
 245 /*
 246  *      dma_inv_range(start, end)
 247  *
 248  *      Invalidate (discard) the specified virtual address range.
 249  *      May not write back any entries.  If 'start' or 'end'
 250  *      are not cache line aligned, those lines must be written
 251  *      back.
 252  *
 253  *      - start - virtual start address
 254  *      - end   - virtual end address
 255  *
 256  * (same as v4wb)
 257  */
 258 arm1026_dma_inv_range:
 259         mov     ip, #0
 260 #ifndef CONFIG_CPU_DCACHE_DISABLE
 261         tst     r0, #CACHE_DLINESIZE - 1
 262         bic     r0, r0, #CACHE_DLINESIZE - 1
 263         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
 264         tst     r1, #CACHE_DLINESIZE - 1
 265         mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
 266 1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
 267         add     r0, r0, #CACHE_DLINESIZE
 268         cmp     r0, r1
 269         blo     1b
 270 #endif
 271         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 272         mov     pc, lr
 273
 274 /*
 275  *      dma_clean_range(start, end)
 276  *
 277  *      Clean the specified virtual address range.
 278  *
 279  *      - start - virtual start address
 280  *      - end   - virtual end address
 281  *
 282  * (same as v4wb)
 283  */
 284 arm1026_dma_clean_range:
 285         mov     ip, #0
 286 #ifndef CONFIG_CPU_DCACHE_DISABLE
 287         bic     r0, r0, #CACHE_DLINESIZE - 1
 288 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 289         add     r0, r0, #CACHE_DLINESIZE
 290         cmp     r0, r1
 291         blo     1b
 292 #endif
 293         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 294         mov     pc, lr
 295
 296 /*
 297  *      dma_flush_range(start, end)
 298  *
 299  *      Clean and invalidate the specified virtual address range.
 300  *
 301  *      - start - virtual start address
 302  *      - end   - virtual end address
 303  */
 304 ENTRY(arm1026_dma_flush_range)
 305         mov     ip, #0
 306 #ifndef CONFIG_CPU_DCACHE_DISABLE
 307         bic     r0, r0, #CACHE_DLINESIZE - 1
 308 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 309         add     r0, r0, #CACHE_DLINESIZE
 310         cmp     r0, r1
 311         blo     1b
 312 #endif
 313         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 314         mov     pc, lr
 315
 316 /*
 317  *      dma_map_area(start, size, dir)
 318  *      - start - kernel virtual start address
 319  *      - size  - size of region
 320  *      - dir   - DMA direction
 321  */
 322 ENTRY(arm1026_dma_map_area)
 323         add     r1, r1, r0
 324         cmp     r2, #DMA_TO_DEVICE
 325         beq     arm1026_dma_clean_range
 326         bcs     arm1026_dma_inv_range
 327         b       arm1026_dma_flush_range
 328 ENDPROC(arm1026_dma_map_area)
 329
 330 /*
 331  *      dma_unmap_area(start, size, dir)
 332  *      - start - kernel virtual start address
 333  *      - size  - size of region
 334  *      - dir   - DMA direction
 335  */
 336 ENTRY(arm1026_dma_unmap_area)
 337         mov     pc, lr
 338 ENDPROC(arm1026_dma_unmap_area)
 339
 340         .globl  arm1026_flush_kern_cache_louis
 341         .equ    arm1026_flush_kern_cache_louis, arm1026_flush_kern_cache_all
 342
 343         @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
 344         define_cache_functions arm1026
 345
 346         .align  5
 347 ENTRY(cpu_arm1026_dcache_clean_area)
 348 #ifndef CONFIG_CPU_DCACHE_DISABLE
 349         mov     ip, #0
 350 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 351         add     r0, r0, #CACHE_DLINESIZE
 352         subs    r1, r1, #CACHE_DLINESIZE
 353         bhi     1b
 354 #endif
 355         mov     pc, lr
 356
 357 /* =============================== PageTable ============================== */
 358
 359 /*
 360  * cpu_arm1026_switch_mm(pgd)
 361  *
 362  * Set the translation base pointer to be as described by pgd.
 363  *
 364  * pgd: new page tables
 365  */
 366         .align  5
 367 ENTRY(cpu_arm1026_switch_mm)
 368 #ifdef CONFIG_MMU
 369         mov     r1, #0
 370 #ifndef CONFIG_CPU_DCACHE_DISABLE
 371 1:      mrc     p15, 0, r15, c7, c14, 3         @ test, clean, invalidate
 372         bne     1b
 373 #endif
 374 #ifndef CONFIG_CPU_ICACHE_DISABLE
 375         mcr     p15, 0, r1, c7, c5, 0           @ invalidate I cache
 376 #endif
 377         mcr     p15, 0, r1, c7, c10, 4          @ drain WB
 378         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
 379         mcr     p15, 0, r1, c8, c7, 0           @ invalidate I & D TLBs
 380 #endif
 381         mov     pc, lr
 382
 383 /*
 384  * cpu_arm1026_set_pte_ext(ptep, pte, ext)
 385  *
 386  * Set a PTE and flush it out
 387  */
 388         .align  5
 389 ENTRY(cpu_arm1026_set_pte_ext)
 390 #ifdef CONFIG_MMU
 391         armv3_set_pte_ext
 392         mov     r0, r0
 393 #ifndef CONFIG_CPU_DCACHE_DISABLE
 394         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 395 #endif
 396 #endif /* CONFIG_MMU */
 397         mov     pc, lr
 398
 399
 400         __CPUINIT
 401
 402         .type   __arm1026_setup, #function
 403 __arm1026_setup:
 404         mov     r0, #0
 405         mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
 406         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
 407 #ifdef CONFIG_MMU
 408         mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
 409         mcr     p15, 0, r4, c2, c0              @ load page table pointer
 410 #endif
 411 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 412         mov     r0, #4                          @ explicitly disable writeback
 413         mcr     p15, 7, r0, c15, c0, 0
 414 #endif
 415         adr     r5, arm1026_crval
 416         ldmia   r5, {r5, r6}
 417         mrc     p15, 0, r0, c1, c0              @ get control register v4
 418         bic     r0, r0, r5
 419         orr     r0, r0, r6
 420 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
 421         orr     r0, r0, #0x4000                 @ .R.. .... .... ....
 422 #endif
 423         mov     pc, lr
 424         .size   __arm1026_setup, . - __arm1026_setup
 425
 426         /*
 427          *  R
 428          * .RVI ZFRS BLDP WCAM
 429          * .011 1001 ..11 0101
 430          *
 431          */
 432         .type   arm1026_crval, #object
 433 arm1026_crval:
 434         crval   clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934
 435
 436         __INITDATA
 437         @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
 438         define_processor_functions arm1026, dabort=v5t_early_abort, pabort=legacy_pabort
 439
 440         .section .rodata
 441
 442         string  cpu_arch_name, "armv5tej"
 443         string  cpu_elf_name, "v5"
 444         .align
 445         string  cpu_arm1026_name, "ARM1026EJ-S"
 446         .align
 447
 448         .section ".proc.info.init", #alloc, #execinstr
 449
 450         .type   __arm1026_proc_info,#object
 451 __arm1026_proc_info:
 452         .long   0x4106a260                      @ ARM 1026EJ-S (v5TEJ)
 453         .long   0xff0ffff0
 454         .long   PMD_TYPE_SECT | \
 455                 PMD_BIT4 | \
 456                 PMD_SECT_AP_WRITE | \
 457                 PMD_SECT_AP_READ
 458         .long   PMD_TYPE_SECT | \
 459                 PMD_BIT4 | \
 460                 PMD_SECT_AP_WRITE | \
 461                 PMD_SECT_AP_READ
 462         b       __arm1026_setup
 463         .long   cpu_arch_name
 464         .long   cpu_elf_name
 465         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
 466         .long   cpu_arm1026_name
 467         .long   arm1026_processor_functions
 468         .long   v4wbi_tlb_fns
 469         .long   v4wb_user_fns
 470         .long   arm1026_cache_fns
 471         .size   __arm1026_proc_info, . - __arm1026_proc_info