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ARM: vexpress: Initial common clock support
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-vexpress / v2m.c
1 /*
2 * Versatile Express V2M Motherboard Support
3 */
4 #include <linux/device.h>
5 #include <linux/amba/bus.h>
6 #include <linux/amba/mmci.h>
7 #include <linux/io.h>
8 #include <linux/init.h>
9 #include <linux/of_address.h>
10 #include <linux/of_fdt.h>
11 #include <linux/of_irq.h>
12 #include <linux/of_platform.h>
13 #include <linux/platform_device.h>
14 #include <linux/ata_platform.h>
15 #include <linux/smsc911x.h>
16 #include <linux/spinlock.h>
17 #include <linux/usb/isp1760.h>
18 #include <linux/clkdev.h>
19 #include <linux/clk-provider.h>
20 #include <linux/mtd/physmap.h>
21
22 #include <asm/arch_timer.h>
23 #include <asm/mach-types.h>
24 #include <asm/sizes.h>
25 #include <asm/smp_twd.h>
26 #include <asm/mach/arch.h>
27 #include <asm/mach/map.h>
28 #include <asm/mach/time.h>
29 #include <asm/hardware/arm_timer.h>
30 #include <asm/hardware/cache-l2x0.h>
31 #include <asm/hardware/gic.h>
32 #include <asm/hardware/timer-sp.h>
33 #include <asm/hardware/sp810.h>
34
35 #include <mach/ct-ca9x4.h>
36 #include <mach/motherboard.h>
37
38 #include <plat/sched_clock.h>
39
40 #include "core.h"
41
42 #define V2M_PA_CS0 0x40000000
43 #define V2M_PA_CS1 0x44000000
44 #define V2M_PA_CS2 0x48000000
45 #define V2M_PA_CS3 0x4c000000
46 #define V2M_PA_CS7 0x10000000
47
48 static struct map_desc v2m_io_desc[] __initdata = {
49 {
50 .virtual = V2M_PERIPH,
51 .pfn = __phys_to_pfn(V2M_PA_CS7),
52 .length = SZ_128K,
53 .type = MT_DEVICE,
54 },
55 };
56
57 static void __iomem *v2m_sysreg_base;
58
59 static void __init v2m_sysctl_init(void __iomem *base)
60 {
61 u32 scctrl;
62
63 if (WARN_ON(!base))
64 return;
65
66 /* Select 1MHz TIMCLK as the reference clock for SP804 timers */
67 scctrl = readl(base + SCCTRL);
68 scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
69 scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
70 writel(scctrl, base + SCCTRL);
71 }
72
73 static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
74 {
75 if (WARN_ON(!base || irq == NO_IRQ))
76 return;
77
78 writel(0, base + TIMER_1_BASE + TIMER_CTRL);
79 writel(0, base + TIMER_2_BASE + TIMER_CTRL);
80
81 sp804_clocksource_init(base + TIMER_2_BASE, "v2m-timer1");
82 sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
83 }
84
85
86 static DEFINE_SPINLOCK(v2m_cfg_lock);
87
88 int v2m_cfg_write(u32 devfn, u32 data)
89 {
90 /* Configuration interface broken? */
91 u32 val;
92
93 printk("%s: writing %08x to %08x\n", __func__, data, devfn);
94
95 devfn |= SYS_CFG_START | SYS_CFG_WRITE;
96
97 spin_lock(&v2m_cfg_lock);
98 val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
99 writel(val & ~SYS_CFG_COMPLETE, v2m_sysreg_base + V2M_SYS_CFGSTAT);
100
101 writel(data, v2m_sysreg_base + V2M_SYS_CFGDATA);
102 writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
103
104 do {
105 val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
106 } while (val == 0);
107 spin_unlock(&v2m_cfg_lock);
108
109 return !!(val & SYS_CFG_ERR);
110 }
111
112 int v2m_cfg_read(u32 devfn, u32 *data)
113 {
114 u32 val;
115
116 devfn |= SYS_CFG_START;
117
118 spin_lock(&v2m_cfg_lock);
119 writel(0, v2m_sysreg_base + V2M_SYS_CFGSTAT);
120 writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
121
122 mb();
123
124 do {
125 cpu_relax();
126 val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
127 } while (val == 0);
128
129 *data = readl(v2m_sysreg_base + V2M_SYS_CFGDATA);
130 spin_unlock(&v2m_cfg_lock);
131
132 return !!(val & SYS_CFG_ERR);
133 }
134
135 void __init v2m_flags_set(u32 data)
136 {
137 writel(~0, v2m_sysreg_base + V2M_SYS_FLAGSCLR);
138 writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET);
139 }
140
141 int v2m_get_master_site(void)
142 {
143 u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
144
145 return misc & SYS_MISC_MASTERSITE ? SYS_CFG_SITE_DB2 : SYS_CFG_SITE_DB1;
146 }
147
148
149 static struct resource v2m_pcie_i2c_resource = {
150 .start = V2M_SERIAL_BUS_PCI,
151 .end = V2M_SERIAL_BUS_PCI + SZ_4K - 1,
152 .flags = IORESOURCE_MEM,
153 };
154
155 static struct platform_device v2m_pcie_i2c_device = {
156 .name = "versatile-i2c",
157 .id = 0,
158 .num_resources = 1,
159 .resource = &v2m_pcie_i2c_resource,
160 };
161
162 static struct resource v2m_ddc_i2c_resource = {
163 .start = V2M_SERIAL_BUS_DVI,
164 .end = V2M_SERIAL_BUS_DVI + SZ_4K - 1,
165 .flags = IORESOURCE_MEM,
166 };
167
168 static struct platform_device v2m_ddc_i2c_device = {
169 .name = "versatile-i2c",
170 .id = 1,
171 .num_resources = 1,
172 .resource = &v2m_ddc_i2c_resource,
173 };
174
175 static struct resource v2m_eth_resources[] = {
176 {
177 .start = V2M_LAN9118,
178 .end = V2M_LAN9118 + SZ_64K - 1,
179 .flags = IORESOURCE_MEM,
180 }, {
181 .start = IRQ_V2M_LAN9118,
182 .end = IRQ_V2M_LAN9118,
183 .flags = IORESOURCE_IRQ,
184 },
185 };
186
187 static struct smsc911x_platform_config v2m_eth_config = {
188 .flags = SMSC911X_USE_32BIT,
189 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
190 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
191 .phy_interface = PHY_INTERFACE_MODE_MII,
192 };
193
194 static struct platform_device v2m_eth_device = {
195 .name = "smsc911x",
196 .id = -1,
197 .resource = v2m_eth_resources,
198 .num_resources = ARRAY_SIZE(v2m_eth_resources),
199 .dev.platform_data = &v2m_eth_config,
200 };
201
202 static struct resource v2m_usb_resources[] = {
203 {
204 .start = V2M_ISP1761,
205 .end = V2M_ISP1761 + SZ_128K - 1,
206 .flags = IORESOURCE_MEM,
207 }, {
208 .start = IRQ_V2M_ISP1761,
209 .end = IRQ_V2M_ISP1761,
210 .flags = IORESOURCE_IRQ,
211 },
212 };
213
214 static struct isp1760_platform_data v2m_usb_config = {
215 .is_isp1761 = true,
216 .bus_width_16 = false,
217 .port1_otg = true,
218 .analog_oc = false,
219 .dack_polarity_high = false,
220 .dreq_polarity_high = false,
221 };
222
223 static struct platform_device v2m_usb_device = {
224 .name = "isp1760",
225 .id = -1,
226 .resource = v2m_usb_resources,
227 .num_resources = ARRAY_SIZE(v2m_usb_resources),
228 .dev.platform_data = &v2m_usb_config,
229 };
230
231 static void v2m_flash_set_vpp(struct platform_device *pdev, int on)
232 {
233 writel(on != 0, v2m_sysreg_base + V2M_SYS_FLASH);
234 }
235
236 static struct physmap_flash_data v2m_flash_data = {
237 .width = 4,
238 .set_vpp = v2m_flash_set_vpp,
239 };
240
241 static struct resource v2m_flash_resources[] = {
242 {
243 .start = V2M_NOR0,
244 .end = V2M_NOR0 + SZ_64M - 1,
245 .flags = IORESOURCE_MEM,
246 }, {
247 .start = V2M_NOR1,
248 .end = V2M_NOR1 + SZ_64M - 1,
249 .flags = IORESOURCE_MEM,
250 },
251 };
252
253 static struct platform_device v2m_flash_device = {
254 .name = "physmap-flash",
255 .id = -1,
256 .resource = v2m_flash_resources,
257 .num_resources = ARRAY_SIZE(v2m_flash_resources),
258 .dev.platform_data = &v2m_flash_data,
259 };
260
261 static struct pata_platform_info v2m_pata_data = {
262 .ioport_shift = 2,
263 };
264
265 static struct resource v2m_pata_resources[] = {
266 {
267 .start = V2M_CF,
268 .end = V2M_CF + 0xff,
269 .flags = IORESOURCE_MEM,
270 }, {
271 .start = V2M_CF + 0x100,
272 .end = V2M_CF + SZ_4K - 1,
273 .flags = IORESOURCE_MEM,
274 },
275 };
276
277 static struct platform_device v2m_cf_device = {
278 .name = "pata_platform",
279 .id = -1,
280 .resource = v2m_pata_resources,
281 .num_resources = ARRAY_SIZE(v2m_pata_resources),
282 .dev.platform_data = &v2m_pata_data,
283 };
284
285 static unsigned int v2m_mmci_status(struct device *dev)
286 {
287 return readl(v2m_sysreg_base + V2M_SYS_MCI) & (1 << 0);
288 }
289
290 static struct mmci_platform_data v2m_mmci_data = {
291 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
292 .status = v2m_mmci_status,
293 };
294
295 static AMBA_APB_DEVICE(aaci, "mb:aaci", 0, V2M_AACI, IRQ_V2M_AACI, NULL);
296 static AMBA_APB_DEVICE(mmci, "mb:mmci", 0, V2M_MMCI, IRQ_V2M_MMCI, &v2m_mmci_data);
297 static AMBA_APB_DEVICE(kmi0, "mb:kmi0", 0, V2M_KMI0, IRQ_V2M_KMI0, NULL);
298 static AMBA_APB_DEVICE(kmi1, "mb:kmi1", 0, V2M_KMI1, IRQ_V2M_KMI1, NULL);
299 static AMBA_APB_DEVICE(uart0, "mb:uart0", 0, V2M_UART0, IRQ_V2M_UART0, NULL);
300 static AMBA_APB_DEVICE(uart1, "mb:uart1", 0, V2M_UART1, IRQ_V2M_UART1, NULL);
301 static AMBA_APB_DEVICE(uart2, "mb:uart2", 0, V2M_UART2, IRQ_V2M_UART2, NULL);
302 static AMBA_APB_DEVICE(uart3, "mb:uart3", 0, V2M_UART3, IRQ_V2M_UART3, NULL);
303 static AMBA_APB_DEVICE(wdt, "mb:wdt", 0, V2M_WDT, IRQ_V2M_WDT, NULL);
304 static AMBA_APB_DEVICE(rtc, "mb:rtc", 0, V2M_RTC, IRQ_V2M_RTC, NULL);
305
306 static struct amba_device *v2m_amba_devs[] __initdata = {
307 &aaci_device,
308 &mmci_device,
309 &kmi0_device,
310 &kmi1_device,
311 &uart0_device,
312 &uart1_device,
313 &uart2_device,
314 &uart3_device,
315 &wdt_device,
316 &rtc_device,
317 };
318
319
320 static unsigned long v2m_osc_recalc_rate(struct clk_hw *hw,
321 unsigned long parent_rate)
322 {
323 struct v2m_osc *osc = to_v2m_osc(hw);
324
325 return !parent_rate ? osc->rate_default : parent_rate;
326 }
327
328 static long v2m_osc_round_rate(struct clk_hw *hw, unsigned long rate,
329 unsigned long *parent_rate)
330 {
331 struct v2m_osc *osc = to_v2m_osc(hw);
332
333 if (WARN_ON(rate < osc->rate_min))
334 rate = osc->rate_min;
335
336 if (WARN_ON(rate > osc->rate_max))
337 rate = osc->rate_max;
338
339 return rate;
340 }
341
342 static int v2m_osc_set_rate(struct clk_hw *hw, unsigned long rate,
343 unsigned long parent_rate)
344 {
345 struct v2m_osc *osc = to_v2m_osc(hw);
346
347 v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(osc->site) |
348 SYS_CFG_STACK(osc->stack) | osc->osc, rate);
349
350 return 0;
351 }
352
353 static struct clk_ops v2m_osc_ops = {
354 .recalc_rate = v2m_osc_recalc_rate,
355 .round_rate = v2m_osc_round_rate,
356 .set_rate = v2m_osc_set_rate,
357 };
358
359 struct clk * __init v2m_osc_register(const char *name, struct v2m_osc *osc)
360 {
361 struct clk_init_data init;
362
363 WARN_ON(osc->site > 2);
364 WARN_ON(osc->stack > 15);
365 WARN_ON(osc->osc > 4095);
366
367 init.name = name;
368 init.ops = &v2m_osc_ops;
369 init.flags = CLK_IS_ROOT;
370 init.num_parents = 0;
371
372 osc->hw.init = &init;
373
374 return clk_register(NULL, &osc->hw);
375 }
376
377 static struct v2m_osc v2m_mb_osc1 = {
378 .site = SYS_CFG_SITE_MB,
379 .osc = 1,
380 .rate_min = 23750000,
381 .rate_max = 63500000,
382 .rate_default = 23750000,
383 };
384
385 static const char *v2m_ref_clk_periphs[] __initconst = {
386 "mb:wdt", "1000f000.wdt", "1c0f0000.wdt", /* SP805 WDT */
387 };
388
389 static const char *v2m_osc1_periphs[] __initconst = {
390 "mb:clcd", "1001f000.clcd", "1c1f0000.clcd", /* PL111 CLCD */
391 };
392
393 static const char *v2m_osc2_periphs[] __initconst = {
394 "mb:mmci", "10005000.mmci", "1c050000.mmci", /* PL180 MMCI */
395 "mb:kmi0", "10006000.kmi", "1c060000.kmi", /* PL050 KMI0 */
396 "mb:kmi1", "10007000.kmi", "1c070000.kmi", /* PL050 KMI1 */
397 "mb:uart0", "10009000.uart", "1c090000.uart", /* PL011 UART0 */
398 "mb:uart1", "1000a000.uart", "1c0a0000.uart", /* PL011 UART1 */
399 "mb:uart2", "1000b000.uart", "1c0b0000.uart", /* PL011 UART2 */
400 "mb:uart3", "1000c000.uart", "1c0c0000.uart", /* PL011 UART3 */
401 };
402
403 static void __init v2m_clk_init(void)
404 {
405 struct clk *clk;
406 int i;
407
408 clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL,
409 CLK_IS_ROOT, 0);
410 WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL));
411
412 clk = clk_register_fixed_rate(NULL, "mb:ref_clk", NULL,
413 CLK_IS_ROOT, 32768);
414 for (i = 0; i < ARRAY_SIZE(v2m_ref_clk_periphs); i++)
415 WARN_ON(clk_register_clkdev(clk, NULL, v2m_ref_clk_periphs[i]));
416
417 clk = clk_register_fixed_rate(NULL, "mb:sp804_clk", NULL,
418 CLK_IS_ROOT, 1000000);
419 WARN_ON(clk_register_clkdev(clk, "v2m-timer0", "sp804"));
420 WARN_ON(clk_register_clkdev(clk, "v2m-timer1", "sp804"));
421
422 clk = v2m_osc_register("mb:osc1", &v2m_mb_osc1);
423 for (i = 0; i < ARRAY_SIZE(v2m_osc1_periphs); i++)
424 WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc1_periphs[i]));
425
426 clk = clk_register_fixed_rate(NULL, "mb:osc2", NULL,
427 CLK_IS_ROOT, 24000000);
428 for (i = 0; i < ARRAY_SIZE(v2m_osc2_periphs); i++)
429 WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc2_periphs[i]));
430 }
431
432 static void __init v2m_timer_init(void)
433 {
434 v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
435 v2m_clk_init();
436 v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
437 }
438
439 static struct sys_timer v2m_timer = {
440 .init = v2m_timer_init,
441 };
442
443 static void __init v2m_init_early(void)
444 {
445 if (ct_desc->init_early)
446 ct_desc->init_early();
447 versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
448 }
449
450 static void v2m_power_off(void)
451 {
452 if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
453 printk(KERN_EMERG "Unable to shutdown\n");
454 }
455
456 static void v2m_restart(char str, const char *cmd)
457 {
458 if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
459 printk(KERN_EMERG "Unable to reboot\n");
460 }
461
462 struct ct_desc *ct_desc;
463
464 static struct ct_desc *ct_descs[] __initdata = {
465 #ifdef CONFIG_ARCH_VEXPRESS_CA9X4
466 &ct_ca9x4_desc,
467 #endif
468 };
469
470 static void __init v2m_populate_ct_desc(void)
471 {
472 int i;
473 u32 current_tile_id;
474
475 ct_desc = NULL;
476 current_tile_id = readl(v2m_sysreg_base + V2M_SYS_PROCID0)
477 & V2M_CT_ID_MASK;
478
479 for (i = 0; i < ARRAY_SIZE(ct_descs) && !ct_desc; ++i)
480 if (ct_descs[i]->id == current_tile_id)
481 ct_desc = ct_descs[i];
482
483 if (!ct_desc)
484 panic("vexpress: this kernel does not support core tile ID 0x%08x when booting via ATAGs.\n"
485 "You may need a device tree blob or a different kernel to boot on this board.\n",
486 current_tile_id);
487 }
488
489 static void __init v2m_map_io(void)
490 {
491 iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
492 v2m_sysreg_base = ioremap(V2M_SYSREGS, SZ_4K);
493 v2m_populate_ct_desc();
494 ct_desc->map_io();
495 }
496
497 static void __init v2m_init_irq(void)
498 {
499 ct_desc->init_irq();
500 }
501
502 static void __init v2m_init(void)
503 {
504 int i;
505
506 platform_device_register(&v2m_pcie_i2c_device);
507 platform_device_register(&v2m_ddc_i2c_device);
508 platform_device_register(&v2m_flash_device);
509 platform_device_register(&v2m_cf_device);
510 platform_device_register(&v2m_eth_device);
511 platform_device_register(&v2m_usb_device);
512
513 for (i = 0; i < ARRAY_SIZE(v2m_amba_devs); i++)
514 amba_device_register(v2m_amba_devs[i], &iomem_resource);
515
516 pm_power_off = v2m_power_off;
517
518 ct_desc->init_tile();
519 }
520
521 MACHINE_START(VEXPRESS, "ARM-Versatile Express")
522 .atag_offset = 0x100,
523 .map_io = v2m_map_io,
524 .init_early = v2m_init_early,
525 .init_irq = v2m_init_irq,
526 .timer = &v2m_timer,
527 .handle_irq = gic_handle_irq,
528 .init_machine = v2m_init,
529 .restart = v2m_restart,
530 MACHINE_END
531
532 #if defined(CONFIG_ARCH_VEXPRESS_DT)
533
534 static struct map_desc v2m_rs1_io_desc __initdata = {
535 .virtual = V2M_PERIPH,
536 .pfn = __phys_to_pfn(0x1c000000),
537 .length = SZ_2M,
538 .type = MT_DEVICE,
539 };
540
541 static int __init v2m_dt_scan_memory_map(unsigned long node, const char *uname,
542 int depth, void *data)
543 {
544 const char **map = data;
545
546 if (strcmp(uname, "motherboard") != 0)
547 return 0;
548
549 *map = of_get_flat_dt_prop(node, "arm,v2m-memory-map", NULL);
550
551 return 1;
552 }
553
554 void __init v2m_dt_map_io(void)
555 {
556 const char *map = NULL;
557
558 of_scan_flat_dt(v2m_dt_scan_memory_map, &map);
559
560 if (map && strcmp(map, "rs1") == 0)
561 iotable_init(&v2m_rs1_io_desc, 1);
562 else
563 iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
564
565 #if defined(CONFIG_SMP)
566 vexpress_dt_smp_map_io();
567 #endif
568 }
569
570 void __init v2m_dt_init_early(void)
571 {
572 struct device_node *node;
573 u32 dt_hbi;
574
575 node = of_find_compatible_node(NULL, NULL, "arm,vexpress-sysreg");
576 v2m_sysreg_base = of_iomap(node, 0);
577 if (WARN_ON(!v2m_sysreg_base))
578 return;
579
580 /* Confirm board type against DT property, if available */
581 if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) {
582 int site = v2m_get_master_site();
583 u32 id = readl(v2m_sysreg_base + (site == SYS_CFG_SITE_DB2 ?
584 V2M_SYS_PROCID1 : V2M_SYS_PROCID0));
585 u32 hbi = id & SYS_PROCIDx_HBI_MASK;
586
587 if (WARN_ON(dt_hbi != hbi))
588 pr_warning("vexpress: DT HBI (%x) is not matching "
589 "hardware (%x)!\n", dt_hbi, hbi);
590 }
591 }
592
593 static struct of_device_id vexpress_irq_match[] __initdata = {
594 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
595 {}
596 };
597
598 static void __init v2m_dt_init_irq(void)
599 {
600 of_irq_init(vexpress_irq_match);
601 }
602
603 static void __init v2m_dt_timer_init(void)
604 {
605 struct device_node *node;
606 const char *path;
607 int err;
608
609 node = of_find_compatible_node(NULL, NULL, "arm,sp810");
610 v2m_sysctl_init(of_iomap(node, 0));
611
612 v2m_clk_init();
613
614 err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
615 if (WARN_ON(err))
616 return;
617 node = of_find_node_by_path(path);
618 v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
619 if (arch_timer_of_register() != 0)
620 twd_local_timer_of_register();
621
622 if (arch_timer_sched_clock_init() != 0)
623 versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
624 }
625
626 static struct sys_timer v2m_dt_timer = {
627 .init = v2m_dt_timer_init,
628 };
629
630 static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
631 OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
632 &v2m_flash_data),
633 OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
634 /* RS1 memory map */
635 OF_DEV_AUXDATA("arm,vexpress-flash", 0x08000000, "physmap-flash",
636 &v2m_flash_data),
637 OF_DEV_AUXDATA("arm,primecell", 0x1c050000, "mb:mmci", &v2m_mmci_data),
638 {}
639 };
640
641 static void __init v2m_dt_init(void)
642 {
643 l2x0_of_init(0x00400000, 0xfe0fffff);
644 of_platform_populate(NULL, of_default_bus_match_table,
645 v2m_dt_auxdata_lookup, NULL);
646 pm_power_off = v2m_power_off;
647 }
648
649 const static char *v2m_dt_match[] __initconst = {
650 "arm,vexpress",
651 NULL,
652 };
653
654 DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
655 .dt_compat = v2m_dt_match,
656 .map_io = v2m_dt_map_io,
657 .init_early = v2m_dt_init_early,
658 .init_irq = v2m_dt_init_irq,
659 .timer = &v2m_dt_timer,
660 .init_machine = v2m_dt_init,
661 .handle_irq = gic_handle_irq,
662 .restart = v2m_restart,
663 MACHINE_END
664
665 #endif
kernel source for telekom puls (alcatel/mediatek)