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f3976f9c404a1bb04da0850badc3e17e421e8790
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-ux500 / board-mop500-pins.c
1 /*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/init.h>
9 #include <linux/bug.h>
10 #include <linux/string.h>
11 #include <linux/pinctrl/machine.h>
12 #include <linux/platform_data/pinctrl-nomadik.h>
13
14 #include <asm/mach-types.h>
15
16 #include "pins-db8500.h"
17 #include "board-mop500.h"
18
19 enum custom_pin_cfg_t {
20 PINS_FOR_DEFAULT,
21 PINS_FOR_U9500,
22 };
23
24 static enum custom_pin_cfg_t pinsfor;
25
26 /* These simply sets bias for pins */
27 #define BIAS(a,b) static unsigned long a[] = { b }
28
29 BIAS(pd, PIN_PULL_DOWN);
30 BIAS(in_nopull, PIN_INPUT_NOPULL);
31 BIAS(in_nopull_slpm_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
32 BIAS(in_pu, PIN_INPUT_PULLUP);
33 BIAS(in_pd, PIN_INPUT_PULLDOWN);
34 BIAS(out_hi, PIN_OUTPUT_HIGH);
35 BIAS(out_lo, PIN_OUTPUT_LOW);
36 BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
37 /* These also force them into GPIO mode */
38 BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
39 BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
40 BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
41 BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
42 BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
43 BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
44 /* Sleep modes */
45 BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED|
46 PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE);
47 BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
48 PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
49 BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|
50 PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
51 BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
52 PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
53 BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED|
54 PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
55 BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|
56 PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
57 BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|
58 PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
59 BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED|
60 PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
61 BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP|
62 PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
63 BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED|
64 PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
65 BIAS(out_lo_wkup_pdis, PIN_SLPM_OUTPUT_LOW|
66 PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
67 BIAS(in_wkup_pdis_en, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
68 PIN_SLPM_PDIS_ENABLED);
69 BIAS(in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
70 PIN_SLPM_PDIS_DISABLED);
71 BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
72 PIN_SLPM_PDIS_DISABLED);
73
74 /* We use these to define hog settings that are always done on boot */
75 #define DB8500_MUX_HOG(group,func) \
76 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
77 #define DB8500_PIN_HOG(pin,conf) \
78 PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
79 #define DB8500_PIN_SLEEP(pin, conf, dev) \
80 PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
81 pin, conf)
82
83 /* These are default states associated with device and changed runtime */
84 #define DB8500_MUX(group,func,dev) \
85 PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
86 #define DB8500_PIN(pin,conf,dev) \
87 PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
88 #define DB8500_PIN_IDLE(pin, conf, dev) \
89 PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_IDLE, "pinctrl-db8500", \
90 pin, conf)
91 #define DB8500_PIN_SLEEP(pin, conf, dev) \
92 PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
93 pin, conf)
94 #define DB8500_MUX_STATE(group, func, dev, state) \
95 PIN_MAP_MUX_GROUP(dev, state, "pinctrl-db8500", group, func)
96 #define DB8500_PIN_STATE(pin, conf, dev, state) \
97 PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf)
98
99 /* Pin control settings */
100 static struct pinctrl_map __initdata mop500_family_pinmap[] = {
101 /*
102 * uMSP0, mux in 4 pins, regular placement of RX/TX
103 * explicitly set the pins to no pull
104 */
105 DB8500_MUX_HOG("msp0txrx_a_1", "msp0"),
106 DB8500_MUX_HOG("msp0tfstck_a_1", "msp0"),
107 DB8500_PIN_HOG("GPIO12_AC4", in_nopull), /* TXD */
108 DB8500_PIN_HOG("GPIO15_AC3", in_nopull), /* RXD */
109 DB8500_PIN_HOG("GPIO13_AF3", in_nopull), /* TFS */
110 DB8500_PIN_HOG("GPIO14_AE3", in_nopull), /* TCK */
111 /* MSP2 for HDMI, pull down TXD, TCK, TFS */
112 DB8500_MUX_HOG("msp2_a_1", "msp2"),
113 DB8500_PIN_HOG("GPIO193_AH27", in_pd), /* TXD */
114 DB8500_PIN_HOG("GPIO194_AF27", in_pd), /* TCK */
115 DB8500_PIN_HOG("GPIO195_AG28", in_pd), /* TFS */
116 DB8500_PIN_HOG("GPIO196_AG26", out_lo), /* RXD */
117 /*
118 * LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to
119 * pull-up
120 * TODO: is this really correct? Snowball doesn't have a LCD.
121 */
122 DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"),
123 DB8500_PIN_HOG("GPIO68_E1", in_pu),
124 DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu),
125 /*
126 * STMPE1601/tc35893 keypad IRQ GPIO 218
127 * TODO: set for snowball and HREF really??
128 */
129 DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu),
130 /*
131 * UART0, we do not mux in u0 here.
132 * uart-0 pins gpio configuration should be kept intact to prevent
133 * a glitch in tx line when the tty dev is opened. Later these pins
134 * are configured by uart driver
135 */
136 DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */
137 DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */
138 DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */
139 DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */
140 /*
141 * Mux in UART2 on altfunction C and set pull-ups.
142 * TODO: is this used on U8500 variants and Snowball really?
143 * The setting on GPIO31 conflicts with magnetometer use on hrefv60
144 */
145 /* default state for UART2 */
146 DB8500_MUX("u2rxtx_c_1", "u2", "uart2"),
147 DB8500_PIN("GPIO29_W2", in_pu, "uart2"), /* RXD */
148 DB8500_PIN("GPIO30_W3", out_hi, "uart2"), /* TXD */
149 /* Sleep state for UART2 */
150 DB8500_PIN_SLEEP("GPIO29_W2", in_wkup_pdis, "uart2"),
151 DB8500_PIN_SLEEP("GPIO30_W3", out_wkup_pdis, "uart2"),
152 /*
153 * The following pin sets were known as "runtime pins" before being
154 * converted to the pinctrl model. Here we model them as "default"
155 * states.
156 */
157 /* Mux in UART0 after initialization */
158 DB8500_MUX("u0_a_1", "u0", "uart0"),
159 DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */
160 DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */
161 DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
162 DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
163 /* Sleep state for UART0 */
164 DB8500_PIN_SLEEP("GPIO0_AJ5", slpm_in_wkup_pdis, "uart0"),
165 DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"),
166 DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"),
167 DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"),
168 /* Mux in UART1 after initialization */
169 DB8500_MUX("u1rxtx_a_1", "u1", "uart1"),
170 DB8500_PIN("GPIO4_AH6", in_pu, "uart1"), /* RXD */
171 DB8500_PIN("GPIO5_AG6", out_hi, "uart1"), /* TXD */
172 /* Sleep state for UART1 */
173 DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"),
174 DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"),
175 /* MSP1 for ALSA codec */
176 DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
177 DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
178 DB8500_PIN("GPIO33_AF2", out_lo_slpm_nowkup, "ux500-msp-i2s.1"),
179 DB8500_PIN("GPIO34_AE1", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
180 DB8500_PIN("GPIO35_AE2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
181 DB8500_PIN("GPIO36_AG2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
182 /* MSP1 sleep state */
183 DB8500_PIN_SLEEP("GPIO33_AF2", slpm_out_lo_wkup, "ux500-msp-i2s.1"),
184 DB8500_PIN_SLEEP("GPIO34_AE1", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
185 DB8500_PIN_SLEEP("GPIO35_AE2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
186 DB8500_PIN_SLEEP("GPIO36_AG2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
187 /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
188 DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
189 DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
190 /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
191 DB8500_MUX("lcdvsi1_a_1", "lcd", "0-0070"),
192 DB8500_PIN("GPIO69_E2", in_pu, "0-0070"),
193 /* LCD VSI1 sleep state */
194 DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"),
195 /* Mux in i2c0 block, default state */
196 DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
197 /* i2c0 sleep state */
198 DB8500_PIN_SLEEP("GPIO147_C15", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SDA */
199 DB8500_PIN_SLEEP("GPIO148_B16", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SCL */
200 /* Mux in i2c1 block, default state */
201 DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
202 /* i2c1 sleep state */
203 DB8500_PIN_SLEEP("GPIO16_AD3", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SDA */
204 DB8500_PIN_SLEEP("GPIO17_AD4", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SCL */
205 /* Mux in i2c2 block, default state */
206 DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
207 /* i2c2 sleep state */
208 DB8500_PIN_SLEEP("GPIO10_AF5", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SDA */
209 DB8500_PIN_SLEEP("GPIO11_AG4", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SCL */
210 /* Mux in i2c3 block, default state */
211 DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
212 /* i2c3 sleep state */
213 DB8500_PIN_SLEEP("GPIO229_AG7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SDA */
214 DB8500_PIN_SLEEP("GPIO230_AF7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SCL */
215 /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
216 DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
217 DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
218 DB8500_PIN("GPIO19_AC1", out_hi, "sdi0"), /* DAT0DIR */
219 DB8500_PIN("GPIO20_AB4", out_hi, "sdi0"), /* DAT2DIR */
220 DB8500_PIN("GPIO22_AA3", in_nopull, "sdi0"), /* FBCLK */
221 DB8500_PIN("GPIO23_AA4", out_lo, "sdi0"), /* CLK */
222 DB8500_PIN("GPIO24_AB2", in_pu, "sdi0"), /* CMD */
223 DB8500_PIN("GPIO25_Y4", in_pu, "sdi0"), /* DAT0 */
224 DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */
225 DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */
226 DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */
227 /* SDI0 sleep state */
228 DB8500_PIN_SLEEP("GPIO18_AC2", slpm_out_hi_wkup_pdis, "sdi0"),
229 DB8500_PIN_SLEEP("GPIO19_AC1", slpm_out_hi_wkup_pdis, "sdi0"),
230 DB8500_PIN_SLEEP("GPIO20_AB4", slpm_out_hi_wkup_pdis, "sdi0"),
231 DB8500_PIN_SLEEP("GPIO22_AA3", slpm_in_wkup_pdis, "sdi0"),
232 DB8500_PIN_SLEEP("GPIO23_AA4", slpm_out_lo_wkup_pdis, "sdi0"),
233 DB8500_PIN_SLEEP("GPIO24_AB2", slpm_in_wkup_pdis, "sdi0"),
234 DB8500_PIN_SLEEP("GPIO25_Y4", slpm_in_wkup_pdis, "sdi0"),
235 DB8500_PIN_SLEEP("GPIO26_Y2", slpm_in_wkup_pdis, "sdi0"),
236 DB8500_PIN_SLEEP("GPIO27_AA2", slpm_in_wkup_pdis, "sdi0"),
237 DB8500_PIN_SLEEP("GPIO28_AA1", slpm_in_wkup_pdis, "sdi0"),
238
239 /* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */
240 DB8500_MUX("mc1_a_1", "mc1", "sdi1"),
241 DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */
242 DB8500_PIN("GPIO209_AG15", in_nopull, "sdi1"), /* FBCLK */
243 DB8500_PIN("GPIO210_AJ15", in_pu, "sdi1"), /* CMD */
244 DB8500_PIN("GPIO211_AG14", in_pu, "sdi1"), /* DAT0 */
245 DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */
246 DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */
247 DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */
248 /* SDI1 sleep state */
249 DB8500_PIN_SLEEP("GPIO208_AH16", slpm_out_lo_wkup_pdis, "sdi1"), /* CLK */
250 DB8500_PIN_SLEEP("GPIO209_AG15", slpm_in_wkup_pdis, "sdi1"), /* FBCLK */
251 DB8500_PIN_SLEEP("GPIO210_AJ15", slpm_in_wkup_pdis, "sdi1"), /* CMD */
252 DB8500_PIN_SLEEP("GPIO211_AG14", slpm_in_wkup_pdis, "sdi1"), /* DAT0 */
253 DB8500_PIN_SLEEP("GPIO212_AF13", slpm_in_wkup_pdis, "sdi1"), /* DAT1 */
254 DB8500_PIN_SLEEP("GPIO213_AG13", slpm_in_wkup_pdis, "sdi1"), /* DAT2 */
255 DB8500_PIN_SLEEP("GPIO214_AH15", slpm_in_wkup_pdis, "sdi1"), /* DAT3 */
256
257 /* Mux in SDI2 (here called MC2) used for for PoP eMMC */
258 DB8500_MUX("mc2_a_1", "mc2", "sdi2"),
259 DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */
260 DB8500_PIN("GPIO129_B4", in_pu, "sdi2"), /* CMD */
261 DB8500_PIN("GPIO130_C8", in_nopull, "sdi2"), /* FBCLK */
262 DB8500_PIN("GPIO131_A12", in_pu, "sdi2"), /* DAT0 */
263 DB8500_PIN("GPIO132_C10", in_pu, "sdi2"), /* DAT1 */
264 DB8500_PIN("GPIO133_B10", in_pu, "sdi2"), /* DAT2 */
265 DB8500_PIN("GPIO134_B9", in_pu, "sdi2"), /* DAT3 */
266 DB8500_PIN("GPIO135_A9", in_pu, "sdi2"), /* DAT4 */
267 DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */
268 DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */
269 DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */
270 /* SDI2 sleep state */
271 DB8500_PIN_SLEEP("GPIO128_A5", out_lo_wkup_pdis, "sdi2"), /* CLK */
272 DB8500_PIN_SLEEP("GPIO129_B4", in_wkup_pdis_en, "sdi2"), /* CMD */
273 DB8500_PIN_SLEEP("GPIO130_C8", in_wkup_pdis_en, "sdi2"), /* FBCLK */
274 DB8500_PIN_SLEEP("GPIO131_A12", in_wkup_pdis, "sdi2"), /* DAT0 */
275 DB8500_PIN_SLEEP("GPIO132_C10", in_wkup_pdis, "sdi2"), /* DAT1 */
276 DB8500_PIN_SLEEP("GPIO133_B10", in_wkup_pdis, "sdi2"), /* DAT2 */
277 DB8500_PIN_SLEEP("GPIO134_B9", in_wkup_pdis, "sdi2"), /* DAT3 */
278 DB8500_PIN_SLEEP("GPIO135_A9", in_wkup_pdis, "sdi2"), /* DAT4 */
279 DB8500_PIN_SLEEP("GPIO136_C7", in_wkup_pdis, "sdi2"), /* DAT5 */
280 DB8500_PIN_SLEEP("GPIO137_A7", in_wkup_pdis, "sdi2"), /* DAT6 */
281 DB8500_PIN_SLEEP("GPIO138_C5", in_wkup_pdis, "sdi2"), /* DAT7 */
282
283 /* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */
284 DB8500_MUX("mc4_a_1", "mc4", "sdi4"),
285 DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */
286 DB8500_PIN("GPIO198_AG25", in_pu, "sdi4"), /* DAT2 */
287 DB8500_PIN("GPIO199_AH23", in_pu, "sdi4"), /* DAT1 */
288 DB8500_PIN("GPIO200_AH26", in_pu, "sdi4"), /* DAT0 */
289 DB8500_PIN("GPIO201_AF24", in_pu, "sdi4"), /* CMD */
290 DB8500_PIN("GPIO202_AF25", in_nopull, "sdi4"), /* FBCLK */
291 DB8500_PIN("GPIO203_AE23", out_lo, "sdi4"), /* CLK */
292 DB8500_PIN("GPIO204_AF23", in_pu, "sdi4"), /* DAT7 */
293 DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */
294 DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */
295 DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */
296 /*SDI4 sleep state */
297 DB8500_PIN_SLEEP("GPIO197_AH24", slpm_in_wkup_pdis, "sdi4"), /* DAT3 */
298 DB8500_PIN_SLEEP("GPIO198_AG25", slpm_in_wkup_pdis, "sdi4"), /* DAT2 */
299 DB8500_PIN_SLEEP("GPIO199_AH23", slpm_in_wkup_pdis, "sdi4"), /* DAT1 */
300 DB8500_PIN_SLEEP("GPIO200_AH26", slpm_in_wkup_pdis, "sdi4"), /* DAT0 */
301 DB8500_PIN_SLEEP("GPIO201_AF24", slpm_in_wkup_pdis, "sdi4"), /* CMD */
302 DB8500_PIN_SLEEP("GPIO202_AF25", slpm_in_wkup_pdis, "sdi4"), /* FBCLK */
303 DB8500_PIN_SLEEP("GPIO203_AE23", slpm_out_lo_wkup_pdis, "sdi4"), /* CLK */
304 DB8500_PIN_SLEEP("GPIO204_AF23", slpm_in_wkup_pdis, "sdi4"), /* DAT7 */
305 DB8500_PIN_SLEEP("GPIO205_AG23", slpm_in_wkup_pdis, "sdi4"), /* DAT6 */
306 DB8500_PIN_SLEEP("GPIO206_AG24", slpm_in_wkup_pdis, "sdi4"), /* DAT5 */
307 DB8500_PIN_SLEEP("GPIO207_AJ23", slpm_in_wkup_pdis, "sdi4"), /* DAT4 */
308
309 /* Mux in USB pins, drive STP high */
310 DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
311 DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
312 /* Mux in SPI2 pins on the "other C1" altfunction */
313 DB8500_MUX("spi2_oc1_2", "spi2", "spi2"),
314 DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
315 DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
316 DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
317 DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
318 /* SPI2 idle state */
319 DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
320 DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
321 DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
322 /* SPI2 sleep state */
323 DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */
324 DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
325 DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
326 DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
327
328 /* ske default state */
329 DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
330 DB8500_PIN("GPIO153_B17", in_pd, "nmk-ske-keypad"), /* I7 */
331 DB8500_PIN("GPIO154_C16", in_pd, "nmk-ske-keypad"), /* I6 */
332 DB8500_PIN("GPIO155_C19", in_pd, "nmk-ske-keypad"), /* I5 */
333 DB8500_PIN("GPIO156_C17", in_pd, "nmk-ske-keypad"), /* I4 */
334 DB8500_PIN("GPIO161_D21", in_pd, "nmk-ske-keypad"), /* I3 */
335 DB8500_PIN("GPIO162_D20", in_pd, "nmk-ske-keypad"), /* I2 */
336 DB8500_PIN("GPIO163_C20", in_pd, "nmk-ske-keypad"), /* I1 */
337 DB8500_PIN("GPIO164_B21", in_pd, "nmk-ske-keypad"), /* I0 */
338 DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
339 DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
340 DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
341 DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
342 DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
343 DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
344 DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
345 DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
346 /* ske sleep state */
347 DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
348 DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
349 DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
350 DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
351 DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
352 DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
353 DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
354 DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
355 DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
356 DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
357 DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
358 DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
359 DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
360 DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
361 DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
362 DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
363
364 /* STM APE pins states */
365 DB8500_MUX_STATE("stmape_c_1", "stmape",
366 "stm", "ape_mipi34"),
367 DB8500_PIN_STATE("GPIO70_G5", in_nopull,
368 "stm", "ape_mipi34"), /* clk */
369 DB8500_PIN_STATE("GPIO71_G4", in_nopull,
370 "stm", "ape_mipi34"), /* dat3 */
371 DB8500_PIN_STATE("GPIO72_H4", in_nopull,
372 "stm", "ape_mipi34"), /* dat2 */
373 DB8500_PIN_STATE("GPIO73_H3", in_nopull,
374 "stm", "ape_mipi34"), /* dat1 */
375 DB8500_PIN_STATE("GPIO74_J3", in_nopull,
376 "stm", "ape_mipi34"), /* dat0 */
377
378 DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
379 "stm", "ape_mipi34_sleep"), /* clk */
380 DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
381 "stm", "ape_mipi34_sleep"), /* dat3 */
382 DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
383 "stm", "ape_mipi34_sleep"), /* dat2 */
384 DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
385 "stm", "ape_mipi34_sleep"), /* dat1 */
386 DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
387 "stm", "ape_mipi34_sleep"), /* dat0 */
388
389 DB8500_MUX_STATE("stmape_oc1_1", "stmape",
390 "stm", "ape_microsd"),
391 DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
392 "stm", "ape_microsd"), /* clk */
393 DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
394 "stm", "ape_microsd"), /* dat0 */
395 DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
396 "stm", "ape_microsd"), /* dat1 */
397 DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
398 "stm", "ape_microsd"), /* dat2 */
399 DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
400 "stm", "ape_microsd"), /* dat3 */
401
402 DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
403 "stm", "ape_microsd_sleep"), /* clk */
404 DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
405 "stm", "ape_microsd_sleep"), /* dat0 */
406 DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
407 "stm", "ape_microsd_sleep"), /* dat1 */
408 DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
409 "stm", "ape_microsd_sleep"), /* dat2 */
410 DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
411 "stm", "ape_microsd_sleep"), /* dat3 */
412
413 /* STM Modem pins states */
414 DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
415 "stm", "mod_mipi34"),
416 DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
417 "stm", "mod_mipi34"),
418 DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
419 "stm", "mod_mipi34"),
420 DB8500_PIN_STATE("GPIO70_G5", in_nopull,
421 "stm", "mod_mipi34"), /* clk */
422 DB8500_PIN_STATE("GPIO71_G4", in_nopull,
423 "stm", "mod_mipi34"), /* dat3 */
424 DB8500_PIN_STATE("GPIO72_H4", in_nopull,
425 "stm", "mod_mipi34"), /* dat2 */
426 DB8500_PIN_STATE("GPIO73_H3", in_nopull,
427 "stm", "mod_mipi34"), /* dat1 */
428 DB8500_PIN_STATE("GPIO74_J3", in_nopull,
429 "stm", "mod_mipi34"), /* dat0 */
430 DB8500_PIN_STATE("GPIO75_H2", in_pu,
431 "stm", "mod_mipi34"), /* uartmod rx */
432 DB8500_PIN_STATE("GPIO76_J2", out_lo,
433 "stm", "mod_mipi34"), /* uartmod tx */
434
435 DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
436 "stm", "mod_mipi34_sleep"), /* clk */
437 DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
438 "stm", "mod_mipi34_sleep"), /* dat3 */
439 DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
440 "stm", "mod_mipi34_sleep"), /* dat2 */
441 DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
442 "stm", "mod_mipi34_sleep"), /* dat1 */
443 DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
444 "stm", "mod_mipi34_sleep"), /* dat0 */
445 DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
446 "stm", "mod_mipi34_sleep"), /* uartmod rx */
447 DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
448 "stm", "mod_mipi34_sleep"), /* uartmod tx */
449
450 DB8500_MUX_STATE("stmmod_b_1", "stmmod",
451 "stm", "mod_microsd"),
452 DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
453 "stm", "mod_microsd"),
454 DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
455 "stm", "mod_microsd"),
456 DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
457 "stm", "mod_microsd"), /* clk */
458 DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
459 "stm", "mod_microsd"), /* dat0 */
460 DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
461 "stm", "mod_microsd"), /* dat1 */
462 DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
463 "stm", "mod_microsd"), /* dat2 */
464 DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
465 "stm", "mod_microsd"), /* dat3 */
466 DB8500_PIN_STATE("GPIO75_H2", in_pu,
467 "stm", "mod_microsd"), /* uartmod rx */
468 DB8500_PIN_STATE("GPIO76_J2", out_lo,
469 "stm", "mod_microsd"), /* uartmod tx */
470
471 DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
472 "stm", "mod_microsd_sleep"), /* clk */
473 DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
474 "stm", "mod_microsd_sleep"), /* dat0 */
475 DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
476 "stm", "mod_microsd_sleep"), /* dat1 */
477 DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
478 "stm", "mod_microsd_sleep"), /* dat2 */
479 DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
480 "stm", "mod_microsd_sleep"), /* dat3 */
481 DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
482 "stm", "mod_microsd_sleep"), /* uartmod rx */
483 DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
484 "stm", "mod_microsd_sleep"), /* uartmod tx */
485
486 /* STM dual Modem/APE pins state */
487 DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
488 "stm", "mod_mipi34_ape_mipi60"),
489 DB8500_MUX_STATE("stmape_c_2", "stmape",
490 "stm", "mod_mipi34_ape_mipi60"),
491 DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
492 "stm", "mod_mipi34_ape_mipi60"),
493 DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
494 "stm", "mod_mipi34_ape_mipi60"),
495 DB8500_PIN_STATE("GPIO70_G5", in_nopull,
496 "stm", "mod_mipi34_ape_mipi60"), /* clk */
497 DB8500_PIN_STATE("GPIO71_G4", in_nopull,
498 "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
499 DB8500_PIN_STATE("GPIO72_H4", in_nopull,
500 "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
501 DB8500_PIN_STATE("GPIO73_H3", in_nopull,
502 "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
503 DB8500_PIN_STATE("GPIO74_J3", in_nopull,
504 "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
505 DB8500_PIN_STATE("GPIO75_H2", in_pu,
506 "stm", "mod_mipi34_ape_mipi60"), /* uartmod rx */
507 DB8500_PIN_STATE("GPIO76_J2", out_lo,
508 "stm", "mod_mipi34_ape_mipi60"), /* uartmod tx */
509 DB8500_PIN_STATE("GPIO155_C19", in_nopull,
510 "stm", "mod_mipi34_ape_mipi60"), /* clk */
511 DB8500_PIN_STATE("GPIO156_C17", in_nopull,
512 "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
513 DB8500_PIN_STATE("GPIO157_A18", in_nopull,
514 "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
515 DB8500_PIN_STATE("GPIO158_C18", in_nopull,
516 "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
517 DB8500_PIN_STATE("GPIO159_B19", in_nopull,
518 "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
519
520 DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
521 "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
522 DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
523 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
524 DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
525 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
526 DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
527 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
528 DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
529 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
530 DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
531 "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod rx */
532 DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
533 "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod tx */
534 DB8500_PIN_STATE("GPIO155_C19", slpm_in_wkup_pdis,
535 "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
536 DB8500_PIN_STATE("GPIO156_C17", slpm_in_wkup_pdis,
537 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
538 DB8500_PIN_STATE("GPIO157_A18", slpm_in_wkup_pdis,
539 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
540 DB8500_PIN_STATE("GPIO158_C18", slpm_in_wkup_pdis,
541 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
542 DB8500_PIN_STATE("GPIO159_B19", slpm_in_wkup_pdis,
543 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
544 };
545
546 /*
547 * These are specifically for the MOP500 and HREFP (pre-v60) version of the
548 * board, which utilized a TC35892 GPIO expander instead of using a lot of
549 * on-chip pins as the HREFv60 and later does.
550 */
551 static struct pinctrl_map __initdata mop500_pinmap[] = {
552 /* Mux in SSP0, pull down RXD pin */
553 DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
554 DB8500_PIN_HOG("GPIO145_C13", pd),
555 /*
556 * XENON Flashgun on image processor GPIO (controlled from image
557 * processor firmware), mux in these image processor GPIO lines 0
558 * (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up
559 * the pins.
560 */
561 DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
562 DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
563 DB8500_PIN_HOG("GPIO6_AF6", in_pu),
564 DB8500_PIN_HOG("GPIO7_AG5", in_pu),
565 /* TC35892 IRQ, pull up the line, let the driver mux in the pin */
566 DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu),
567 /* Mux in UART1 and set the pull-ups */
568 DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
569 DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */
570 DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */
571 /*
572 * Runtime stuff: make it possible to mux in the SKE keypad
573 * and bias the pins
574 */
575 /* ske default state */
576 DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
577 DB8500_PIN("GPIO153_B17", in_pu, "nmk-ske-keypad"), /* I7 */
578 DB8500_PIN("GPIO154_C16", in_pu, "nmk-ske-keypad"), /* I6 */
579 DB8500_PIN("GPIO155_C19", in_pu, "nmk-ske-keypad"), /* I5 */
580 DB8500_PIN("GPIO156_C17", in_pu, "nmk-ske-keypad"), /* I4 */
581 DB8500_PIN("GPIO161_D21", in_pu, "nmk-ske-keypad"), /* I3 */
582 DB8500_PIN("GPIO162_D20", in_pu, "nmk-ske-keypad"), /* I2 */
583 DB8500_PIN("GPIO163_C20", in_pu, "nmk-ske-keypad"), /* I1 */
584 DB8500_PIN("GPIO164_B21", in_pu, "nmk-ske-keypad"), /* I0 */
585 DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
586 DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
587 DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
588 DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
589 DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
590 DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
591 DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
592 DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
593 /* ske sleep state */
594 DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
595 DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
596 DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
597 DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
598 DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
599 DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
600 DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
601 DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
602 DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
603 DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
604 DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
605 DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
606 DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
607 DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
608 DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
609 DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
610
611 /* Mux in and drive the SDI0 DAT31DIR line high at runtime */
612 DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"),
613 DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"),
614 };
615
616 /*
617 * The HREFv60 series of platforms is using available pins on the DB8500
618 * insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0
619 * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines.
620 */
621 static struct pinctrl_map __initdata hrefv60_pinmap[] = {
622 /* Drive WLAN_ENA low */
623 DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */
624 /*
625 * XENON Flashgun on image processor GPIO (controlled from image
626 * processor firmware), mux in these image processor GPIO lines 0
627 * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
628 * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
629 * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
630 */
631 DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
632 DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
633 DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"),
634 DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */
635 DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */
636 DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */
637 DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */
638 /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
639 DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */
640 DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */
641 /*
642 * Display Interface 1 uses GPIO 65 for RST (reset).
643 * Display Interface 2 uses GPIO 66 for RST (reset).
644 * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
645 */
646 DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */
647 DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */
648 /*
649 * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
650 * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
651 * reset signals low.
652 */
653 DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */
654 DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */
655 DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */
656 /*
657 * Drive D19-D23 for the ETM PTM trace interface low,
658 * (presumably pins are unconnected therefore grounded here,
659 * the "other alt C1" setting enables these pins)
660 */
661 DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo),
662 DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo),
663 DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo),
664 DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo),
665 DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo),
666 /* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */
667 DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */
668 DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */
669 /* NFC ENA and RESET to low, pulldown IRQ line */
670 DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */
671 DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */
672 DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */
673 /*
674 * SKE keyboard partly on alt A and partly on "Other alt C1"
675 * Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three
676 * rows of 6 keys, then pull up force sensing interrup and
677 * drive reset and force sensing WU low.
678 */
679 DB8500_MUX_HOG("kp_a_1", "kp"),
680 DB8500_MUX_HOG("kp_oc1_1", "kp"),
681 DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */
682 DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */
683 DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */
684 DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */
685 DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */
686 DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */
687 DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */
688 DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */
689 DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */
690 DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */
691 DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */
692 /* DiPro Sensor interrupt */
693 DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */
694 /* Audio Amplifier HF enable */
695 DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */
696 /* GBF interface, pull low to reset state */
697 DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */
698 /* MSP : HDTV INTERFACE GPIO line */
699 DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd),
700 /* Accelerometer interrupt lines */
701 DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */
702 DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */
703 /* SD card detect GPIO pin */
704 DB8500_PIN_HOG("GPIO95_E8", gpio_in_pu),
705 /*
706 * Runtime stuff
707 * Pull up/down of some sensor GPIO pins, for proximity, HAL sensor
708 * etc.
709 */
710 DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
711 DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"),
712 DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
713 };
714
715 static struct pinctrl_map __initdata u9500_pinmap[] = {
716 /* Mux in UART1 (just RX/TX) and set the pull-ups */
717 DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
718 DB8500_PIN_HOG("GPIO4_AH6", in_pu),
719 DB8500_PIN_HOG("GPIO5_AG6", out_hi),
720 /* WLAN_IRQ line */
721 DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
722 /* HSI */
723 DB8500_MUX_HOG("hsir_a_1", "hsi"),
724 DB8500_MUX_HOG("hsit_a_2", "hsi"),
725 DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
726 DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
727 DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
728 DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */
729 DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
730 DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
731 DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
732 DB8500_PIN_HOG("GPIO226_AF8", gpio_out_hi), /* ACWAKE0 */
733 };
734
735 static struct pinctrl_map __initdata u8500_pinmap[] = {
736 DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */
737 DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */
738 };
739
740 static struct pinctrl_map __initdata snowball_pinmap[] = {
741 /* Mux in SSP0 connected to AB8500, pull down RXD pin */
742 DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
743 DB8500_PIN_HOG("GPIO145_C13", pd),
744 /* Always drive the MC0 DAT31DIR line high on these boards */
745 DB8500_PIN_HOG("GPIO21_AB3", out_hi),
746 /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
747 DB8500_MUX_HOG("sm_b_1", "sm"),
748 /* Drive RSTn_LAN high */
749 DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
750 /* Accelerometer/Magnetometer */
751 DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
752 DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
753 DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
754 /* WLAN/GBF */
755 DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
756 DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
757 DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
758 DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
759 };
760
761 /*
762 * passing "pinsfor=" in kernel cmdline allows for custom
763 * configuration of GPIOs on u8500 derived boards.
764 */
765 static int __init early_pinsfor(char *p)
766 {
767 pinsfor = PINS_FOR_DEFAULT;
768
769 if (strcmp(p, "u9500-21") == 0)
770 pinsfor = PINS_FOR_U9500;
771
772 return 0;
773 }
774 early_param("pinsfor", early_pinsfor);
775
776 int pins_for_u9500(void)
777 {
778 if (pinsfor == PINS_FOR_U9500)
779 return 1;
780
781 return 0;
782 }
783
784 static void __init mop500_href_family_pinmaps_init(void)
785 {
786 switch (pinsfor) {
787 case PINS_FOR_U9500:
788 pinctrl_register_mappings(u9500_pinmap,
789 ARRAY_SIZE(u9500_pinmap));
790 break;
791 case PINS_FOR_DEFAULT:
792 pinctrl_register_mappings(u8500_pinmap,
793 ARRAY_SIZE(u8500_pinmap));
794 default:
795 break;
796 }
797 }
798
799 void __init mop500_pinmaps_init(void)
800 {
801 pinctrl_register_mappings(mop500_family_pinmap,
802 ARRAY_SIZE(mop500_family_pinmap));
803 pinctrl_register_mappings(mop500_pinmap,
804 ARRAY_SIZE(mop500_pinmap));
805 mop500_href_family_pinmaps_init();
806 }
807
808 void __init snowball_pinmaps_init(void)
809 {
810 pinctrl_register_mappings(mop500_family_pinmap,
811 ARRAY_SIZE(mop500_family_pinmap));
812 pinctrl_register_mappings(snowball_pinmap,
813 ARRAY_SIZE(snowball_pinmap));
814 pinctrl_register_mappings(u8500_pinmap,
815 ARRAY_SIZE(u8500_pinmap));
816 }
817
818 void __init hrefv60_pinmaps_init(void)
819 {
820 pinctrl_register_mappings(mop500_family_pinmap,
821 ARRAY_SIZE(mop500_family_pinmap));
822 pinctrl_register_mappings(hrefv60_pinmap,
823 ARRAY_SIZE(hrefv60_pinmap));
824 mop500_href_family_pinmaps_init();
825 }
kernel source for telekom puls (alcatel/mediatek)