arch/arm/mach-tegra/timer.c

   1 /*
   2  * arch/arch/mach-tegra/timer.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  *
   6  * Author:
   7  *      Colin Cross <ccross@google.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/sched.h>
  22 #include <linux/time.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/clockchips.h>
  26 #include <linux/clocksource.h>
  27 #include <linux/clk.h>
  28 #include <linux/io.h>
  29
  30 #include <asm/mach/time.h>
  31 #include <asm/localtimer.h>
  32 #include <asm/sched_clock.h>
  33
  34 #include <mach/iomap.h>
  35 #include <mach/irqs.h>
  36
  37 #include "board.h"
  38 #include "clock.h"
  39
  40 #define TIMERUS_CNTR_1US 0x10
  41 #define TIMERUS_USEC_CFG 0x14
  42 #define TIMERUS_CNTR_FREEZE 0x4c
  43
  44 #define TIMER1_BASE 0x0
  45 #define TIMER2_BASE 0x8
  46 #define TIMER3_BASE 0x50
  47 #define TIMER4_BASE 0x58
  48
  49 #define TIMER_PTV 0x0
  50 #define TIMER_PCR 0x4
  51
  52 struct tegra_timer;
  53
  54 static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
  55
  56 #define timer_writel(value, reg) \
  57         __raw_writel(value, (u32)timer_reg_base + (reg))
  58 #define timer_readl(reg) \
  59         __raw_readl((u32)timer_reg_base + (reg))
  60
  61 static int tegra_timer_set_next_event(unsigned long cycles,
  62                                          struct clock_event_device *evt)
  63 {
  64         u32 reg;
  65
  66         reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
  67         timer_writel(reg, TIMER3_BASE + TIMER_PTV);
  68
  69         return 0;
  70 }
  71
  72 static void tegra_timer_set_mode(enum clock_event_mode mode,
  73                                     struct clock_event_device *evt)
  74 {
  75         u32 reg;
  76
  77         timer_writel(0, TIMER3_BASE + TIMER_PTV);
  78
  79         switch (mode) {
  80         case CLOCK_EVT_MODE_PERIODIC:
  81                 reg = 0xC0000000 | ((1000000/HZ)-1);
  82                 timer_writel(reg, TIMER3_BASE + TIMER_PTV);
  83                 break;
  84         case CLOCK_EVT_MODE_ONESHOT:
  85                 break;
  86         case CLOCK_EVT_MODE_UNUSED:
  87         case CLOCK_EVT_MODE_SHUTDOWN:
  88         case CLOCK_EVT_MODE_RESUME:
  89                 break;
  90         }
  91 }
  92
  93 static cycle_t tegra_clocksource_read(struct clocksource *cs)
  94 {
  95         return timer_readl(TIMERUS_CNTR_1US);
  96 }
  97
  98 static struct clock_event_device tegra_clockevent = {
  99         .name           = "timer0",
 100         .rating         = 300,
 101         .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
 102         .set_next_event = tegra_timer_set_next_event,
 103         .set_mode       = tegra_timer_set_mode,
 104 };
 105
 106 static struct clocksource tegra_clocksource = {
 107         .name   = "timer_us",
 108         .rating = 300,
 109         .read   = tegra_clocksource_read,
 110         .mask   = CLOCKSOURCE_MASK(32),
 111         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 112 };
 113
 114 static DEFINE_CLOCK_DATA(cd);
 115
 116 /*
 117  * Constants generated by clocks_calc_mult_shift(m, s, 1MHz, NSEC_PER_SEC, 60).
 118  * This gives a resolution of about 1us and a wrap period of about 1h11min.
 119  */
 120 #define SC_MULT         4194304000u
 121 #define SC_SHIFT        22
 122
 123 unsigned long long notrace sched_clock(void)
 124 {
 125         u32 cyc = timer_readl(TIMERUS_CNTR_1US);
 126         return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
 127 }
 128
 129 static void notrace tegra_update_sched_clock(void)
 130 {
 131         u32 cyc = timer_readl(TIMERUS_CNTR_1US);
 132         update_sched_clock(&cd, cyc, (u32)~0);
 133 }
 134
 135 static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
 136 {
 137         struct clock_event_device *evt = (struct clock_event_device *)dev_id;
 138         timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
 139         evt->event_handler(evt);
 140         return IRQ_HANDLED;
 141 }
 142
 143 static struct irqaction tegra_timer_irq = {
 144         .name           = "timer0",
 145         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
 146         .handler        = tegra_timer_interrupt,
 147         .dev_id         = &tegra_clockevent,
 148         .irq            = INT_TMR3,
 149 };
 150
 151 static void __init tegra_init_timer(void)
 152 {
 153         unsigned long rate = clk_measure_input_freq();
 154         int ret;
 155
 156 #ifdef CONFIG_HAVE_ARM_TWD
 157         twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
 158 #endif
 159
 160         switch (rate) {
 161         case 12000000:
 162                 timer_writel(0x000b, TIMERUS_USEC_CFG);
 163                 break;
 164         case 13000000:
 165                 timer_writel(0x000c, TIMERUS_USEC_CFG);
 166                 break;
 167         case 19200000:
 168                 timer_writel(0x045f, TIMERUS_USEC_CFG);
 169                 break;
 170         case 26000000:
 171                 timer_writel(0x0019, TIMERUS_USEC_CFG);
 172                 break;
 173         default:
 174                 WARN(1, "Unknown clock rate");
 175         }
 176
 177         init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32,
 178                                1000000, SC_MULT, SC_SHIFT);
 179
 180         if (clocksource_register_hz(&tegra_clocksource, 1000000)) {
 181                 printk(KERN_ERR "Failed to register clocksource\n");
 182                 BUG();
 183         }
 184
 185         ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
 186         if (ret) {
 187                 printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
 188                 BUG();
 189         }
 190
 191         clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
 192         tegra_clockevent.max_delta_ns =
 193                 clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
 194         tegra_clockevent.min_delta_ns =
 195                 clockevent_delta2ns(0x1, &tegra_clockevent);
 196         tegra_clockevent.cpumask = cpu_all_mask;
 197         tegra_clockevent.irq = tegra_timer_irq.irq;
 198         clockevents_register_device(&tegra_clockevent);
 199
 200         return;
 201 }
 202
 203 struct sys_timer tegra_timer = {
 204         .init = tegra_init_timer,
 205 };