projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge git://git.kernel.org/pub/scm/linux/kernel/git/sfrench/cifs-2.6
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-tegra / tegra2_clocks.c
1 /*
2 * arch/arm/mach-tegra/tegra2_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/list.h>
23 #include <linux/spinlock.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26 #include <linux/hrtimer.h>
27 #include <linux/clkdev.h>
28
29 #include <mach/iomap.h>
30
31 #include "clock.h"
32 #include "fuse.h"
33 #include "tegra2_dvfs.h"
34
35 #define RST_DEVICES 0x004
36 #define RST_DEVICES_SET 0x300
37 #define RST_DEVICES_CLR 0x304
38 #define RST_DEVICES_NUM 3
39
40 #define CLK_OUT_ENB 0x010
41 #define CLK_OUT_ENB_SET 0x320
42 #define CLK_OUT_ENB_CLR 0x324
43 #define CLK_OUT_ENB_NUM 3
44
45 #define CLK_MASK_ARM 0x44
46 #define MISC_CLK_ENB 0x48
47
48 #define OSC_CTRL 0x50
49 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
50 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
51 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
52 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
53 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
54 #define OSC_CTRL_MASK 0x3f2
55
56 #define OSC_FREQ_DET 0x58
57 #define OSC_FREQ_DET_TRIG (1<<31)
58
59 #define OSC_FREQ_DET_STATUS 0x5C
60 #define OSC_FREQ_DET_BUSY (1<<31)
61 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
62
63 #define PERIPH_CLK_SOURCE_I2S1 0x100
64 #define PERIPH_CLK_SOURCE_EMC 0x19c
65 #define PERIPH_CLK_SOURCE_OSC 0x1fc
66 #define PERIPH_CLK_SOURCE_NUM \
67 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
68
69 #define PERIPH_CLK_SOURCE_MASK (3<<30)
70 #define PERIPH_CLK_SOURCE_SHIFT 30
71 #define PERIPH_CLK_SOURCE_ENABLE (1<<28)
72 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
73 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
74 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
75
76 #define PLL_BASE 0x0
77 #define PLL_BASE_BYPASS (1<<31)
78 #define PLL_BASE_ENABLE (1<<30)
79 #define PLL_BASE_REF_ENABLE (1<<29)
80 #define PLL_BASE_OVERRIDE (1<<28)
81 #define PLL_BASE_LOCK (1<<27)
82 #define PLL_BASE_DIVP_MASK (0x7<<20)
83 #define PLL_BASE_DIVP_SHIFT 20
84 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
85 #define PLL_BASE_DIVN_SHIFT 8
86 #define PLL_BASE_DIVM_MASK (0x1F)
87 #define PLL_BASE_DIVM_SHIFT 0
88
89 #define PLL_OUT_RATIO_MASK (0xFF<<8)
90 #define PLL_OUT_RATIO_SHIFT 8
91 #define PLL_OUT_OVERRIDE (1<<2)
92 #define PLL_OUT_CLKEN (1<<1)
93 #define PLL_OUT_RESET_DISABLE (1<<0)
94
95 #define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
96 #define PLL_MISC_LOCK_ENABLE(c) (((c)->flags & PLLU) ? (1<<22) : (1<<18))
97
98 #define PLL_MISC_DCCON_SHIFT 20
99 #define PLL_MISC_CPCON_SHIFT 8
100 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
101 #define PLL_MISC_LFCON_SHIFT 4
102 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
103 #define PLL_MISC_VCOCON_SHIFT 0
104 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
105
106 #define PLLU_BASE_POST_DIV (1<<20)
107
108 #define PLLD_MISC_CLKENABLE (1<<30)
109 #define PLLD_MISC_DIV_RST (1<<23)
110 #define PLLD_MISC_DCCON_SHIFT 12
111
112 #define PLLE_MISC_READY (1 << 15)
113
114 #define PERIPH_CLK_TO_ENB_REG(c) ((c->clk_num / 32) * 4)
115 #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->clk_num / 32) * 8)
116 #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->clk_num % 32))
117
118 #define SUPER_CLK_MUX 0x00
119 #define SUPER_STATE_SHIFT 28
120 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
121 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
122 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
123 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
124 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
125 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
126 #define SUPER_SOURCE_MASK 0xF
127 #define SUPER_FIQ_SOURCE_SHIFT 12
128 #define SUPER_IRQ_SOURCE_SHIFT 8
129 #define SUPER_RUN_SOURCE_SHIFT 4
130 #define SUPER_IDLE_SOURCE_SHIFT 0
131
132 #define SUPER_CLK_DIVIDER 0x04
133
134 #define BUS_CLK_DISABLE (1<<3)
135 #define BUS_CLK_DIV_MASK 0x3
136
137 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
138
139 #define clk_writel(value, reg) \
140 __raw_writel(value, (u32)reg_clk_base + (reg))
141 #define clk_readl(reg) \
142 __raw_readl((u32)reg_clk_base + (reg))
143
144 unsigned long clk_measure_input_freq(void)
145 {
146 u32 clock_autodetect;
147 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
148 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
149 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
150 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
151 return 12000000;
152 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
153 return 13000000;
154 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
155 return 19200000;
156 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
157 return 26000000;
158 } else {
159 pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
160 BUG();
161 return 0;
162 }
163 }
164
165 static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
166 {
167 s64 divider_u71 = parent_rate * 2;
168 divider_u71 += rate - 1;
169 do_div(divider_u71, rate);
170
171 if (divider_u71 - 2 < 0)
172 return 0;
173
174 if (divider_u71 - 2 > 255)
175 return -EINVAL;
176
177 return divider_u71 - 2;
178 }
179
180 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
181 {
182 s64 divider_u16;
183
184 divider_u16 = parent_rate;
185 divider_u16 += rate - 1;
186 do_div(divider_u16, rate);
187
188 if (divider_u16 - 1 < 0)
189 return 0;
190
191 if (divider_u16 - 1 > 255)
192 return -EINVAL;
193
194 return divider_u16 - 1;
195 }
196
197 /* clk_m functions */
198 static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
199 {
200 u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
201
202 c->rate = clk_measure_input_freq();
203 switch (c->rate) {
204 case 12000000:
205 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
206 break;
207 case 13000000:
208 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
209 break;
210 case 19200000:
211 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
212 break;
213 case 26000000:
214 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
215 break;
216 default:
217 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
218 BUG();
219 }
220 clk_writel(auto_clock_control, OSC_CTRL);
221 return c->rate;
222 }
223
224 static void tegra2_clk_m_init(struct clk *c)
225 {
226 pr_debug("%s on clock %s\n", __func__, c->name);
227 tegra2_clk_m_autodetect_rate(c);
228 }
229
230 static int tegra2_clk_m_enable(struct clk *c)
231 {
232 pr_debug("%s on clock %s\n", __func__, c->name);
233 return 0;
234 }
235
236 static void tegra2_clk_m_disable(struct clk *c)
237 {
238 pr_debug("%s on clock %s\n", __func__, c->name);
239 BUG();
240 }
241
242 static struct clk_ops tegra_clk_m_ops = {
243 .init = tegra2_clk_m_init,
244 .enable = tegra2_clk_m_enable,
245 .disable = tegra2_clk_m_disable,
246 };
247
248 /* super clock functions */
249 /* "super clocks" on tegra have two-stage muxes and a clock skipping
250 * super divider. We will ignore the clock skipping divider, since we
251 * can't lower the voltage when using the clock skip, but we can if we
252 * lower the PLL frequency.
253 */
254 static void tegra2_super_clk_init(struct clk *c)
255 {
256 u32 val;
257 int source;
258 int shift;
259 const struct clk_mux_sel *sel;
260 val = clk_readl(c->reg + SUPER_CLK_MUX);
261 c->state = ON;
262 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
263 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
264 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
265 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
266 source = (val >> shift) & SUPER_SOURCE_MASK;
267 for (sel = c->inputs; sel->input != NULL; sel++) {
268 if (sel->value == source)
269 break;
270 }
271 BUG_ON(sel->input == NULL);
272 c->parent = sel->input;
273 }
274
275 static int tegra2_super_clk_enable(struct clk *c)
276 {
277 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
278 return 0;
279 }
280
281 static void tegra2_super_clk_disable(struct clk *c)
282 {
283 pr_debug("%s on clock %s\n", __func__, c->name);
284
285 /* oops - don't disable the CPU clock! */
286 BUG();
287 }
288
289 static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
290 {
291 u32 val;
292 const struct clk_mux_sel *sel;
293 int shift;
294
295 val = clk_readl(c->reg + SUPER_CLK_MUX);;
296 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
297 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
298 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
299 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
300 for (sel = c->inputs; sel->input != NULL; sel++) {
301 if (sel->input == p) {
302 val &= ~(SUPER_SOURCE_MASK << shift);
303 val |= sel->value << shift;
304
305 if (c->refcnt)
306 clk_enable_locked(p);
307
308 clk_writel(val, c->reg);
309
310 if (c->refcnt && c->parent)
311 clk_disable_locked(c->parent);
312
313 clk_reparent(c, p);
314 return 0;
315 }
316 }
317 return -EINVAL;
318 }
319
320 static struct clk_ops tegra_super_ops = {
321 .init = tegra2_super_clk_init,
322 .enable = tegra2_super_clk_enable,
323 .disable = tegra2_super_clk_disable,
324 .set_parent = tegra2_super_clk_set_parent,
325 };
326
327 /* virtual cpu clock functions */
328 /* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
329 To change the frequency of these clocks, the parent pll may need to be
330 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
331 and then the clock moved back to the pll. To hide this sequence, a virtual
332 clock handles it.
333 */
334 static void tegra2_cpu_clk_init(struct clk *c)
335 {
336 }
337
338 static int tegra2_cpu_clk_enable(struct clk *c)
339 {
340 return 0;
341 }
342
343 static void tegra2_cpu_clk_disable(struct clk *c)
344 {
345 pr_debug("%s on clock %s\n", __func__, c->name);
346
347 /* oops - don't disable the CPU clock! */
348 BUG();
349 }
350
351 static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
352 {
353 int ret;
354 ret = clk_set_parent_locked(c->parent, c->backup);
355 if (ret) {
356 pr_err("Failed to switch cpu to clock %s\n", c->backup->name);
357 return ret;
358 }
359
360 ret = clk_set_rate_locked(c->main, rate);
361 if (ret) {
362 pr_err("Failed to change cpu pll to %lu\n", rate);
363 return ret;
364 }
365
366 ret = clk_set_parent_locked(c->parent, c->main);
367 if (ret) {
368 pr_err("Failed to switch cpu to clock %s\n", c->main->name);
369 return ret;
370 }
371
372 return 0;
373 }
374
375 static struct clk_ops tegra_cpu_ops = {
376 .init = tegra2_cpu_clk_init,
377 .enable = tegra2_cpu_clk_enable,
378 .disable = tegra2_cpu_clk_disable,
379 .set_rate = tegra2_cpu_clk_set_rate,
380 };
381
382 /* bus clock functions */
383 static void tegra2_bus_clk_init(struct clk *c)
384 {
385 u32 val = clk_readl(c->reg);
386 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
387 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
388 c->mul = 1;
389 }
390
391 static int tegra2_bus_clk_enable(struct clk *c)
392 {
393 u32 val = clk_readl(c->reg);
394 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
395 clk_writel(val, c->reg);
396 return 0;
397 }
398
399 static void tegra2_bus_clk_disable(struct clk *c)
400 {
401 u32 val = clk_readl(c->reg);
402 val |= BUS_CLK_DISABLE << c->reg_shift;
403 clk_writel(val, c->reg);
404 }
405
406 static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
407 {
408 u32 val = clk_readl(c->reg);
409 unsigned long parent_rate = c->parent->rate;
410 int i;
411 for (i = 1; i <= 4; i++) {
412 if (rate == parent_rate / i) {
413 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
414 val |= (i - 1) << c->reg_shift;
415 clk_writel(val, c->reg);
416 c->div = i;
417 c->mul = 1;
418 return 0;
419 }
420 }
421 return -EINVAL;
422 }
423
424 static struct clk_ops tegra_bus_ops = {
425 .init = tegra2_bus_clk_init,
426 .enable = tegra2_bus_clk_enable,
427 .disable = tegra2_bus_clk_disable,
428 .set_rate = tegra2_bus_clk_set_rate,
429 };
430
431 /* PLL Functions */
432 static int tegra2_pll_clk_wait_for_lock(struct clk *c)
433 {
434 ktime_t before;
435
436 before = ktime_get();
437
438 while (!(clk_readl(c->reg + PLL_BASE) & PLL_BASE_LOCK)) {
439 if (ktime_us_delta(ktime_get(), before) > 5000) {
440 pr_err("Timed out waiting for lock bit on pll %s",
441 c->name);
442 return -1;
443 }
444 }
445
446 return 0;
447 }
448
449 static void tegra2_pll_clk_init(struct clk *c)
450 {
451 u32 val = clk_readl(c->reg + PLL_BASE);
452
453 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
454
455 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
456 pr_warning("Clock %s has unknown fixed frequency\n", c->name);
457 c->mul = 1;
458 c->div = 1;
459 } else if (val & PLL_BASE_BYPASS) {
460 c->mul = 1;
461 c->div = 1;
462 } else {
463 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
464 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
465 if (c->flags & PLLU)
466 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
467 else
468 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
469 }
470 }
471
472 static int tegra2_pll_clk_enable(struct clk *c)
473 {
474 u32 val;
475 pr_debug("%s on clock %s\n", __func__, c->name);
476
477 val = clk_readl(c->reg + PLL_BASE);
478 val &= ~PLL_BASE_BYPASS;
479 val |= PLL_BASE_ENABLE;
480 clk_writel(val, c->reg + PLL_BASE);
481
482 val = clk_readl(c->reg + PLL_MISC(c));
483 val |= PLL_MISC_LOCK_ENABLE(c);
484 clk_writel(val, c->reg + PLL_MISC(c));
485
486 tegra2_pll_clk_wait_for_lock(c);
487
488 return 0;
489 }
490
491 static void tegra2_pll_clk_disable(struct clk *c)
492 {
493 u32 val;
494 pr_debug("%s on clock %s\n", __func__, c->name);
495
496 val = clk_readl(c->reg);
497 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
498 clk_writel(val, c->reg);
499 }
500
501 static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
502 {
503 u32 val;
504 unsigned long input_rate;
505 const struct clk_pll_table *sel;
506
507 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
508 BUG_ON(c->refcnt != 0);
509
510 input_rate = c->parent->rate;
511 for (sel = c->pll_table; sel->input_rate != 0; sel++) {
512 if (sel->input_rate == input_rate && sel->output_rate == rate) {
513 c->mul = sel->n;
514 c->div = sel->m * sel->p;
515
516 val = clk_readl(c->reg + PLL_BASE);
517 if (c->flags & PLL_FIXED)
518 val |= PLL_BASE_OVERRIDE;
519 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
520 PLL_BASE_DIVM_MASK);
521 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
522 (sel->n << PLL_BASE_DIVN_SHIFT);
523 BUG_ON(sel->p < 1 || sel->p > 2);
524 if (c->flags & PLLU) {
525 if (sel->p == 1)
526 val |= PLLU_BASE_POST_DIV;
527 } else {
528 if (sel->p == 2)
529 val |= 1 << PLL_BASE_DIVP_SHIFT;
530 }
531 clk_writel(val, c->reg + PLL_BASE);
532
533 if (c->flags & PLL_HAS_CPCON) {
534 val = clk_readl(c->reg + PLL_MISC(c));
535 val &= ~PLL_MISC_CPCON_MASK;
536 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
537 clk_writel(val, c->reg + PLL_MISC(c));
538 }
539
540 if (c->state == ON)
541 tegra2_pll_clk_enable(c);
542
543 return 0;
544 }
545 }
546 return -EINVAL;
547 }
548
549 static struct clk_ops tegra_pll_ops = {
550 .init = tegra2_pll_clk_init,
551 .enable = tegra2_pll_clk_enable,
552 .disable = tegra2_pll_clk_disable,
553 .set_rate = tegra2_pll_clk_set_rate,
554 };
555
556 static void tegra2_pllx_clk_init(struct clk *c)
557 {
558 tegra2_pll_clk_init(c);
559
560 if (tegra_sku_id() == 7)
561 c->max_rate = 750000000;
562 }
563
564 static struct clk_ops tegra_pllx_ops = {
565 .init = tegra2_pllx_clk_init,
566 .enable = tegra2_pll_clk_enable,
567 .disable = tegra2_pll_clk_disable,
568 .set_rate = tegra2_pll_clk_set_rate,
569 };
570
571 static int tegra2_plle_clk_enable(struct clk *c)
572 {
573 u32 val;
574
575 pr_debug("%s on clock %s\n", __func__, c->name);
576
577 mdelay(1);
578
579 val = clk_readl(c->reg + PLL_BASE);
580 if (!(val & PLLE_MISC_READY))
581 return -EBUSY;
582
583 val = clk_readl(c->reg + PLL_BASE);
584 val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
585 clk_writel(val, c->reg + PLL_BASE);
586
587 return 0;
588 }
589
590 static struct clk_ops tegra_plle_ops = {
591 .init = tegra2_pll_clk_init,
592 .enable = tegra2_plle_clk_enable,
593 .set_rate = tegra2_pll_clk_set_rate,
594 };
595
596 /* Clock divider ops */
597 static void tegra2_pll_div_clk_init(struct clk *c)
598 {
599 u32 val = clk_readl(c->reg);
600 u32 divu71;
601 val >>= c->reg_shift;
602 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
603 if (!(val & PLL_OUT_RESET_DISABLE))
604 c->state = OFF;
605
606 if (c->flags & DIV_U71) {
607 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
608 c->div = (divu71 + 2);
609 c->mul = 2;
610 } else if (c->flags & DIV_2) {
611 c->div = 2;
612 c->mul = 1;
613 } else {
614 c->div = 1;
615 c->mul = 1;
616 }
617 }
618
619 static int tegra2_pll_div_clk_enable(struct clk *c)
620 {
621 u32 val;
622 u32 new_val;
623
624 pr_debug("%s: %s\n", __func__, c->name);
625 if (c->flags & DIV_U71) {
626 val = clk_readl(c->reg);
627 new_val = val >> c->reg_shift;
628 new_val &= 0xFFFF;
629
630 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
631
632 val &= ~(0xFFFF << c->reg_shift);
633 val |= new_val << c->reg_shift;
634 clk_writel(val, c->reg);
635 return 0;
636 } else if (c->flags & DIV_2) {
637 BUG_ON(!(c->flags & PLLD));
638 val = clk_readl(c->reg);
639 val &= ~PLLD_MISC_DIV_RST;
640 clk_writel(val, c->reg);
641 return 0;
642 }
643 return -EINVAL;
644 }
645
646 static void tegra2_pll_div_clk_disable(struct clk *c)
647 {
648 u32 val;
649 u32 new_val;
650
651 pr_debug("%s: %s\n", __func__, c->name);
652 if (c->flags & DIV_U71) {
653 val = clk_readl(c->reg);
654 new_val = val >> c->reg_shift;
655 new_val &= 0xFFFF;
656
657 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
658
659 val &= ~(0xFFFF << c->reg_shift);
660 val |= new_val << c->reg_shift;
661 clk_writel(val, c->reg);
662 } else if (c->flags & DIV_2) {
663 BUG_ON(!(c->flags & PLLD));
664 val = clk_readl(c->reg);
665 val |= PLLD_MISC_DIV_RST;
666 clk_writel(val, c->reg);
667 }
668 }
669
670 static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
671 {
672 u32 val;
673 u32 new_val;
674 int divider_u71;
675 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
676 if (c->flags & DIV_U71) {
677 divider_u71 = clk_div71_get_divider(c->parent->rate, rate);
678 if (divider_u71 >= 0) {
679 val = clk_readl(c->reg);
680 new_val = val >> c->reg_shift;
681 new_val &= 0xFFFF;
682 if (c->flags & DIV_U71_FIXED)
683 new_val |= PLL_OUT_OVERRIDE;
684 new_val &= ~PLL_OUT_RATIO_MASK;
685 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
686
687 val &= ~(0xFFFF << c->reg_shift);
688 val |= new_val << c->reg_shift;
689 clk_writel(val, c->reg);
690 c->div = divider_u71 + 2;
691 c->mul = 2;
692 return 0;
693 }
694 } else if (c->flags & DIV_2) {
695 if (c->parent->rate == rate * 2)
696 return 0;
697 }
698 return -EINVAL;
699 }
700
701 static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
702 {
703 int divider;
704 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
705
706 if (c->flags & DIV_U71) {
707 divider = clk_div71_get_divider(c->parent->rate, rate);
708 if (divider < 0)
709 return divider;
710 return c->parent->rate * 2 / (divider + 2);
711 } else if (c->flags & DIV_2) {
712 return c->parent->rate / 2;
713 }
714 return -EINVAL;
715 }
716
717 static struct clk_ops tegra_pll_div_ops = {
718 .init = tegra2_pll_div_clk_init,
719 .enable = tegra2_pll_div_clk_enable,
720 .disable = tegra2_pll_div_clk_disable,
721 .set_rate = tegra2_pll_div_clk_set_rate,
722 .round_rate = tegra2_pll_div_clk_round_rate,
723 };
724
725 /* Periph clk ops */
726
727 static void tegra2_periph_clk_init(struct clk *c)
728 {
729 u32 val = clk_readl(c->reg);
730 const struct clk_mux_sel *mux = 0;
731 const struct clk_mux_sel *sel;
732 if (c->flags & MUX) {
733 for (sel = c->inputs; sel->input != NULL; sel++) {
734 if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)
735 mux = sel;
736 }
737 BUG_ON(!mux);
738
739 c->parent = mux->input;
740 } else {
741 c->parent = c->inputs[0].input;
742 }
743
744 if (c->flags & DIV_U71) {
745 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
746 c->div = divu71 + 2;
747 c->mul = 2;
748 } else if (c->flags & DIV_U16) {
749 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
750 c->div = divu16 + 1;
751 c->mul = 1;
752 } else {
753 c->div = 1;
754 c->mul = 1;
755 }
756
757 c->state = ON;
758 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
759 PERIPH_CLK_TO_ENB_BIT(c)))
760 c->state = OFF;
761 if (!(c->flags & PERIPH_NO_RESET))
762 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
763 PERIPH_CLK_TO_ENB_BIT(c))
764 c->state = OFF;
765 }
766
767 static int tegra2_periph_clk_enable(struct clk *c)
768 {
769 u32 val;
770 pr_debug("%s on clock %s\n", __func__, c->name);
771
772 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
773 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
774 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
775 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
776 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
777 if (c->flags & PERIPH_EMC_ENB) {
778 /* The EMC peripheral clock has 2 extra enable bits */
779 /* FIXME: Do they need to be disabled? */
780 val = clk_readl(c->reg);
781 val |= 0x3 << 24;
782 clk_writel(val, c->reg);
783 }
784 return 0;
785 }
786
787 static void tegra2_periph_clk_disable(struct clk *c)
788 {
789 pr_debug("%s on clock %s\n", __func__, c->name);
790
791 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
792 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
793 }
794
795 void tegra2_periph_reset_deassert(struct clk *c)
796 {
797 pr_debug("%s on clock %s\n", __func__, c->name);
798 if (!(c->flags & PERIPH_NO_RESET))
799 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
800 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
801 }
802
803 void tegra2_periph_reset_assert(struct clk *c)
804 {
805 pr_debug("%s on clock %s\n", __func__, c->name);
806 if (!(c->flags & PERIPH_NO_RESET))
807 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
808 RST_DEVICES_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
809 }
810
811
812 static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
813 {
814 u32 val;
815 const struct clk_mux_sel *sel;
816 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
817 for (sel = c->inputs; sel->input != NULL; sel++) {
818 if (sel->input == p) {
819 val = clk_readl(c->reg);
820 val &= ~PERIPH_CLK_SOURCE_MASK;
821 val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;
822
823 if (c->refcnt)
824 clk_enable_locked(p);
825
826 clk_writel(val, c->reg);
827
828 if (c->refcnt && c->parent)
829 clk_disable_locked(c->parent);
830
831 clk_reparent(c, p);
832 return 0;
833 }
834 }
835
836 return -EINVAL;
837 }
838
839 static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
840 {
841 u32 val;
842 int divider;
843 pr_debug("%s: %lu\n", __func__, rate);
844 if (c->flags & DIV_U71) {
845 divider = clk_div71_get_divider(c->parent->rate, rate);
846 if (divider >= 0) {
847 val = clk_readl(c->reg);
848 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
849 val |= divider;
850 clk_writel(val, c->reg);
851 c->div = divider + 2;
852 c->mul = 2;
853 return 0;
854 }
855 } else if (c->flags & DIV_U16) {
856 divider = clk_div16_get_divider(c->parent->rate, rate);
857 if (divider >= 0) {
858 val = clk_readl(c->reg);
859 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
860 val |= divider;
861 clk_writel(val, c->reg);
862 c->div = divider + 1;
863 c->mul = 1;
864 return 0;
865 }
866 } else if (c->parent->rate <= rate) {
867 c->div = 1;
868 c->mul = 1;
869 return 0;
870 }
871 return -EINVAL;
872 }
873
874 static long tegra2_periph_clk_round_rate(struct clk *c,
875 unsigned long rate)
876 {
877 int divider;
878 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
879
880 if (c->flags & DIV_U71) {
881 divider = clk_div71_get_divider(c->parent->rate, rate);
882 if (divider < 0)
883 return divider;
884
885 return c->parent->rate * 2 / (divider + 2);
886 } else if (c->flags & DIV_U16) {
887 divider = clk_div16_get_divider(c->parent->rate, rate);
888 if (divider < 0)
889 return divider;
890 return c->parent->rate / (divider + 1);
891 }
892 return -EINVAL;
893 }
894
895 static struct clk_ops tegra_periph_clk_ops = {
896 .init = &tegra2_periph_clk_init,
897 .enable = &tegra2_periph_clk_enable,
898 .disable = &tegra2_periph_clk_disable,
899 .set_parent = &tegra2_periph_clk_set_parent,
900 .set_rate = &tegra2_periph_clk_set_rate,
901 .round_rate = &tegra2_periph_clk_round_rate,
902 };
903
904 /* Clock doubler ops */
905 static void tegra2_clk_double_init(struct clk *c)
906 {
907 c->mul = 2;
908 c->div = 1;
909 c->state = ON;
910 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
911 PERIPH_CLK_TO_ENB_BIT(c)))
912 c->state = OFF;
913 };
914
915 static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
916 {
917 if (rate != 2 * c->parent->rate)
918 return -EINVAL;
919 c->mul = 2;
920 c->div = 1;
921 return 0;
922 }
923
924 static struct clk_ops tegra_clk_double_ops = {
925 .init = &tegra2_clk_double_init,
926 .enable = &tegra2_periph_clk_enable,
927 .disable = &tegra2_periph_clk_disable,
928 .set_rate = &tegra2_clk_double_set_rate,
929 };
930
931 static void tegra2_audio_sync_clk_init(struct clk *c)
932 {
933 int source;
934 const struct clk_mux_sel *sel;
935 u32 val = clk_readl(c->reg);
936 c->state = (val & (1<<4)) ? OFF : ON;
937 source = val & 0xf;
938 for (sel = c->inputs; sel->input != NULL; sel++)
939 if (sel->value == source)
940 break;
941 BUG_ON(sel->input == NULL);
942 c->parent = sel->input;
943 }
944
945 static int tegra2_audio_sync_clk_enable(struct clk *c)
946 {
947 clk_writel(0, c->reg);
948 return 0;
949 }
950
951 static void tegra2_audio_sync_clk_disable(struct clk *c)
952 {
953 clk_writel(1, c->reg);
954 }
955
956 static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
957 {
958 u32 val;
959 const struct clk_mux_sel *sel;
960 for (sel = c->inputs; sel->input != NULL; sel++) {
961 if (sel->input == p) {
962 val = clk_readl(c->reg);
963 val &= ~0xf;
964 val |= sel->value;
965
966 if (c->refcnt)
967 clk_enable_locked(p);
968
969 clk_writel(val, c->reg);
970
971 if (c->refcnt && c->parent)
972 clk_disable_locked(c->parent);
973
974 clk_reparent(c, p);
975 return 0;
976 }
977 }
978
979 return -EINVAL;
980 }
981
982 static int tegra2_audio_sync_clk_set_rate(struct clk *c, unsigned long rate)
983 {
984 unsigned long parent_rate;
985 if (!c->parent) {
986 pr_err("%s: clock has no parent\n", __func__);
987 return -EINVAL;
988 }
989 parent_rate = c->parent->rate;
990 if (rate != parent_rate) {
991 pr_err("%s: %s/%ld differs from parent %s/%ld\n",
992 __func__,
993 c->name, rate,
994 c->parent->name, parent_rate);
995 return -EINVAL;
996 }
997 c->rate = parent_rate;
998 return 0;
999 }
1000
1001 static struct clk_ops tegra_audio_sync_clk_ops = {
1002 .init = tegra2_audio_sync_clk_init,
1003 .enable = tegra2_audio_sync_clk_enable,
1004 .disable = tegra2_audio_sync_clk_disable,
1005 .set_rate = tegra2_audio_sync_clk_set_rate,
1006 .set_parent = tegra2_audio_sync_clk_set_parent,
1007 };
1008
1009 /* Clock definitions */
1010 static struct clk tegra_clk_32k = {
1011 .name = "clk_32k",
1012 .rate = 32768,
1013 .ops = NULL,
1014 .max_rate = 32768,
1015 };
1016
1017 static struct clk_pll_table tegra_pll_s_table[] = {
1018 {32768, 12000000, 366, 1, 1, 0},
1019 {32768, 13000000, 397, 1, 1, 0},
1020 {32768, 19200000, 586, 1, 1, 0},
1021 {32768, 26000000, 793, 1, 1, 0},
1022 {0, 0, 0, 0, 0, 0},
1023 };
1024
1025 static struct clk tegra_pll_s = {
1026 .name = "pll_s",
1027 .flags = PLL_ALT_MISC_REG,
1028 .ops = &tegra_pll_ops,
1029 .reg = 0xf0,
1030 .input_min = 32768,
1031 .input_max = 32768,
1032 .parent = &tegra_clk_32k,
1033 .cf_min = 0, /* FIXME */
1034 .cf_max = 0, /* FIXME */
1035 .vco_min = 12000000,
1036 .vco_max = 26000000,
1037 .pll_table = tegra_pll_s_table,
1038 .max_rate = 26000000,
1039 };
1040
1041 static struct clk_mux_sel tegra_clk_m_sel[] = {
1042 { .input = &tegra_clk_32k, .value = 0},
1043 { .input = &tegra_pll_s, .value = 1},
1044 { 0, 0},
1045 };
1046 static struct clk tegra_clk_m = {
1047 .name = "clk_m",
1048 .flags = ENABLE_ON_INIT,
1049 .ops = &tegra_clk_m_ops,
1050 .inputs = tegra_clk_m_sel,
1051 .reg = 0x1fc,
1052 .reg_mask = (1<<28),
1053 .reg_shift = 28,
1054 .max_rate = 26000000,
1055 };
1056
1057 static struct clk_pll_table tegra_pll_c_table[] = {
1058 { 0, 0, 0, 0, 0, 0 },
1059 };
1060
1061 static struct clk tegra_pll_c = {
1062 .name = "pll_c",
1063 .flags = PLL_HAS_CPCON,
1064 .ops = &tegra_pll_ops,
1065 .reg = 0x80,
1066 .input_min = 2000000,
1067 .input_max = 31000000,
1068 .parent = &tegra_clk_m,
1069 .cf_min = 1000000,
1070 .cf_max = 6000000,
1071 .vco_min = 20000000,
1072 .vco_max = 1400000000,
1073 .pll_table = tegra_pll_c_table,
1074 .max_rate = 600000000,
1075 };
1076
1077 static struct clk tegra_pll_c_out1 = {
1078 .name = "pll_c_out1",
1079 .ops = &tegra_pll_div_ops,
1080 .flags = DIV_U71,
1081 .parent = &tegra_pll_c,
1082 .reg = 0x84,
1083 .reg_shift = 0,
1084 .max_rate = 600000000,
1085 };
1086
1087 static struct clk_pll_table tegra_pll_m_table[] = {
1088 { 12000000, 666000000, 666, 12, 1, 8},
1089 { 13000000, 666000000, 666, 13, 1, 8},
1090 { 19200000, 666000000, 555, 16, 1, 8},
1091 { 26000000, 666000000, 666, 26, 1, 8},
1092 { 12000000, 600000000, 600, 12, 1, 8},
1093 { 13000000, 600000000, 600, 13, 1, 8},
1094 { 19200000, 600000000, 375, 12, 1, 6},
1095 { 26000000, 600000000, 600, 26, 1, 8},
1096 { 0, 0, 0, 0, 0, 0 },
1097 };
1098
1099 static struct clk tegra_pll_m = {
1100 .name = "pll_m",
1101 .flags = PLL_HAS_CPCON,
1102 .ops = &tegra_pll_ops,
1103 .reg = 0x90,
1104 .input_min = 2000000,
1105 .input_max = 31000000,
1106 .parent = &tegra_clk_m,
1107 .cf_min = 1000000,
1108 .cf_max = 6000000,
1109 .vco_min = 20000000,
1110 .vco_max = 1200000000,
1111 .pll_table = tegra_pll_m_table,
1112 .max_rate = 800000000,
1113 };
1114
1115 static struct clk tegra_pll_m_out1 = {
1116 .name = "pll_m_out1",
1117 .ops = &tegra_pll_div_ops,
1118 .flags = DIV_U71,
1119 .parent = &tegra_pll_m,
1120 .reg = 0x94,
1121 .reg_shift = 0,
1122 .max_rate = 600000000,
1123 };
1124
1125 static struct clk_pll_table tegra_pll_p_table[] = {
1126 { 12000000, 216000000, 432, 12, 2, 8},
1127 { 13000000, 216000000, 432, 13, 2, 8},
1128 { 19200000, 216000000, 90, 4, 2, 1},
1129 { 26000000, 216000000, 432, 26, 2, 8},
1130 { 12000000, 432000000, 432, 12, 1, 8},
1131 { 13000000, 432000000, 432, 13, 1, 8},
1132 { 19200000, 432000000, 90, 4, 1, 1},
1133 { 26000000, 432000000, 432, 26, 1, 8},
1134 { 0, 0, 0, 0, 0, 0 },
1135 };
1136
1137 static struct clk tegra_pll_p = {
1138 .name = "pll_p",
1139 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
1140 .ops = &tegra_pll_ops,
1141 .reg = 0xa0,
1142 .input_min = 2000000,
1143 .input_max = 31000000,
1144 .parent = &tegra_clk_m,
1145 .cf_min = 1000000,
1146 .cf_max = 6000000,
1147 .vco_min = 20000000,
1148 .vco_max = 1400000000,
1149 .pll_table = tegra_pll_p_table,
1150 .max_rate = 432000000,
1151 };
1152
1153 static struct clk tegra_pll_p_out1 = {
1154 .name = "pll_p_out1",
1155 .ops = &tegra_pll_div_ops,
1156 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1157 .parent = &tegra_pll_p,
1158 .reg = 0xa4,
1159 .reg_shift = 0,
1160 .max_rate = 432000000,
1161 };
1162
1163 static struct clk tegra_pll_p_out2 = {
1164 .name = "pll_p_out2",
1165 .ops = &tegra_pll_div_ops,
1166 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1167 .parent = &tegra_pll_p,
1168 .reg = 0xa4,
1169 .reg_shift = 16,
1170 .max_rate = 432000000,
1171 };
1172
1173 static struct clk tegra_pll_p_out3 = {
1174 .name = "pll_p_out3",
1175 .ops = &tegra_pll_div_ops,
1176 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1177 .parent = &tegra_pll_p,
1178 .reg = 0xa8,
1179 .reg_shift = 0,
1180 .max_rate = 432000000,
1181 };
1182
1183 static struct clk tegra_pll_p_out4 = {
1184 .name = "pll_p_out4",
1185 .ops = &tegra_pll_div_ops,
1186 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1187 .parent = &tegra_pll_p,
1188 .reg = 0xa8,
1189 .reg_shift = 16,
1190 .max_rate = 432000000,
1191 };
1192
1193 static struct clk_pll_table tegra_pll_a_table[] = {
1194 { 28800000, 56448000, 49, 25, 1, 1},
1195 { 28800000, 73728000, 64, 25, 1, 1},
1196 { 28800000, 11289600, 49, 25, 1, 1},
1197 { 28800000, 12288000, 64, 25, 1, 1},
1198 { 28800000, 24000000, 5, 6, 1, 1},
1199 { 0, 0, 0, 0, 0, 0 },
1200 };
1201
1202 static struct clk tegra_pll_a = {
1203 .name = "pll_a",
1204 .flags = PLL_HAS_CPCON,
1205 .ops = &tegra_pll_ops,
1206 .reg = 0xb0,
1207 .input_min = 2000000,
1208 .input_max = 31000000,
1209 .parent = &tegra_pll_p_out1,
1210 .cf_min = 1000000,
1211 .cf_max = 6000000,
1212 .vco_min = 20000000,
1213 .vco_max = 1400000000,
1214 .pll_table = tegra_pll_a_table,
1215 .max_rate = 56448000,
1216 };
1217
1218 static struct clk tegra_pll_a_out0 = {
1219 .name = "pll_a_out0",
1220 .ops = &tegra_pll_div_ops,
1221 .flags = DIV_U71,
1222 .parent = &tegra_pll_a,
1223 .reg = 0xb4,
1224 .reg_shift = 0,
1225 .max_rate = 56448000,
1226 };
1227
1228 static struct clk_pll_table tegra_pll_d_table[] = {
1229 { 12000000, 1000000000, 1000, 12, 1, 12},
1230 { 13000000, 1000000000, 1000, 13, 1, 12},
1231 { 19200000, 1000000000, 625, 12, 1, 8},
1232 { 26000000, 1000000000, 1000, 26, 1, 12},
1233 { 0, 0, 0, 0, 0, 0 },
1234 };
1235
1236 static struct clk tegra_pll_d = {
1237 .name = "pll_d",
1238 .flags = PLL_HAS_CPCON | PLLD,
1239 .ops = &tegra_pll_ops,
1240 .reg = 0xd0,
1241 .input_min = 2000000,
1242 .input_max = 40000000,
1243 .parent = &tegra_clk_m,
1244 .cf_min = 1000000,
1245 .cf_max = 6000000,
1246 .vco_min = 40000000,
1247 .vco_max = 1000000000,
1248 .pll_table = tegra_pll_d_table,
1249 .max_rate = 1000000000,
1250 };
1251
1252 static struct clk tegra_pll_d_out0 = {
1253 .name = "pll_d_out0",
1254 .ops = &tegra_pll_div_ops,
1255 .flags = DIV_2 | PLLD,
1256 .parent = &tegra_pll_d,
1257 .max_rate = 500000000,
1258 };
1259
1260 static struct clk_pll_table tegra_pll_u_table[] = {
1261 { 12000000, 480000000, 960, 12, 2, 0},
1262 { 13000000, 480000000, 960, 13, 2, 0},
1263 { 19200000, 480000000, 200, 4, 2, 0},
1264 { 26000000, 480000000, 960, 26, 2, 0},
1265 { 0, 0, 0, 0, 0, 0 },
1266 };
1267
1268 static struct clk tegra_pll_u = {
1269 .name = "pll_u",
1270 .flags = PLLU,
1271 .ops = &tegra_pll_ops,
1272 .reg = 0xc0,
1273 .input_min = 2000000,
1274 .input_max = 40000000,
1275 .parent = &tegra_clk_m,
1276 .cf_min = 1000000,
1277 .cf_max = 6000000,
1278 .vco_min = 480000000,
1279 .vco_max = 960000000,
1280 .pll_table = tegra_pll_u_table,
1281 .max_rate = 480000000,
1282 };
1283
1284 static struct clk_pll_table tegra_pll_x_table[] = {
1285 /* 1 GHz */
1286 { 12000000, 1000000000, 1000, 12, 1, 12},
1287 { 13000000, 1000000000, 1000, 13, 1, 12},
1288 { 19200000, 1000000000, 625, 12, 1, 8},
1289 { 26000000, 1000000000, 1000, 26, 1, 12},
1290
1291 /* 912 MHz */
1292 { 12000000, 912000000, 912, 12, 1, 12},
1293 { 13000000, 912000000, 912, 13, 1, 12},
1294 { 19200000, 912000000, 760, 16, 1, 8},
1295 { 26000000, 912000000, 912, 26, 1, 12},
1296
1297 /* 816 MHz */
1298 { 12000000, 816000000, 816, 12, 1, 12},
1299 { 13000000, 816000000, 816, 13, 1, 12},
1300 { 19200000, 816000000, 680, 16, 1, 8},
1301 { 26000000, 816000000, 816, 26, 1, 12},
1302
1303 /* 760 MHz */
1304 { 12000000, 760000000, 760, 12, 1, 12},
1305 { 13000000, 760000000, 760, 13, 1, 12},
1306 { 19200000, 760000000, 950, 24, 1, 8},
1307 { 26000000, 760000000, 760, 26, 1, 12},
1308
1309 /* 608 MHz */
1310 { 12000000, 608000000, 760, 12, 1, 12},
1311 { 13000000, 608000000, 760, 13, 1, 12},
1312 { 19200000, 608000000, 380, 12, 1, 8},
1313 { 26000000, 608000000, 760, 26, 1, 12},
1314
1315 /* 456 MHz */
1316 { 12000000, 456000000, 456, 12, 1, 12},
1317 { 13000000, 456000000, 456, 13, 1, 12},
1318 { 19200000, 456000000, 380, 16, 1, 8},
1319 { 26000000, 456000000, 456, 26, 1, 12},
1320
1321 /* 312 MHz */
1322 { 12000000, 312000000, 312, 12, 1, 12},
1323 { 13000000, 312000000, 312, 13, 1, 12},
1324 { 19200000, 312000000, 260, 16, 1, 8},
1325 { 26000000, 312000000, 312, 26, 1, 12},
1326
1327 { 0, 0, 0, 0, 0, 0 },
1328 };
1329
1330 static struct clk tegra_pll_x = {
1331 .name = "pll_x",
1332 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
1333 .ops = &tegra_pllx_ops,
1334 .reg = 0xe0,
1335 .input_min = 2000000,
1336 .input_max = 31000000,
1337 .parent = &tegra_clk_m,
1338 .cf_min = 1000000,
1339 .cf_max = 6000000,
1340 .vco_min = 20000000,
1341 .vco_max = 1200000000,
1342 .pll_table = tegra_pll_x_table,
1343 .max_rate = 1000000000,
1344 };
1345
1346 static struct clk_pll_table tegra_pll_e_table[] = {
1347 { 12000000, 100000000, 200, 24, 1, 0 },
1348 { 0, 0, 0, 0, 0, 0 },
1349 };
1350
1351 static struct clk tegra_pll_e = {
1352 .name = "pll_e",
1353 .flags = PLL_ALT_MISC_REG,
1354 .ops = &tegra_plle_ops,
1355 .input_min = 12000000,
1356 .input_max = 12000000,
1357 .max_rate = 100000000,
1358 .parent = &tegra_clk_m,
1359 .reg = 0xe8,
1360 .pll_table = tegra_pll_e_table,
1361 };
1362
1363 static struct clk tegra_clk_d = {
1364 .name = "clk_d",
1365 .flags = PERIPH_NO_RESET,
1366 .ops = &tegra_clk_double_ops,
1367 .clk_num = 90,
1368 .reg = 0x34,
1369 .reg_shift = 12,
1370 .parent = &tegra_clk_m,
1371 .max_rate = 52000000,
1372 };
1373
1374 /* initialized before peripheral clocks */
1375 static struct clk_mux_sel mux_audio_sync_clk[8+1];
1376 static const struct audio_sources {
1377 const char *name;
1378 int value;
1379 } mux_audio_sync_clk_sources[] = {
1380 { .name = "spdif_in", .value = 0 },
1381 { .name = "i2s1", .value = 1 },
1382 { .name = "i2s2", .value = 2 },
1383 { .name = "pll_a_out0", .value = 4 },
1384 #if 0 /* FIXME: not implemented */
1385 { .name = "ac97", .value = 3 },
1386 { .name = "ext_audio_clk2", .value = 5 },
1387 { .name = "ext_audio_clk1", .value = 6 },
1388 { .name = "ext_vimclk", .value = 7 },
1389 #endif
1390 { 0, 0 }
1391 };
1392
1393 static struct clk tegra_clk_audio = {
1394 .name = "audio",
1395 .inputs = mux_audio_sync_clk,
1396 .reg = 0x38,
1397 .max_rate = 24000000,
1398 .ops = &tegra_audio_sync_clk_ops
1399 };
1400
1401 static struct clk tegra_clk_audio_2x = {
1402 .name = "audio_2x",
1403 .flags = PERIPH_NO_RESET,
1404 .max_rate = 48000000,
1405 .ops = &tegra_clk_double_ops,
1406 .clk_num = 89,
1407 .reg = 0x34,
1408 .reg_shift = 8,
1409 .parent = &tegra_clk_audio,
1410 };
1411
1412 struct clk_lookup tegra_audio_clk_lookups[] = {
1413 { .con_id = "audio", .clk = &tegra_clk_audio },
1414 { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
1415 };
1416
1417 /* This is called after peripheral clocks are initialized, as the
1418 * audio_sync clock depends on some of the peripheral clocks.
1419 */
1420
1421 static void init_audio_sync_clock_mux(void)
1422 {
1423 int i;
1424 struct clk_mux_sel *sel = mux_audio_sync_clk;
1425 const struct audio_sources *src = mux_audio_sync_clk_sources;
1426 struct clk_lookup *lookup;
1427
1428 for (i = 0; src->name; i++, sel++, src++) {
1429 sel->input = tegra_get_clock_by_name(src->name);
1430 if (!sel->input)
1431 pr_err("%s: could not find clk %s\n", __func__,
1432 src->name);
1433 sel->value = src->value;
1434 }
1435
1436 lookup = tegra_audio_clk_lookups;
1437 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
1438 clk_init(lookup->clk);
1439 clkdev_add(lookup);
1440 }
1441 }
1442
1443 static struct clk_mux_sel mux_cclk[] = {
1444 { .input = &tegra_clk_m, .value = 0},
1445 { .input = &tegra_pll_c, .value = 1},
1446 { .input = &tegra_clk_32k, .value = 2},
1447 { .input = &tegra_pll_m, .value = 3},
1448 { .input = &tegra_pll_p, .value = 4},
1449 { .input = &tegra_pll_p_out4, .value = 5},
1450 { .input = &tegra_pll_p_out3, .value = 6},
1451 { .input = &tegra_clk_d, .value = 7},
1452 { .input = &tegra_pll_x, .value = 8},
1453 { 0, 0},
1454 };
1455
1456 static struct clk_mux_sel mux_sclk[] = {
1457 { .input = &tegra_clk_m, .value = 0},
1458 { .input = &tegra_pll_c_out1, .value = 1},
1459 { .input = &tegra_pll_p_out4, .value = 2},
1460 { .input = &tegra_pll_p_out3, .value = 3},
1461 { .input = &tegra_pll_p_out2, .value = 4},
1462 { .input = &tegra_clk_d, .value = 5},
1463 { .input = &tegra_clk_32k, .value = 6},
1464 { .input = &tegra_pll_m_out1, .value = 7},
1465 { 0, 0},
1466 };
1467
1468 static struct clk tegra_clk_cclk = {
1469 .name = "cclk",
1470 .inputs = mux_cclk,
1471 .reg = 0x20,
1472 .ops = &tegra_super_ops,
1473 .max_rate = 1000000000,
1474 };
1475
1476 static struct clk tegra_clk_sclk = {
1477 .name = "sclk",
1478 .inputs = mux_sclk,
1479 .reg = 0x28,
1480 .ops = &tegra_super_ops,
1481 .max_rate = 600000000,
1482 };
1483
1484 static struct clk tegra_clk_virtual_cpu = {
1485 .name = "cpu",
1486 .parent = &tegra_clk_cclk,
1487 .main = &tegra_pll_x,
1488 .backup = &tegra_clk_m,
1489 .ops = &tegra_cpu_ops,
1490 .max_rate = 1000000000,
1491 .dvfs = &tegra_dvfs_virtual_cpu_dvfs,
1492 };
1493
1494 static struct clk tegra_clk_hclk = {
1495 .name = "hclk",
1496 .flags = DIV_BUS,
1497 .parent = &tegra_clk_sclk,
1498 .reg = 0x30,
1499 .reg_shift = 4,
1500 .ops = &tegra_bus_ops,
1501 .max_rate = 240000000,
1502 };
1503
1504 static struct clk tegra_clk_pclk = {
1505 .name = "pclk",
1506 .flags = DIV_BUS,
1507 .parent = &tegra_clk_hclk,
1508 .reg = 0x30,
1509 .reg_shift = 0,
1510 .ops = &tegra_bus_ops,
1511 .max_rate = 108000000,
1512 };
1513
1514 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
1515 { .input = &tegra_pll_m, .value = 0},
1516 { .input = &tegra_pll_c, .value = 1},
1517 { .input = &tegra_pll_p, .value = 2},
1518 { .input = &tegra_pll_a_out0, .value = 3},
1519 { 0, 0},
1520 };
1521
1522 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
1523 { .input = &tegra_pll_m, .value = 0},
1524 { .input = &tegra_pll_c, .value = 1},
1525 { .input = &tegra_pll_p, .value = 2},
1526 { .input = &tegra_clk_m, .value = 3},
1527 { 0, 0},
1528 };
1529
1530 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
1531 { .input = &tegra_pll_p, .value = 0},
1532 { .input = &tegra_pll_c, .value = 1},
1533 { .input = &tegra_pll_m, .value = 2},
1534 { .input = &tegra_clk_m, .value = 3},
1535 { 0, 0},
1536 };
1537
1538 static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
1539 {.input = &tegra_pll_a_out0, .value = 0},
1540 {.input = &tegra_clk_audio_2x, .value = 1},
1541 {.input = &tegra_pll_p, .value = 2},
1542 {.input = &tegra_clk_m, .value = 3},
1543 { 0, 0},
1544 };
1545
1546 static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
1547 {.input = &tegra_pll_p, .value = 0},
1548 {.input = &tegra_pll_d_out0, .value = 1},
1549 {.input = &tegra_pll_c, .value = 2},
1550 {.input = &tegra_clk_m, .value = 3},
1551 { 0, 0},
1552 };
1553
1554 static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
1555 {.input = &tegra_pll_p, .value = 0},
1556 {.input = &tegra_pll_c, .value = 1},
1557 {.input = &tegra_clk_audio, .value = 2},
1558 {.input = &tegra_clk_m, .value = 3},
1559 {.input = &tegra_clk_32k, .value = 4},
1560 { 0, 0},
1561 };
1562
1563 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
1564 {.input = &tegra_pll_p, .value = 0},
1565 {.input = &tegra_pll_c, .value = 1},
1566 {.input = &tegra_pll_m, .value = 2},
1567 { 0, 0},
1568 };
1569
1570 static struct clk_mux_sel mux_clk_m[] = {
1571 { .input = &tegra_clk_m, .value = 0},
1572 { 0, 0},
1573 };
1574
1575 static struct clk_mux_sel mux_pllp_out3[] = {
1576 { .input = &tegra_pll_p_out3, .value = 0},
1577 { 0, 0},
1578 };
1579
1580 static struct clk_mux_sel mux_plld[] = {
1581 { .input = &tegra_pll_d, .value = 0},
1582 { 0, 0},
1583 };
1584
1585 static struct clk_mux_sel mux_clk_32k[] = {
1586 { .input = &tegra_clk_32k, .value = 0},
1587 { 0, 0},
1588 };
1589
1590 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
1591 { \
1592 .name = _name, \
1593 .lookup = { \
1594 .dev_id = _dev, \
1595 .con_id = _con, \
1596 }, \
1597 .ops = &tegra_periph_clk_ops, \
1598 .clk_num = _clk_num, \
1599 .reg = _reg, \
1600 .inputs = _inputs, \
1601 .flags = _flags, \
1602 .max_rate = _max, \
1603 }
1604
1605 struct clk tegra_periph_clks[] = {
1606 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
1607 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
1608 PERIPH_CLK("i2s1", "i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
1609 PERIPH_CLK("i2s2", "i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
1610 /* FIXME: spdif has 2 clocks but 1 enable */
1611 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
1612 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
1613 PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71),
1614 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1615 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1616 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1617 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1618 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1619 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1620 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1621 PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
1622 PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1623 /* FIXME: vfir shares an enable with uartb */
1624 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1625 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1626 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1627 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1628 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x160, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1629 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
1630 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
1631 /* FIXME: what is la? */
1632 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1633 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1634 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
1635 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1636 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1637 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1638 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1639 PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1640 PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1641 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1642 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1643 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1644 PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, 216000000, mux_pllp_pllc_pllm_clkm, MUX),
1645 PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, 216000000, mux_pllp_pllc_pllm_clkm, MUX),
1646 PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, 216000000, mux_pllp_pllc_pllm_clkm, MUX),
1647 PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, 216000000, mux_pllp_pllc_pllm_clkm, MUX),
1648 PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, 216000000, mux_pllp_pllc_pllm_clkm, MUX),
1649 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
1650 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1651 /* FIXME: vi and vi_sensor share an enable */
1652 PERIPH_CLK("vi", "vi", NULL, 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1653 PERIPH_CLK("vi_sensor", "vi_sensor", NULL, 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
1654 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1655 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1656 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1657 /* FIXME: cve and tvo share an enable */
1658 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1659 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1660 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1661 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1662 PERIPH_CLK("disp1", "tegrafb.0", NULL, 27, 0x138, 190000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
1663 PERIPH_CLK("disp2", "tegrafb.1", NULL, 26, 0x13c, 190000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
1664 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
1665 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
1666 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
1667 PERIPH_CLK("emc", "emc", NULL, 57, 0x19c, 800000000, mux_pllm_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_EMC_ENB),
1668 PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */
1669 PERIPH_CLK("csi", "csi", NULL, 52, 0, 72000000, mux_pllp_out3, 0),
1670 PERIPH_CLK("isp", "isp", NULL, 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
1671 PERIPH_CLK("csus", "csus", NULL, 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
1672 PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
1673 PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
1674 PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
1675 };
1676
1677 #define CLK_DUPLICATE(_name, _dev, _con) \
1678 { \
1679 .name = _name, \
1680 .lookup = { \
1681 .dev_id = _dev, \
1682 .con_id = _con, \
1683 }, \
1684 }
1685
1686 /* Some clocks may be used by different drivers depending on the board
1687 * configuration. List those here to register them twice in the clock lookup
1688 * table under two names.
1689 */
1690 struct clk_duplicate tegra_clk_duplicates[] = {
1691 CLK_DUPLICATE("uarta", "tegra_uart.0", NULL),
1692 CLK_DUPLICATE("uartb", "tegra_uart.1", NULL),
1693 CLK_DUPLICATE("uartc", "tegra_uart.2", NULL),
1694 CLK_DUPLICATE("uartd", "tegra_uart.3", NULL),
1695 CLK_DUPLICATE("uarte", "tegra_uart.4", NULL),
1696 CLK_DUPLICATE("host1x", "tegrafb.0", "host1x"),
1697 CLK_DUPLICATE("host1x", "tegrafb.1", "host1x"),
1698 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1699 };
1700
1701 #define CLK(dev, con, ck) \
1702 { \
1703 .dev_id = dev, \
1704 .con_id = con, \
1705 .clk = ck, \
1706 }
1707
1708 struct clk_lookup tegra_clk_lookups[] = {
1709 /* external root sources */
1710 CLK(NULL, "32k_clk", &tegra_clk_32k),
1711 CLK(NULL, "pll_s", &tegra_pll_s),
1712 CLK(NULL, "clk_m", &tegra_clk_m),
1713 CLK(NULL, "pll_m", &tegra_pll_m),
1714 CLK(NULL, "pll_m_out1", &tegra_pll_m_out1),
1715 CLK(NULL, "pll_c", &tegra_pll_c),
1716 CLK(NULL, "pll_c_out1", &tegra_pll_c_out1),
1717 CLK(NULL, "pll_p", &tegra_pll_p),
1718 CLK(NULL, "pll_p_out1", &tegra_pll_p_out1),
1719 CLK(NULL, "pll_p_out2", &tegra_pll_p_out2),
1720 CLK(NULL, "pll_p_out3", &tegra_pll_p_out3),
1721 CLK(NULL, "pll_p_out4", &tegra_pll_p_out4),
1722 CLK(NULL, "pll_a", &tegra_pll_a),
1723 CLK(NULL, "pll_a_out0", &tegra_pll_a_out0),
1724 CLK(NULL, "pll_d", &tegra_pll_d),
1725 CLK(NULL, "pll_d_out0", &tegra_pll_d_out0),
1726 CLK(NULL, "pll_u", &tegra_pll_u),
1727 CLK(NULL, "pll_x", &tegra_pll_x),
1728 CLK(NULL, "pll_e", &tegra_pll_e),
1729 CLK(NULL, "cclk", &tegra_clk_cclk),
1730 CLK(NULL, "sclk", &tegra_clk_sclk),
1731 CLK(NULL, "hclk", &tegra_clk_hclk),
1732 CLK(NULL, "pclk", &tegra_clk_pclk),
1733 CLK(NULL, "clk_d", &tegra_clk_d),
1734 CLK(NULL, "cpu", &tegra_clk_virtual_cpu),
1735 };
1736
1737 void __init tegra2_init_clocks(void)
1738 {
1739 int i;
1740 struct clk_lookup *cl;
1741 struct clk *c;
1742 struct clk_duplicate *cd;
1743
1744 for (i = 0; i < ARRAY_SIZE(tegra_clk_lookups); i++) {
1745 cl = &tegra_clk_lookups[i];
1746 clk_init(cl->clk);
1747 clkdev_add(cl);
1748 }
1749
1750 for (i = 0; i < ARRAY_SIZE(tegra_periph_clks); i++) {
1751 c = &tegra_periph_clks[i];
1752 cl = &c->lookup;
1753 cl->clk = c;
1754
1755 clk_init(cl->clk);
1756 clkdev_add(cl);
1757 }
1758
1759 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1760 cd = &tegra_clk_duplicates[i];
1761 c = tegra_get_clock_by_name(cd->name);
1762 if (c) {
1763 cl = &cd->lookup;
1764 cl->clk = c;
1765 clkdev_add(cl);
1766 } else {
1767 pr_err("%s: Unknown duplicate clock %s\n", __func__,
1768 cd->name);
1769 }
1770 }
1771
1772 init_audio_sync_clock_mux();
1773 }
1774
1775 #ifdef CONFIG_PM
1776 static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
1777 PERIPH_CLK_SOURCE_NUM + 3];
1778
1779 void tegra_clk_suspend(void)
1780 {
1781 unsigned long off, i;
1782 u32 *ctx = clk_rst_suspend;
1783
1784 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
1785
1786 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
1787 off += 4) {
1788 if (off == PERIPH_CLK_SOURCE_EMC)
1789 continue;
1790 *ctx++ = clk_readl(off);
1791 }
1792
1793 off = RST_DEVICES;
1794 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
1795 *ctx++ = clk_readl(off);
1796
1797 off = CLK_OUT_ENB;
1798 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
1799 *ctx++ = clk_readl(off);
1800
1801 *ctx++ = clk_readl(MISC_CLK_ENB);
1802 *ctx++ = clk_readl(CLK_MASK_ARM);
1803 }
1804
1805 void tegra_clk_resume(void)
1806 {
1807 unsigned long off, i;
1808 const u32 *ctx = clk_rst_suspend;
1809 u32 val;
1810
1811 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
1812 val |= *ctx++;
1813 clk_writel(val, OSC_CTRL);
1814
1815 /* enable all clocks before configuring clock sources */
1816 clk_writel(0xbffffff9ul, CLK_OUT_ENB);
1817 clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
1818 clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
1819 wmb();
1820
1821 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
1822 off += 4) {
1823 if (off == PERIPH_CLK_SOURCE_EMC)
1824 continue;
1825 clk_writel(*ctx++, off);
1826 }
1827 wmb();
1828
1829 off = RST_DEVICES;
1830 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
1831 clk_writel(*ctx++, off);
1832 wmb();
1833
1834 off = CLK_OUT_ENB;
1835 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
1836 clk_writel(*ctx++, off);
1837 wmb();
1838
1839 clk_writel(*ctx++, MISC_CLK_ENB);
1840 clk_writel(*ctx++, CLK_MASK_ARM);
1841 }
1842 #endif
kernel source for telekom puls (alcatel/mediatek)