arch/arm/mach-shmobile/setup-sh7372.c

   1 /*
   2  * sh7372 processor support
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2008  Yoshihiro Shimoda
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/uio_driver.h>
  27 #include <linux/delay.h>
  28 #include <linux/input.h>
  29 #include <linux/io.h>
  30 #include <linux/serial_sci.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/sh_intc.h>
  33 #include <linux/sh_timer.h>
  34 #include <linux/pm_domain.h>
  35 #include <linux/dma-mapping.h>
  36 #include <mach/dma-register.h>
  37 #include <mach/hardware.h>
  38 #include <mach/irqs.h>
  39 #include <mach/sh7372.h>
  40 #include <mach/common.h>
  41 #include <asm/mach/map.h>
  42 #include <asm/mach-types.h>
  43 #include <asm/mach/arch.h>
  44 #include <asm/mach/time.h>
  45
  46 static struct map_desc sh7372_io_desc[] __initdata = {
  47         /* create a 1:1 entity map for 0xe6xxxxxx
  48          * used by CPGA, INTC and PFC.
  49          */
  50         {
  51                 .virtual        = 0xe6000000,
  52                 .pfn            = __phys_to_pfn(0xe6000000),
  53                 .length         = 256 << 20,
  54                 .type           = MT_DEVICE_NONSHARED
  55         },
  56 };
  57
  58 void __init sh7372_map_io(void)
  59 {
  60         iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
  61 }
  62
  63 /* SCIFA0 */
  64 static struct plat_sci_port scif0_platform_data = {
  65         .mapbase        = 0xe6c40000,
  66         .flags          = UPF_BOOT_AUTOCONF,
  67         .scscr          = SCSCR_RE | SCSCR_TE,
  68         .scbrr_algo_id  = SCBRR_ALGO_4,
  69         .type           = PORT_SCIFA,
  70         .irqs           = { evt2irq(0x0c00), evt2irq(0x0c00),
  71                             evt2irq(0x0c00), evt2irq(0x0c00) },
  72 };
  73
  74 static struct platform_device scif0_device = {
  75         .name           = "sh-sci",
  76         .id             = 0,
  77         .dev            = {
  78                 .platform_data  = &scif0_platform_data,
  79         },
  80 };
  81
  82 /* SCIFA1 */
  83 static struct plat_sci_port scif1_platform_data = {
  84         .mapbase        = 0xe6c50000,
  85         .flags          = UPF_BOOT_AUTOCONF,
  86         .scscr          = SCSCR_RE | SCSCR_TE,
  87         .scbrr_algo_id  = SCBRR_ALGO_4,
  88         .type           = PORT_SCIFA,
  89         .irqs           = { evt2irq(0x0c20), evt2irq(0x0c20),
  90                             evt2irq(0x0c20), evt2irq(0x0c20) },
  91 };
  92
  93 static struct platform_device scif1_device = {
  94         .name           = "sh-sci",
  95         .id             = 1,
  96         .dev            = {
  97                 .platform_data  = &scif1_platform_data,
  98         },
  99 };
 100
 101 /* SCIFA2 */
 102 static struct plat_sci_port scif2_platform_data = {
 103         .mapbase        = 0xe6c60000,
 104         .flags          = UPF_BOOT_AUTOCONF,
 105         .scscr          = SCSCR_RE | SCSCR_TE,
 106         .scbrr_algo_id  = SCBRR_ALGO_4,
 107         .type           = PORT_SCIFA,
 108         .irqs           = { evt2irq(0x0c40), evt2irq(0x0c40),
 109                             evt2irq(0x0c40), evt2irq(0x0c40) },
 110 };
 111
 112 static struct platform_device scif2_device = {
 113         .name           = "sh-sci",
 114         .id             = 2,
 115         .dev            = {
 116                 .platform_data  = &scif2_platform_data,
 117         },
 118 };
 119
 120 /* SCIFA3 */
 121 static struct plat_sci_port scif3_platform_data = {
 122         .mapbase        = 0xe6c70000,
 123         .flags          = UPF_BOOT_AUTOCONF,
 124         .scscr          = SCSCR_RE | SCSCR_TE,
 125         .scbrr_algo_id  = SCBRR_ALGO_4,
 126         .type           = PORT_SCIFA,
 127         .irqs           = { evt2irq(0x0c60), evt2irq(0x0c60),
 128                             evt2irq(0x0c60), evt2irq(0x0c60) },
 129 };
 130
 131 static struct platform_device scif3_device = {
 132         .name           = "sh-sci",
 133         .id             = 3,
 134         .dev            = {
 135                 .platform_data  = &scif3_platform_data,
 136         },
 137 };
 138
 139 /* SCIFA4 */
 140 static struct plat_sci_port scif4_platform_data = {
 141         .mapbase        = 0xe6c80000,
 142         .flags          = UPF_BOOT_AUTOCONF,
 143         .scscr          = SCSCR_RE | SCSCR_TE,
 144         .scbrr_algo_id  = SCBRR_ALGO_4,
 145         .type           = PORT_SCIFA,
 146         .irqs           = { evt2irq(0x0d20), evt2irq(0x0d20),
 147                             evt2irq(0x0d20), evt2irq(0x0d20) },
 148 };
 149
 150 static struct platform_device scif4_device = {
 151         .name           = "sh-sci",
 152         .id             = 4,
 153         .dev            = {
 154                 .platform_data  = &scif4_platform_data,
 155         },
 156 };
 157
 158 /* SCIFA5 */
 159 static struct plat_sci_port scif5_platform_data = {
 160         .mapbase        = 0xe6cb0000,
 161         .flags          = UPF_BOOT_AUTOCONF,
 162         .scscr          = SCSCR_RE | SCSCR_TE,
 163         .scbrr_algo_id  = SCBRR_ALGO_4,
 164         .type           = PORT_SCIFA,
 165         .irqs           = { evt2irq(0x0d40), evt2irq(0x0d40),
 166                             evt2irq(0x0d40), evt2irq(0x0d40) },
 167 };
 168
 169 static struct platform_device scif5_device = {
 170         .name           = "sh-sci",
 171         .id             = 5,
 172         .dev            = {
 173                 .platform_data  = &scif5_platform_data,
 174         },
 175 };
 176
 177 /* SCIFB */
 178 static struct plat_sci_port scif6_platform_data = {
 179         .mapbase        = 0xe6c30000,
 180         .flags          = UPF_BOOT_AUTOCONF,
 181         .scscr          = SCSCR_RE | SCSCR_TE,
 182         .scbrr_algo_id  = SCBRR_ALGO_4,
 183         .type           = PORT_SCIFB,
 184         .irqs           = { evt2irq(0x0d60), evt2irq(0x0d60),
 185                             evt2irq(0x0d60), evt2irq(0x0d60) },
 186 };
 187
 188 static struct platform_device scif6_device = {
 189         .name           = "sh-sci",
 190         .id             = 6,
 191         .dev            = {
 192                 .platform_data  = &scif6_platform_data,
 193         },
 194 };
 195
 196 /* CMT */
 197 static struct sh_timer_config cmt2_platform_data = {
 198         .name = "CMT2",
 199         .channel_offset = 0x40,
 200         .timer_bit = 5,
 201         .clockevent_rating = 125,
 202         .clocksource_rating = 125,
 203 };
 204
 205 static struct resource cmt2_resources[] = {
 206         [0] = {
 207                 .name   = "CMT2",
 208                 .start  = 0xe6130040,
 209                 .end    = 0xe613004b,
 210                 .flags  = IORESOURCE_MEM,
 211         },
 212         [1] = {
 213                 .start  = evt2irq(0x0b80), /* CMT2 */
 214                 .flags  = IORESOURCE_IRQ,
 215         },
 216 };
 217
 218 static struct platform_device cmt2_device = {
 219         .name           = "sh_cmt",
 220         .id             = 2,
 221         .dev = {
 222                 .platform_data  = &cmt2_platform_data,
 223         },
 224         .resource       = cmt2_resources,
 225         .num_resources  = ARRAY_SIZE(cmt2_resources),
 226 };
 227
 228 /* TMU */
 229 static struct sh_timer_config tmu00_platform_data = {
 230         .name = "TMU00",
 231         .channel_offset = 0x4,
 232         .timer_bit = 0,
 233         .clockevent_rating = 200,
 234 };
 235
 236 static struct resource tmu00_resources[] = {
 237         [0] = {
 238                 .name   = "TMU00",
 239                 .start  = 0xfff60008,
 240                 .end    = 0xfff60013,
 241                 .flags  = IORESOURCE_MEM,
 242         },
 243         [1] = {
 244                 .start  = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
 245                 .flags  = IORESOURCE_IRQ,
 246         },
 247 };
 248
 249 static struct platform_device tmu00_device = {
 250         .name           = "sh_tmu",
 251         .id             = 0,
 252         .dev = {
 253                 .platform_data  = &tmu00_platform_data,
 254         },
 255         .resource       = tmu00_resources,
 256         .num_resources  = ARRAY_SIZE(tmu00_resources),
 257 };
 258
 259 static struct sh_timer_config tmu01_platform_data = {
 260         .name = "TMU01",
 261         .channel_offset = 0x10,
 262         .timer_bit = 1,
 263         .clocksource_rating = 200,
 264 };
 265
 266 static struct resource tmu01_resources[] = {
 267         [0] = {
 268                 .name   = "TMU01",
 269                 .start  = 0xfff60014,
 270                 .end    = 0xfff6001f,
 271                 .flags  = IORESOURCE_MEM,
 272         },
 273         [1] = {
 274                 .start  = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
 275                 .flags  = IORESOURCE_IRQ,
 276         },
 277 };
 278
 279 static struct platform_device tmu01_device = {
 280         .name           = "sh_tmu",
 281         .id             = 1,
 282         .dev = {
 283                 .platform_data  = &tmu01_platform_data,
 284         },
 285         .resource       = tmu01_resources,
 286         .num_resources  = ARRAY_SIZE(tmu01_resources),
 287 };
 288
 289 /* I2C */
 290 static struct resource iic0_resources[] = {
 291         [0] = {
 292                 .name   = "IIC0",
 293                 .start  = 0xFFF20000,
 294                 .end    = 0xFFF20425 - 1,
 295                 .flags  = IORESOURCE_MEM,
 296         },
 297         [1] = {
 298                 .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
 299                 .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
 300                 .flags  = IORESOURCE_IRQ,
 301         },
 302 };
 303
 304 static struct platform_device iic0_device = {
 305         .name           = "i2c-sh_mobile",
 306         .id             = 0, /* "i2c0" clock */
 307         .num_resources  = ARRAY_SIZE(iic0_resources),
 308         .resource       = iic0_resources,
 309 };
 310
 311 static struct resource iic1_resources[] = {
 312         [0] = {
 313                 .name   = "IIC1",
 314                 .start  = 0xE6C20000,
 315                 .end    = 0xE6C20425 - 1,
 316                 .flags  = IORESOURCE_MEM,
 317         },
 318         [1] = {
 319                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
 320                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
 321                 .flags  = IORESOURCE_IRQ,
 322         },
 323 };
 324
 325 static struct platform_device iic1_device = {
 326         .name           = "i2c-sh_mobile",
 327         .id             = 1, /* "i2c1" clock */
 328         .num_resources  = ARRAY_SIZE(iic1_resources),
 329         .resource       = iic1_resources,
 330 };
 331
 332 /* DMA */
 333 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
 334         {
 335                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 336                 .addr           = 0xe6c40020,
 337                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 338                 .mid_rid        = 0x21,
 339         }, {
 340                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 341                 .addr           = 0xe6c40024,
 342                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 343                 .mid_rid        = 0x22,
 344         }, {
 345                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 346                 .addr           = 0xe6c50020,
 347                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 348                 .mid_rid        = 0x25,
 349         }, {
 350                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 351                 .addr           = 0xe6c50024,
 352                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 353                 .mid_rid        = 0x26,
 354         }, {
 355                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 356                 .addr           = 0xe6c60020,
 357                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 358                 .mid_rid        = 0x29,
 359         }, {
 360                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 361                 .addr           = 0xe6c60024,
 362                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 363                 .mid_rid        = 0x2a,
 364         }, {
 365                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 366                 .addr           = 0xe6c70020,
 367                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 368                 .mid_rid        = 0x2d,
 369         }, {
 370                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 371                 .addr           = 0xe6c70024,
 372                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 373                 .mid_rid        = 0x2e,
 374         }, {
 375                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 376                 .addr           = 0xe6c80020,
 377                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 378                 .mid_rid        = 0x39,
 379         }, {
 380                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 381                 .addr           = 0xe6c80024,
 382                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 383                 .mid_rid        = 0x3a,
 384         }, {
 385                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 386                 .addr           = 0xe6cb0020,
 387                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 388                 .mid_rid        = 0x35,
 389         }, {
 390                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 391                 .addr           = 0xe6cb0024,
 392                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 393                 .mid_rid        = 0x36,
 394         }, {
 395                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 396                 .addr           = 0xe6c30040,
 397                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 398                 .mid_rid        = 0x3d,
 399         }, {
 400                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 401                 .addr           = 0xe6c30060,
 402                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 403                 .mid_rid        = 0x3e,
 404         }, {
 405                 .slave_id       = SHDMA_SLAVE_FLCTL0_TX,
 406                 .addr           = 0xe6a30050,
 407                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 408                 .mid_rid        = 0x83,
 409         }, {
 410                 .slave_id       = SHDMA_SLAVE_FLCTL0_RX,
 411                 .addr           = 0xe6a30050,
 412                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 413                 .mid_rid        = 0x83,
 414         }, {
 415                 .slave_id       = SHDMA_SLAVE_FLCTL1_TX,
 416                 .addr           = 0xe6a30060,
 417                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 418                 .mid_rid        = 0x87,
 419         }, {
 420                 .slave_id       = SHDMA_SLAVE_FLCTL1_RX,
 421                 .addr           = 0xe6a30060,
 422                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 423                 .mid_rid        = 0x87,
 424         }, {
 425                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 426                 .addr           = 0xe6850030,
 427                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 428                 .mid_rid        = 0xc1,
 429         }, {
 430                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 431                 .addr           = 0xe6850030,
 432                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 433                 .mid_rid        = 0xc2,
 434         }, {
 435                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 436                 .addr           = 0xe6860030,
 437                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 438                 .mid_rid        = 0xc9,
 439         }, {
 440                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 441                 .addr           = 0xe6860030,
 442                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 443                 .mid_rid        = 0xca,
 444         }, {
 445                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 446                 .addr           = 0xe6870030,
 447                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 448                 .mid_rid        = 0xcd,
 449         }, {
 450                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 451                 .addr           = 0xe6870030,
 452                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 453                 .mid_rid        = 0xce,
 454         }, {
 455                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 456                 .addr           = 0xfe1f0024,
 457                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 458                 .mid_rid        = 0xb1,
 459         }, {
 460                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 461                 .addr           = 0xfe1f0020,
 462                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 463                 .mid_rid        = 0xb2,
 464         }, {
 465                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 466                 .addr           = 0xe6bd0034,
 467                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 468                 .mid_rid        = 0xd1,
 469         }, {
 470                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 471                 .addr           = 0xe6bd0034,
 472                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 473                 .mid_rid        = 0xd2,
 474         },
 475 };
 476
 477 #define SH7372_CHCLR (0x220 - 0x20)
 478
 479 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
 480         {
 481                 .offset = 0,
 482                 .dmars = 0,
 483                 .dmars_bit = 0,
 484                 .chclr_offset = SH7372_CHCLR + 0,
 485         }, {
 486                 .offset = 0x10,
 487                 .dmars = 0,
 488                 .dmars_bit = 8,
 489                 .chclr_offset = SH7372_CHCLR + 0x10,
 490         }, {
 491                 .offset = 0x20,
 492                 .dmars = 4,
 493                 .dmars_bit = 0,
 494                 .chclr_offset = SH7372_CHCLR + 0x20,
 495         }, {
 496                 .offset = 0x30,
 497                 .dmars = 4,
 498                 .dmars_bit = 8,
 499                 .chclr_offset = SH7372_CHCLR + 0x30,
 500         }, {
 501                 .offset = 0x50,
 502                 .dmars = 8,
 503                 .dmars_bit = 0,
 504                 .chclr_offset = SH7372_CHCLR + 0x50,
 505         }, {
 506                 .offset = 0x60,
 507                 .dmars = 8,
 508                 .dmars_bit = 8,
 509                 .chclr_offset = SH7372_CHCLR + 0x60,
 510         }
 511 };
 512
 513 static struct sh_dmae_pdata dma_platform_data = {
 514         .slave          = sh7372_dmae_slaves,
 515         .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
 516         .channel        = sh7372_dmae_channels,
 517         .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
 518         .ts_low_shift   = TS_LOW_SHIFT,
 519         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 520         .ts_high_shift  = TS_HI_SHIFT,
 521         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 522         .ts_shift       = dma_ts_shift,
 523         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 524         .dmaor_init     = DMAOR_DME,
 525         .chclr_present  = 1,
 526 };
 527
 528 /* Resource order important! */
 529 static struct resource sh7372_dmae0_resources[] = {
 530         {
 531                 /* Channel registers and DMAOR */
 532                 .start  = 0xfe008020,
 533                 .end    = 0xfe00828f,
 534                 .flags  = IORESOURCE_MEM,
 535         },
 536         {
 537                 /* DMARSx */
 538                 .start  = 0xfe009000,
 539                 .end    = 0xfe00900b,
 540                 .flags  = IORESOURCE_MEM,
 541         },
 542         {
 543                 .name   = "error_irq",
 544                 .start  = evt2irq(0x20c0),
 545                 .end    = evt2irq(0x20c0),
 546                 .flags  = IORESOURCE_IRQ,
 547         },
 548         {
 549                 /* IRQ for channels 0-5 */
 550                 .start  = evt2irq(0x2000),
 551                 .end    = evt2irq(0x20a0),
 552                 .flags  = IORESOURCE_IRQ,
 553         },
 554 };
 555
 556 /* Resource order important! */
 557 static struct resource sh7372_dmae1_resources[] = {
 558         {
 559                 /* Channel registers and DMAOR */
 560                 .start  = 0xfe018020,
 561                 .end    = 0xfe01828f,
 562                 .flags  = IORESOURCE_MEM,
 563         },
 564         {
 565                 /* DMARSx */
 566                 .start  = 0xfe019000,
 567                 .end    = 0xfe01900b,
 568                 .flags  = IORESOURCE_MEM,
 569         },
 570         {
 571                 .name   = "error_irq",
 572                 .start  = evt2irq(0x21c0),
 573                 .end    = evt2irq(0x21c0),
 574                 .flags  = IORESOURCE_IRQ,
 575         },
 576         {
 577                 /* IRQ for channels 0-5 */
 578                 .start  = evt2irq(0x2100),
 579                 .end    = evt2irq(0x21a0),
 580                 .flags  = IORESOURCE_IRQ,
 581         },
 582 };
 583
 584 /* Resource order important! */
 585 static struct resource sh7372_dmae2_resources[] = {
 586         {
 587                 /* Channel registers and DMAOR */
 588                 .start  = 0xfe028020,
 589                 .end    = 0xfe02828f,
 590                 .flags  = IORESOURCE_MEM,
 591         },
 592         {
 593                 /* DMARSx */
 594                 .start  = 0xfe029000,
 595                 .end    = 0xfe02900b,
 596                 .flags  = IORESOURCE_MEM,
 597         },
 598         {
 599                 .name   = "error_irq",
 600                 .start  = evt2irq(0x22c0),
 601                 .end    = evt2irq(0x22c0),
 602                 .flags  = IORESOURCE_IRQ,
 603         },
 604         {
 605                 /* IRQ for channels 0-5 */
 606                 .start  = evt2irq(0x2200),
 607                 .end    = evt2irq(0x22a0),
 608                 .flags  = IORESOURCE_IRQ,
 609         },
 610 };
 611
 612 static struct platform_device dma0_device = {
 613         .name           = "sh-dma-engine",
 614         .id             = 0,
 615         .resource       = sh7372_dmae0_resources,
 616         .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
 617         .dev            = {
 618                 .platform_data  = &dma_platform_data,
 619         },
 620 };
 621
 622 static struct platform_device dma1_device = {
 623         .name           = "sh-dma-engine",
 624         .id             = 1,
 625         .resource       = sh7372_dmae1_resources,
 626         .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
 627         .dev            = {
 628                 .platform_data  = &dma_platform_data,
 629         },
 630 };
 631
 632 static struct platform_device dma2_device = {
 633         .name           = "sh-dma-engine",
 634         .id             = 2,
 635         .resource       = sh7372_dmae2_resources,
 636         .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
 637         .dev            = {
 638                 .platform_data  = &dma_platform_data,
 639         },
 640 };
 641
 642 /*
 643  * USB-DMAC
 644  */
 645 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
 646         {
 647                 .offset = 0,
 648         }, {
 649                 .offset = 0x20,
 650         },
 651 };
 652
 653 /* USB DMAC0 */
 654 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
 655         {
 656                 .slave_id       = SHDMA_SLAVE_USB0_TX,
 657                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 658         }, {
 659                 .slave_id       = SHDMA_SLAVE_USB0_RX,
 660                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 661         },
 662 };
 663
 664 static struct sh_dmae_pdata usb_dma0_platform_data = {
 665         .slave          = sh7372_usb_dmae0_slaves,
 666         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
 667         .channel        = sh7372_usb_dmae_channels,
 668         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 669         .ts_low_shift   = USBTS_LOW_SHIFT,
 670         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 671         .ts_high_shift  = USBTS_HI_SHIFT,
 672         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 673         .ts_shift       = dma_usbts_shift,
 674         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 675         .dmaor_init     = DMAOR_DME,
 676         .chcr_offset    = 0x14,
 677         .chcr_ie_bit    = 1 << 5,
 678         .dmaor_is_32bit = 1,
 679         .needs_tend_set = 1,
 680         .no_dmars       = 1,
 681         .slave_only     = 1,
 682 };
 683
 684 static struct resource sh7372_usb_dmae0_resources[] = {
 685         {
 686                 /* Channel registers and DMAOR */
 687                 .start  = 0xe68a0020,
 688                 .end    = 0xe68a0064 - 1,
 689                 .flags  = IORESOURCE_MEM,
 690         },
 691         {
 692                 /* VCR/SWR/DMICR */
 693                 .start  = 0xe68a0000,
 694                 .end    = 0xe68a0014 - 1,
 695                 .flags  = IORESOURCE_MEM,
 696         },
 697         {
 698                 /* IRQ for channels */
 699                 .start  = evt2irq(0x0a00),
 700                 .end    = evt2irq(0x0a00),
 701                 .flags  = IORESOURCE_IRQ,
 702         },
 703 };
 704
 705 static struct platform_device usb_dma0_device = {
 706         .name           = "sh-dma-engine",
 707         .id             = 3,
 708         .resource       = sh7372_usb_dmae0_resources,
 709         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae0_resources),
 710         .dev            = {
 711                 .platform_data  = &usb_dma0_platform_data,
 712         },
 713 };
 714
 715 /* USB DMAC1 */
 716 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
 717         {
 718                 .slave_id       = SHDMA_SLAVE_USB1_TX,
 719                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 720         }, {
 721                 .slave_id       = SHDMA_SLAVE_USB1_RX,
 722                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 723         },
 724 };
 725
 726 static struct sh_dmae_pdata usb_dma1_platform_data = {
 727         .slave          = sh7372_usb_dmae1_slaves,
 728         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
 729         .channel        = sh7372_usb_dmae_channels,
 730         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 731         .ts_low_shift   = USBTS_LOW_SHIFT,
 732         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 733         .ts_high_shift  = USBTS_HI_SHIFT,
 734         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 735         .ts_shift       = dma_usbts_shift,
 736         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 737         .dmaor_init     = DMAOR_DME,
 738         .chcr_offset    = 0x14,
 739         .chcr_ie_bit    = 1 << 5,
 740         .dmaor_is_32bit = 1,
 741         .needs_tend_set = 1,
 742         .no_dmars       = 1,
 743         .slave_only     = 1,
 744 };
 745
 746 static struct resource sh7372_usb_dmae1_resources[] = {
 747         {
 748                 /* Channel registers and DMAOR */
 749                 .start  = 0xe68c0020,
 750                 .end    = 0xe68c0064 - 1,
 751                 .flags  = IORESOURCE_MEM,
 752         },
 753         {
 754                 /* VCR/SWR/DMICR */
 755                 .start  = 0xe68c0000,
 756                 .end    = 0xe68c0014 - 1,
 757                 .flags  = IORESOURCE_MEM,
 758         },
 759         {
 760                 /* IRQ for channels */
 761                 .start  = evt2irq(0x1d00),
 762                 .end    = evt2irq(0x1d00),
 763                 .flags  = IORESOURCE_IRQ,
 764         },
 765 };
 766
 767 static struct platform_device usb_dma1_device = {
 768         .name           = "sh-dma-engine",
 769         .id             = 4,
 770         .resource       = sh7372_usb_dmae1_resources,
 771         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae1_resources),
 772         .dev            = {
 773                 .platform_data  = &usb_dma1_platform_data,
 774         },
 775 };
 776
 777 /* VPU */
 778 static struct uio_info vpu_platform_data = {
 779         .name = "VPU5HG",
 780         .version = "0",
 781         .irq = intcs_evt2irq(0x980),
 782 };
 783
 784 static struct resource vpu_resources[] = {
 785         [0] = {
 786                 .name   = "VPU",
 787                 .start  = 0xfe900000,
 788                 .end    = 0xfe900157,
 789                 .flags  = IORESOURCE_MEM,
 790         },
 791 };
 792
 793 static struct platform_device vpu_device = {
 794         .name           = "uio_pdrv_genirq",
 795         .id             = 0,
 796         .dev = {
 797                 .platform_data  = &vpu_platform_data,
 798         },
 799         .resource       = vpu_resources,
 800         .num_resources  = ARRAY_SIZE(vpu_resources),
 801 };
 802
 803 /* VEU0 */
 804 static struct uio_info veu0_platform_data = {
 805         .name = "VEU0",
 806         .version = "0",
 807         .irq = intcs_evt2irq(0x700),
 808 };
 809
 810 static struct resource veu0_resources[] = {
 811         [0] = {
 812                 .name   = "VEU0",
 813                 .start  = 0xfe920000,
 814                 .end    = 0xfe9200cb,
 815                 .flags  = IORESOURCE_MEM,
 816         },
 817 };
 818
 819 static struct platform_device veu0_device = {
 820         .name           = "uio_pdrv_genirq",
 821         .id             = 1,
 822         .dev = {
 823                 .platform_data  = &veu0_platform_data,
 824         },
 825         .resource       = veu0_resources,
 826         .num_resources  = ARRAY_SIZE(veu0_resources),
 827 };
 828
 829 /* VEU1 */
 830 static struct uio_info veu1_platform_data = {
 831         .name = "VEU1",
 832         .version = "0",
 833         .irq = intcs_evt2irq(0x720),
 834 };
 835
 836 static struct resource veu1_resources[] = {
 837         [0] = {
 838                 .name   = "VEU1",
 839                 .start  = 0xfe924000,
 840                 .end    = 0xfe9240cb,
 841                 .flags  = IORESOURCE_MEM,
 842         },
 843 };
 844
 845 static struct platform_device veu1_device = {
 846         .name           = "uio_pdrv_genirq",
 847         .id             = 2,
 848         .dev = {
 849                 .platform_data  = &veu1_platform_data,
 850         },
 851         .resource       = veu1_resources,
 852         .num_resources  = ARRAY_SIZE(veu1_resources),
 853 };
 854
 855 /* VEU2 */
 856 static struct uio_info veu2_platform_data = {
 857         .name = "VEU2",
 858         .version = "0",
 859         .irq = intcs_evt2irq(0x740),
 860 };
 861
 862 static struct resource veu2_resources[] = {
 863         [0] = {
 864                 .name   = "VEU2",
 865                 .start  = 0xfe928000,
 866                 .end    = 0xfe928307,
 867                 .flags  = IORESOURCE_MEM,
 868         },
 869 };
 870
 871 static struct platform_device veu2_device = {
 872         .name           = "uio_pdrv_genirq",
 873         .id             = 3,
 874         .dev = {
 875                 .platform_data  = &veu2_platform_data,
 876         },
 877         .resource       = veu2_resources,
 878         .num_resources  = ARRAY_SIZE(veu2_resources),
 879 };
 880
 881 /* VEU3 */
 882 static struct uio_info veu3_platform_data = {
 883         .name = "VEU3",
 884         .version = "0",
 885         .irq = intcs_evt2irq(0x760),
 886 };
 887
 888 static struct resource veu3_resources[] = {
 889         [0] = {
 890                 .name   = "VEU3",
 891                 .start  = 0xfe92c000,
 892                 .end    = 0xfe92c307,
 893                 .flags  = IORESOURCE_MEM,
 894         },
 895 };
 896
 897 static struct platform_device veu3_device = {
 898         .name           = "uio_pdrv_genirq",
 899         .id             = 4,
 900         .dev = {
 901                 .platform_data  = &veu3_platform_data,
 902         },
 903         .resource       = veu3_resources,
 904         .num_resources  = ARRAY_SIZE(veu3_resources),
 905 };
 906
 907 /* JPU */
 908 static struct uio_info jpu_platform_data = {
 909         .name = "JPU",
 910         .version = "0",
 911         .irq = intcs_evt2irq(0x560),
 912 };
 913
 914 static struct resource jpu_resources[] = {
 915         [0] = {
 916                 .name   = "JPU",
 917                 .start  = 0xfe980000,
 918                 .end    = 0xfe9902d3,
 919                 .flags  = IORESOURCE_MEM,
 920         },
 921 };
 922
 923 static struct platform_device jpu_device = {
 924         .name           = "uio_pdrv_genirq",
 925         .id             = 5,
 926         .dev = {
 927                 .platform_data  = &jpu_platform_data,
 928         },
 929         .resource       = jpu_resources,
 930         .num_resources  = ARRAY_SIZE(jpu_resources),
 931 };
 932
 933 /* SPU2DSP0 */
 934 static struct uio_info spu0_platform_data = {
 935         .name = "SPU2DSP0",
 936         .version = "0",
 937         .irq = evt2irq(0x1800),
 938 };
 939
 940 static struct resource spu0_resources[] = {
 941         [0] = {
 942                 .name   = "SPU2DSP0",
 943                 .start  = 0xfe200000,
 944                 .end    = 0xfe2fffff,
 945                 .flags  = IORESOURCE_MEM,
 946         },
 947 };
 948
 949 static struct platform_device spu0_device = {
 950         .name           = "uio_pdrv_genirq",
 951         .id             = 6,
 952         .dev = {
 953                 .platform_data  = &spu0_platform_data,
 954         },
 955         .resource       = spu0_resources,
 956         .num_resources  = ARRAY_SIZE(spu0_resources),
 957 };
 958
 959 /* SPU2DSP1 */
 960 static struct uio_info spu1_platform_data = {
 961         .name = "SPU2DSP1",
 962         .version = "0",
 963         .irq = evt2irq(0x1820),
 964 };
 965
 966 static struct resource spu1_resources[] = {
 967         [0] = {
 968                 .name   = "SPU2DSP1",
 969                 .start  = 0xfe300000,
 970                 .end    = 0xfe3fffff,
 971                 .flags  = IORESOURCE_MEM,
 972         },
 973 };
 974
 975 static struct platform_device spu1_device = {
 976         .name           = "uio_pdrv_genirq",
 977         .id             = 7,
 978         .dev = {
 979                 .platform_data  = &spu1_platform_data,
 980         },
 981         .resource       = spu1_resources,
 982         .num_resources  = ARRAY_SIZE(spu1_resources),
 983 };
 984
 985 static struct platform_device *sh7372_early_devices[] __initdata = {
 986         &scif0_device,
 987         &scif1_device,
 988         &scif2_device,
 989         &scif3_device,
 990         &scif4_device,
 991         &scif5_device,
 992         &scif6_device,
 993         &cmt2_device,
 994         &tmu00_device,
 995         &tmu01_device,
 996 };
 997
 998 static struct platform_device *sh7372_late_devices[] __initdata = {
 999         &iic0_device,
1000         &iic1_device,
1001         &dma0_device,
1002         &dma1_device,
1003         &dma2_device,
1004         &usb_dma0_device,
1005         &usb_dma1_device,
1006         &vpu_device,
1007         &veu0_device,
1008         &veu1_device,
1009         &veu2_device,
1010         &veu3_device,
1011         &jpu_device,
1012         &spu0_device,
1013         &spu1_device,
1014 };
1015
1016 void __init sh7372_add_standard_devices(void)
1017 {
1018         struct pm_domain_device domain_devices[] = {
1019                 { "A3RV", &vpu_device, },
1020                 { "A4MP", &spu0_device, },
1021                 { "A4MP", &spu1_device, },
1022                 { "A3SP", &scif0_device, },
1023                 { "A3SP", &scif1_device, },
1024                 { "A3SP", &scif2_device, },
1025                 { "A3SP", &scif3_device, },
1026                 { "A3SP", &scif4_device, },
1027                 { "A3SP", &scif5_device, },
1028                 { "A3SP", &scif6_device, },
1029                 { "A3SP", &iic1_device, },
1030                 { "A3SP", &dma0_device, },
1031                 { "A3SP", &dma1_device, },
1032                 { "A3SP", &dma2_device, },
1033                 { "A3SP", &usb_dma0_device, },
1034                 { "A3SP", &usb_dma1_device, },
1035                 { "A4R", &iic0_device, },
1036                 { "A4R", &veu0_device, },
1037                 { "A4R", &veu1_device, },
1038                 { "A4R", &veu2_device, },
1039                 { "A4R", &veu3_device, },
1040                 { "A4R", &jpu_device, },
1041                 { "A4R", &tmu00_device, },
1042                 { "A4R", &tmu01_device, },
1043         };
1044
1045         sh7372_init_pm_domains();
1046
1047         platform_add_devices(sh7372_early_devices,
1048                             ARRAY_SIZE(sh7372_early_devices));
1049
1050         platform_add_devices(sh7372_late_devices,
1051                             ARRAY_SIZE(sh7372_late_devices));
1052
1053         rmobile_add_devices_to_domains(domain_devices,
1054                                        ARRAY_SIZE(domain_devices));
1055 }
1056
1057 void __init sh7372_earlytimer_init(void)
1058 {
1059         sh7372_clock_init();
1060         shmobile_earlytimer_init();
1061 }
1062
1063 void __init sh7372_add_early_devices(void)
1064 {
1065         early_platform_add_devices(sh7372_early_devices,
1066                                    ARRAY_SIZE(sh7372_early_devices));
1067
1068         /* setup early console here as well */
1069         shmobile_setup_console();
1070 }
1071
1072 #ifdef CONFIG_USE_OF
1073
1074 void __init sh7372_add_early_devices_dt(void)
1075 {
1076         shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
1077
1078         early_platform_add_devices(sh7372_early_devices,
1079                                    ARRAY_SIZE(sh7372_early_devices));
1080
1081         /* setup early console here as well */
1082         shmobile_setup_console();
1083 }
1084
1085 static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
1086         { }
1087 };
1088
1089 void __init sh7372_add_standard_devices_dt(void)
1090 {
1091         /* clocks are setup late during boot in the case of DT */
1092         sh7372_clock_init();
1093
1094         platform_add_devices(sh7372_early_devices,
1095                             ARRAY_SIZE(sh7372_early_devices));
1096
1097         of_platform_populate(NULL, of_default_bus_match_table,
1098                              sh7372_auxdata_lookup, NULL);
1099 }
1100
1101 static const char *sh7372_boards_compat_dt[] __initdata = {
1102         "renesas,sh7372",
1103         NULL,
1104 };
1105
1106 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1107         .map_io         = sh7372_map_io,
1108         .init_early     = sh7372_add_early_devices_dt,
1109         .nr_irqs        = NR_IRQS_LEGACY,
1110         .init_irq       = sh7372_init_irq,
1111         .handle_irq     = shmobile_handle_irq_intc,
1112         .init_machine   = sh7372_add_standard_devices_dt,
1113         .init_time      = shmobile_timer_init,
1114         .dt_compat      = sh7372_boards_compat_dt,
1115 MACHINE_END
1116
1117 #endif /* CONFIG_USE_OF */