08489efdaf0639670ecc9db5576e280ebb691b92
1 /* linux/arch/arm/mach-s3c2410/clock.c
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 Clock control support
8 * Based on, and code from linux/arch/arm/mach-versatile/clock.c
10 ** Copyright (C) 2004 ARM Limited.
11 ** Written by Deep Blue Solutions Limited.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
33 #include <linux/errno.h>
34 #include <linux/err.h>
35 #include <linux/platform_device.h>
36 #include <linux/sysdev.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/clk.h>
40 #include <linux/mutex.h>
42 #include <asm/hardware.h>
46 #include <asm/arch/regs-clock.h>
51 /* clock information */
53 static LIST_HEAD(clocks
);
54 static DEFINE_MUTEX(clocks_mutex
);
58 void inline s3c24xx_clk_enable(unsigned int clocks
, unsigned int enable
)
62 clkcon
= __raw_readl(S3C2410_CLKCON
);
69 /* ensure none of the special function bits set */
70 clkcon
&= ~(S3C2410_CLKCON_IDLE
|S3C2410_CLKCON_POWER
);
72 __raw_writel(clkcon
, S3C2410_CLKCON
);
75 /* enable and disable calls for use with the clk struct */
77 static int clk_null_enable(struct clk
*clk
, int enable
)
82 int s3c24xx_clkcon_enable(struct clk
*clk
, int enable
)
84 s3c24xx_clk_enable(clk
->ctrlbit
, enable
);
90 struct clk
*clk_get(struct device
*dev
, const char *id
)
93 struct clk
*clk
= ERR_PTR(-ENOENT
);
96 if (dev
== NULL
|| dev
->bus
!= &platform_bus_type
)
99 idno
= to_platform_device(dev
)->id
;
101 mutex_lock(&clocks_mutex
);
103 list_for_each_entry(p
, &clocks
, list
) {
105 strcmp(id
, p
->name
) == 0 &&
106 try_module_get(p
->owner
)) {
112 /* check for the case where a device was supplied, but the
113 * clock that was being searched for is not device specific */
116 list_for_each_entry(p
, &clocks
, list
) {
117 if (p
->id
== -1 && strcmp(id
, p
->name
) == 0 &&
118 try_module_get(p
->owner
)) {
125 mutex_unlock(&clocks_mutex
);
129 void clk_put(struct clk
*clk
)
131 module_put(clk
->owner
);
134 int clk_enable(struct clk
*clk
)
136 if (IS_ERR(clk
) || clk
== NULL
)
139 clk_enable(clk
->parent
);
141 mutex_lock(&clocks_mutex
);
143 if ((clk
->usage
++) == 0)
144 (clk
->enable
)(clk
, 1);
146 mutex_unlock(&clocks_mutex
);
150 void clk_disable(struct clk
*clk
)
152 if (IS_ERR(clk
) || clk
== NULL
)
155 mutex_lock(&clocks_mutex
);
157 if ((--clk
->usage
) == 0)
158 (clk
->enable
)(clk
, 0);
160 mutex_unlock(&clocks_mutex
);
161 clk_disable(clk
->parent
);
165 unsigned long clk_get_rate(struct clk
*clk
)
173 while (clk
->parent
!= NULL
&& clk
->rate
== 0)
179 long clk_round_rate(struct clk
*clk
, unsigned long rate
)
184 int clk_set_rate(struct clk
*clk
, unsigned long rate
)
189 struct clk
*clk_get_parent(struct clk
*clk
)
194 EXPORT_SYMBOL(clk_get
);
195 EXPORT_SYMBOL(clk_put
);
196 EXPORT_SYMBOL(clk_enable
);
197 EXPORT_SYMBOL(clk_disable
);
198 EXPORT_SYMBOL(clk_get_rate
);
199 EXPORT_SYMBOL(clk_round_rate
);
200 EXPORT_SYMBOL(clk_set_rate
);
201 EXPORT_SYMBOL(clk_get_parent
);
205 static struct clk clk_xtal
= {
213 static struct clk clk_f
= {
221 static struct clk clk_h
= {
229 static struct clk clk_p
= {
237 /* clocks that could be registered by external code */
239 struct clk s3c24xx_dclk0
= {
244 struct clk s3c24xx_dclk1
= {
249 struct clk s3c24xx_clkout0
= {
254 struct clk s3c24xx_clkout1
= {
259 struct clk s3c24xx_uclk
= {
265 /* clock definitions */
267 static struct clk init_clocks
[] = {
272 .enable
= s3c24xx_clkcon_enable
,
273 .ctrlbit
= S3C2410_CLKCON_NAND
,
278 .enable
= s3c24xx_clkcon_enable
,
279 .ctrlbit
= S3C2410_CLKCON_LCDC
,
284 .enable
= s3c24xx_clkcon_enable
,
285 .ctrlbit
= S3C2410_CLKCON_USBH
,
287 .name
= "usb-device",
290 .enable
= s3c24xx_clkcon_enable
,
291 .ctrlbit
= S3C2410_CLKCON_USBD
,
296 .enable
= s3c24xx_clkcon_enable
,
297 .ctrlbit
= S3C2410_CLKCON_PWMT
,
302 .enable
= s3c24xx_clkcon_enable
,
303 .ctrlbit
= S3C2410_CLKCON_SDI
,
308 .enable
= s3c24xx_clkcon_enable
,
309 .ctrlbit
= S3C2410_CLKCON_UART0
,
314 .enable
= s3c24xx_clkcon_enable
,
315 .ctrlbit
= S3C2410_CLKCON_UART1
,
320 .enable
= s3c24xx_clkcon_enable
,
321 .ctrlbit
= S3C2410_CLKCON_UART2
,
326 .enable
= s3c24xx_clkcon_enable
,
327 .ctrlbit
= S3C2410_CLKCON_GPIO
,
332 .enable
= s3c24xx_clkcon_enable
,
333 .ctrlbit
= S3C2410_CLKCON_RTC
,
338 .enable
= s3c24xx_clkcon_enable
,
339 .ctrlbit
= S3C2410_CLKCON_ADC
,
344 .enable
= s3c24xx_clkcon_enable
,
345 .ctrlbit
= S3C2410_CLKCON_IIC
,
350 .enable
= s3c24xx_clkcon_enable
,
351 .ctrlbit
= S3C2410_CLKCON_IIS
,
356 .enable
= s3c24xx_clkcon_enable
,
357 .ctrlbit
= S3C2410_CLKCON_SPI
,
366 /* initialise the clock system */
368 int s3c24xx_register_clock(struct clk
*clk
)
370 clk
->owner
= THIS_MODULE
;
372 if (clk
->enable
== NULL
)
373 clk
->enable
= clk_null_enable
;
375 /* if this is a standard clock, set the usage state */
378 unsigned long clkcon
= __raw_readl(S3C2410_CLKCON
);
380 clk
->usage
= (clkcon
& clk
->ctrlbit
) ? 1 : 0;
383 /* add to the list of available clocks */
385 mutex_lock(&clocks_mutex
);
386 list_add(&clk
->list
, &clocks
);
387 mutex_unlock(&clocks_mutex
);
392 /* initalise all the clocks */
394 int __init
s3c24xx_setup_clocks(unsigned long xtal
,
399 unsigned long clkslow
= __raw_readl(S3C2410_CLKSLOW
);
400 struct clk
*clkp
= init_clocks
;
404 printk(KERN_INFO
"S3C2410 Clocks, (c) 2004 Simtec Electronics\n");
406 /* initialise the main system clocks */
408 clk_xtal
.rate
= xtal
;
414 /* We must be careful disabling the clocks we are not intending to
415 * be using at boot time, as subsytems such as the LCD which do
416 * their own DMA requests to the bus can cause the system to lockup
417 * if they where in the middle of requesting bus access.
419 * Disabling the LCD clock if the LCD is active is very dangerous,
420 * and therefore the bootloader should be careful to not enable
421 * the LCD clock if it is not needed.
424 mutex_lock(&clocks_mutex
);
426 s3c24xx_clk_enable(S3C2410_CLKCON_NAND
, 0);
427 s3c24xx_clk_enable(S3C2410_CLKCON_USBH
, 0);
428 s3c24xx_clk_enable(S3C2410_CLKCON_USBD
, 0);
429 s3c24xx_clk_enable(S3C2410_CLKCON_ADC
, 0);
430 s3c24xx_clk_enable(S3C2410_CLKCON_IIC
, 0);
431 s3c24xx_clk_enable(S3C2410_CLKCON_SPI
, 0);
433 mutex_unlock(&clocks_mutex
);
435 /* assume uart clocks are correctly setup */
437 /* register our clocks */
439 if (s3c24xx_register_clock(&clk_xtal
) < 0)
440 printk(KERN_ERR
"failed to register master xtal\n");
442 if (s3c24xx_register_clock(&clk_f
) < 0)
443 printk(KERN_ERR
"failed to register cpu fclk\n");
445 if (s3c24xx_register_clock(&clk_h
) < 0)
446 printk(KERN_ERR
"failed to register cpu hclk\n");
448 if (s3c24xx_register_clock(&clk_p
) < 0)
449 printk(KERN_ERR
"failed to register cpu pclk\n");
451 /* register clocks from clock array */
453 for (ptr
= 0; ptr
< ARRAY_SIZE(init_clocks
); ptr
++, clkp
++) {
454 ret
= s3c24xx_register_clock(clkp
);
456 printk(KERN_ERR
"Failed to register clock %s (%d)\n",
461 /* show the clock-slow value */
463 printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
464 print_mhz(xtal
/ ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow
))),
465 (clkslow
& S3C2410_CLKSLOW_SLOW
) ? "slow" : "fast",
466 (clkslow
& S3C2410_CLKSLOW_MPLL_OFF
) ? "off" : "on",
467 (clkslow
& S3C2410_CLKSLOW_UCLK_OFF
) ? "off" : "on");