arch/arm/mach-realview/core.c

   1 /*
   2  *  linux/arch/arm/mach-realview/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/sysdev.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/amba/clcd.h>
  28 #include <linux/clocksource.h>
  29 #include <linux/clockchips.h>
  30 #include <linux/io.h>
  31
  32 #include <asm/clkdev.h>
  33 #include <asm/system.h>
  34 #include <mach/hardware.h>
  35 #include <asm/irq.h>
  36 #include <asm/leds.h>
  37 #include <asm/hardware/arm_timer.h>
  38 #include <asm/hardware/icst307.h>
  39
  40 #include <asm/mach/arch.h>
  41 #include <asm/mach/flash.h>
  42 #include <asm/mach/irq.h>
  43 #include <asm/mach/map.h>
  44 #include <asm/mach/mmc.h>
  45
  46 #include <asm/hardware/gic.h>
  47
  48 #include "core.h"
  49 #include "clock.h"
  50
  51 #define REALVIEW_REFCOUNTER     (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
  52
  53 /* used by entry-macro.S */
  54 void __iomem *gic_cpu_base_addr;
  55
  56 /*
  57  * This is the RealView sched_clock implementation.  This has
  58  * a resolution of 41.7ns, and a maximum value of about 179s.
  59  */
  60 unsigned long long sched_clock(void)
  61 {
  62         unsigned long long v;
  63
  64         v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
  65         do_div(v, 3);
  66
  67         return v;
  68 }
  69
  70
  71 #define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
  72
  73 static int realview_flash_init(void)
  74 {
  75         u32 val;
  76
  77         val = __raw_readl(REALVIEW_FLASHCTRL);
  78         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  79         __raw_writel(val, REALVIEW_FLASHCTRL);
  80
  81         return 0;
  82 }
  83
  84 static void realview_flash_exit(void)
  85 {
  86         u32 val;
  87
  88         val = __raw_readl(REALVIEW_FLASHCTRL);
  89         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  90         __raw_writel(val, REALVIEW_FLASHCTRL);
  91 }
  92
  93 static void realview_flash_set_vpp(int on)
  94 {
  95         u32 val;
  96
  97         val = __raw_readl(REALVIEW_FLASHCTRL);
  98         if (on)
  99                 val |= REALVIEW_FLASHPROG_FLVPPEN;
 100         else
 101                 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
 102         __raw_writel(val, REALVIEW_FLASHCTRL);
 103 }
 104
 105 static struct flash_platform_data realview_flash_data = {
 106         .map_name               = "cfi_probe",
 107         .width                  = 4,
 108         .init                   = realview_flash_init,
 109         .exit                   = realview_flash_exit,
 110         .set_vpp                = realview_flash_set_vpp,
 111 };
 112
 113 struct platform_device realview_flash_device = {
 114         .name                   = "armflash",
 115         .id                     = 0,
 116         .dev                    = {
 117                 .platform_data  = &realview_flash_data,
 118         },
 119 };
 120
 121 int realview_flash_register(struct resource *res, u32 num)
 122 {
 123         realview_flash_device.resource = res;
 124         realview_flash_device.num_resources = num;
 125         return platform_device_register(&realview_flash_device);
 126 }
 127
 128 static struct resource realview_i2c_resource = {
 129         .start          = REALVIEW_I2C_BASE,
 130         .end            = REALVIEW_I2C_BASE + SZ_4K - 1,
 131         .flags          = IORESOURCE_MEM,
 132 };
 133
 134 struct platform_device realview_i2c_device = {
 135         .name           = "versatile-i2c",
 136         .id             = -1,
 137         .num_resources  = 1,
 138         .resource       = &realview_i2c_resource,
 139 };
 140
 141 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
 142
 143 static unsigned int realview_mmc_status(struct device *dev)
 144 {
 145         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 146         u32 mask;
 147
 148         if (adev->res.start == REALVIEW_MMCI0_BASE)
 149                 mask = 1;
 150         else
 151                 mask = 2;
 152
 153         return readl(REALVIEW_SYSMCI) & mask;
 154 }
 155
 156 struct mmc_platform_data realview_mmc0_plat_data = {
 157         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 158         .status         = realview_mmc_status,
 159 };
 160
 161 struct mmc_platform_data realview_mmc1_plat_data = {
 162         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 163         .status         = realview_mmc_status,
 164 };
 165
 166 /*
 167  * Clock handling
 168  */
 169 static const struct icst307_params realview_oscvco_params = {
 170         .ref            = 24000,
 171         .vco_max        = 200000,
 172         .vd_min         = 4 + 8,
 173         .vd_max         = 511 + 8,
 174         .rd_min         = 1 + 2,
 175         .rd_max         = 127 + 2,
 176 };
 177
 178 static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
 179 {
 180         void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
 181         void __iomem *sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
 182         u32 val;
 183
 184         val = readl(sys_osc) & ~0x7ffff;
 185         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 186
 187         writel(0xa05f, sys_lock);
 188         writel(val, sys_osc);
 189         writel(0, sys_lock);
 190 }
 191
 192 static struct clk oscvco_clk = {
 193         .params = &realview_oscvco_params,
 194         .setvco = realview_oscvco_set,
 195 };
 196
 197 /*
 198  * These are fixed clocks.
 199  */
 200 static struct clk ref24_clk = {
 201         .rate   = 24000000,
 202 };
 203
 204 static struct clk_lookup lookups[] = {
 205         {       /* UART0 */
 206                 .dev_id         = "dev:f1",
 207                 .clk            = &ref24_clk,
 208         }, {    /* UART1 */
 209                 .dev_id         = "dev:f2",
 210                 .clk            = &ref24_clk,
 211         }, {    /* UART2 */
 212                 .dev_id         = "dev:f3",
 213                 .clk            = &ref24_clk,
 214         }, {    /* UART3 */
 215                 .dev_id         = "fpga:09",
 216                 .clk            = &ref24_clk,
 217         }, {    /* KMI0 */
 218                 .dev_id         = "fpga:06",
 219                 .clk            = &ref24_clk,
 220         }, {    /* KMI1 */
 221                 .dev_id         = "fpga:07",
 222                 .clk            = &ref24_clk,
 223         }, {    /* MMC0 */
 224                 .dev_id         = "fpga:05",
 225                 .clk            = &ref24_clk,
 226         }, {    /* EB:CLCD */
 227                 .dev_id         = "dev:20",
 228                 .clk            = &oscvco_clk,
 229         }, {    /* PB:CLCD */
 230                 .dev_id         = "issp:20",
 231                 .clk            = &oscvco_clk,
 232         }
 233 };
 234
 235 static int __init clk_init(void)
 236 {
 237         int i;
 238
 239         for (i = 0; i < ARRAY_SIZE(lookups); i++)
 240                 clkdev_add(&lookups[i]);
 241         return 0;
 242 }
 243 arch_initcall(clk_init);
 244
 245 /*
 246  * CLCD support.
 247  */
 248 #define SYS_CLCD_NLCDIOON       (1 << 2)
 249 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 250 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 251 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 252 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 253 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 254 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 255 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 256 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 257
 258 static struct clcd_panel vga = {
 259         .mode           = {
 260                 .name           = "VGA",
 261                 .refresh        = 60,
 262                 .xres           = 640,
 263                 .yres           = 480,
 264                 .pixclock       = 39721,
 265                 .left_margin    = 40,
 266                 .right_margin   = 24,
 267                 .upper_margin   = 32,
 268                 .lower_margin   = 11,
 269                 .hsync_len      = 96,
 270                 .vsync_len      = 2,
 271                 .sync           = 0,
 272                 .vmode          = FB_VMODE_NONINTERLACED,
 273         },
 274         .width          = -1,
 275         .height         = -1,
 276         .tim2           = TIM2_BCD | TIM2_IPC,
 277         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 278         .bpp            = 16,
 279 };
 280
 281 static struct clcd_panel sanyo_3_8_in = {
 282         .mode           = {
 283                 .name           = "Sanyo QVGA",
 284                 .refresh        = 116,
 285                 .xres           = 320,
 286                 .yres           = 240,
 287                 .pixclock       = 100000,
 288                 .left_margin    = 6,
 289                 .right_margin   = 6,
 290                 .upper_margin   = 5,
 291                 .lower_margin   = 5,
 292                 .hsync_len      = 6,
 293                 .vsync_len      = 6,
 294                 .sync           = 0,
 295                 .vmode          = FB_VMODE_NONINTERLACED,
 296         },
 297         .width          = -1,
 298         .height         = -1,
 299         .tim2           = TIM2_BCD,
 300         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 301         .bpp            = 16,
 302 };
 303
 304 static struct clcd_panel sanyo_2_5_in = {
 305         .mode           = {
 306                 .name           = "Sanyo QVGA Portrait",
 307                 .refresh        = 116,
 308                 .xres           = 240,
 309                 .yres           = 320,
 310                 .pixclock       = 100000,
 311                 .left_margin    = 20,
 312                 .right_margin   = 10,
 313                 .upper_margin   = 2,
 314                 .lower_margin   = 2,
 315                 .hsync_len      = 10,
 316                 .vsync_len      = 2,
 317                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 318                 .vmode          = FB_VMODE_NONINTERLACED,
 319         },
 320         .width          = -1,
 321         .height         = -1,
 322         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 323         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 324         .bpp            = 16,
 325 };
 326
 327 static struct clcd_panel epson_2_2_in = {
 328         .mode           = {
 329                 .name           = "Epson QCIF",
 330                 .refresh        = 390,
 331                 .xres           = 176,
 332                 .yres           = 220,
 333                 .pixclock       = 62500,
 334                 .left_margin    = 3,
 335                 .right_margin   = 2,
 336                 .upper_margin   = 1,
 337                 .lower_margin   = 0,
 338                 .hsync_len      = 3,
 339                 .vsync_len      = 2,
 340                 .sync           = 0,
 341                 .vmode          = FB_VMODE_NONINTERLACED,
 342         },
 343         .width          = -1,
 344         .height         = -1,
 345         .tim2           = TIM2_BCD | TIM2_IPC,
 346         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 347         .bpp            = 16,
 348 };
 349
 350 /*
 351  * Detect which LCD panel is connected, and return the appropriate
 352  * clcd_panel structure.  Note: we do not have any information on
 353  * the required timings for the 8.4in panel, so we presently assume
 354  * VGA timings.
 355  */
 356 static struct clcd_panel *realview_clcd_panel(void)
 357 {
 358         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 359         struct clcd_panel *panel = &vga;
 360         u32 val;
 361
 362         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 363         if (val == SYS_CLCD_ID_SANYO_3_8)
 364                 panel = &sanyo_3_8_in;
 365         else if (val == SYS_CLCD_ID_SANYO_2_5)
 366                 panel = &sanyo_2_5_in;
 367         else if (val == SYS_CLCD_ID_EPSON_2_2)
 368                 panel = &epson_2_2_in;
 369         else if (val == SYS_CLCD_ID_VGA)
 370                 panel = &vga;
 371         else {
 372                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 373                         val);
 374                 panel = &vga;
 375         }
 376
 377         return panel;
 378 }
 379
 380 /*
 381  * Disable all display connectors on the interface module.
 382  */
 383 static void realview_clcd_disable(struct clcd_fb *fb)
 384 {
 385         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 386         u32 val;
 387
 388         val = readl(sys_clcd);
 389         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 390         writel(val, sys_clcd);
 391 }
 392
 393 /*
 394  * Enable the relevant connector on the interface module.
 395  */
 396 static void realview_clcd_enable(struct clcd_fb *fb)
 397 {
 398         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 399         u32 val;
 400
 401         /*
 402          * Enable the PSUs
 403          */
 404         val = readl(sys_clcd);
 405         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 406         writel(val, sys_clcd);
 407 }
 408
 409 static unsigned long framesize = SZ_1M;
 410
 411 static int realview_clcd_setup(struct clcd_fb *fb)
 412 {
 413         dma_addr_t dma;
 414
 415         fb->panel               = realview_clcd_panel();
 416
 417         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 418                                                     &dma, GFP_KERNEL);
 419         if (!fb->fb.screen_base) {
 420                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 421                 return -ENOMEM;
 422         }
 423
 424         fb->fb.fix.smem_start   = dma;
 425         fb->fb.fix.smem_len     = framesize;
 426
 427         return 0;
 428 }
 429
 430 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 431 {
 432         return dma_mmap_writecombine(&fb->dev->dev, vma,
 433                                      fb->fb.screen_base,
 434                                      fb->fb.fix.smem_start,
 435                                      fb->fb.fix.smem_len);
 436 }
 437
 438 static void realview_clcd_remove(struct clcd_fb *fb)
 439 {
 440         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 441                               fb->fb.screen_base, fb->fb.fix.smem_start);
 442 }
 443
 444 struct clcd_board clcd_plat_data = {
 445         .name           = "RealView",
 446         .check          = clcdfb_check,
 447         .decode         = clcdfb_decode,
 448         .disable        = realview_clcd_disable,
 449         .enable         = realview_clcd_enable,
 450         .setup          = realview_clcd_setup,
 451         .mmap           = realview_clcd_mmap,
 452         .remove         = realview_clcd_remove,
 453 };
 454
 455 #ifdef CONFIG_LEDS
 456 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
 457
 458 void realview_leds_event(led_event_t ledevt)
 459 {
 460         unsigned long flags;
 461         u32 val;
 462
 463         local_irq_save(flags);
 464         val = readl(VA_LEDS_BASE);
 465
 466         switch (ledevt) {
 467         case led_idle_start:
 468                 val = val & ~REALVIEW_SYS_LED0;
 469                 break;
 470
 471         case led_idle_end:
 472                 val = val | REALVIEW_SYS_LED0;
 473                 break;
 474
 475         case led_timer:
 476                 val = val ^ REALVIEW_SYS_LED1;
 477                 break;
 478
 479         case led_halted:
 480                 val = 0;
 481                 break;
 482
 483         default:
 484                 break;
 485         }
 486
 487         writel(val, VA_LEDS_BASE);
 488         local_irq_restore(flags);
 489 }
 490 #endif  /* CONFIG_LEDS */
 491
 492 /*
 493  * Where is the timer (VA)?
 494  */
 495 void __iomem *timer0_va_base;
 496 void __iomem *timer1_va_base;
 497 void __iomem *timer2_va_base;
 498 void __iomem *timer3_va_base;
 499
 500 /*
 501  * How long is the timer interval?
 502  */
 503 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 504 #if TIMER_INTERVAL >= 0x100000
 505 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
 506 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
 507 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 508 #elif TIMER_INTERVAL >= 0x10000
 509 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
 510 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
 511 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 512 #else
 513 #define TIMER_RELOAD    (TIMER_INTERVAL)
 514 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
 515 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 516 #endif
 517
 518 static void timer_set_mode(enum clock_event_mode mode,
 519                            struct clock_event_device *clk)
 520 {
 521         unsigned long ctrl;
 522
 523         switch(mode) {
 524         case CLOCK_EVT_MODE_PERIODIC:
 525                 writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
 526
 527                 ctrl = TIMER_CTRL_PERIODIC;
 528                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
 529                 break;
 530         case CLOCK_EVT_MODE_ONESHOT:
 531                 /* period set, and timer enabled in 'next_event' hook */
 532                 ctrl = TIMER_CTRL_ONESHOT;
 533                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
 534                 break;
 535         case CLOCK_EVT_MODE_UNUSED:
 536         case CLOCK_EVT_MODE_SHUTDOWN:
 537         default:
 538                 ctrl = 0;
 539         }
 540
 541         writel(ctrl, timer0_va_base + TIMER_CTRL);
 542 }
 543
 544 static int timer_set_next_event(unsigned long evt,
 545                                 struct clock_event_device *unused)
 546 {
 547         unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
 548
 549         writel(evt, timer0_va_base + TIMER_LOAD);
 550         writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
 551
 552         return 0;
 553 }
 554
 555 static struct clock_event_device timer0_clockevent =     {
 556         .name           = "timer0",
 557         .shift          = 32,
 558         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 559         .set_mode       = timer_set_mode,
 560         .set_next_event = timer_set_next_event,
 561         .rating         = 300,
 562         .cpumask        = CPU_MASK_ALL,
 563 };
 564
 565 static void __init realview_clockevents_init(unsigned int timer_irq)
 566 {
 567         timer0_clockevent.irq = timer_irq;
 568         timer0_clockevent.mult =
 569                 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
 570         timer0_clockevent.max_delta_ns =
 571                 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
 572         timer0_clockevent.min_delta_ns =
 573                 clockevent_delta2ns(0xf, &timer0_clockevent);
 574
 575         clockevents_register_device(&timer0_clockevent);
 576 }
 577
 578 /*
 579  * IRQ handler for the timer
 580  */
 581 static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
 582 {
 583         struct clock_event_device *evt = &timer0_clockevent;
 584
 585         /* clear the interrupt */
 586         writel(1, timer0_va_base + TIMER_INTCLR);
 587
 588         evt->event_handler(evt);
 589
 590         return IRQ_HANDLED;
 591 }
 592
 593 static struct irqaction realview_timer_irq = {
 594         .name           = "RealView Timer Tick",
 595         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 596         .handler        = realview_timer_interrupt,
 597 };
 598
 599 static cycle_t realview_get_cycles(void)
 600 {
 601         return ~readl(timer3_va_base + TIMER_VALUE);
 602 }
 603
 604 static struct clocksource clocksource_realview = {
 605         .name   = "timer3",
 606         .rating = 200,
 607         .read   = realview_get_cycles,
 608         .mask   = CLOCKSOURCE_MASK(32),
 609         .shift  = 20,
 610         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 611 };
 612
 613 static void __init realview_clocksource_init(void)
 614 {
 615         /* setup timer 0 as free-running clocksource */
 616         writel(0, timer3_va_base + TIMER_CTRL);
 617         writel(0xffffffff, timer3_va_base + TIMER_LOAD);
 618         writel(0xffffffff, timer3_va_base + TIMER_VALUE);
 619         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
 620                 timer3_va_base + TIMER_CTRL);
 621
 622         clocksource_realview.mult =
 623                 clocksource_khz2mult(1000, clocksource_realview.shift);
 624         clocksource_register(&clocksource_realview);
 625 }
 626
 627 /*
 628  * Set up the clock source and clock events devices
 629  */
 630 void __init realview_timer_init(unsigned int timer_irq)
 631 {
 632         u32 val;
 633
 634 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
 635         /*
 636          * The dummy clock device has to be registered before the main device
 637          * so that the latter will broadcast the clock events
 638          */
 639         local_timer_setup(smp_processor_id());
 640 #endif
 641
 642         /*
 643          * set clock frequency:
 644          *      REALVIEW_REFCLK is 32KHz
 645          *      REALVIEW_TIMCLK is 1MHz
 646          */
 647         val = readl(__io_address(REALVIEW_SCTL_BASE));
 648         writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
 649                (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
 650                (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
 651                (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
 652                __io_address(REALVIEW_SCTL_BASE));
 653
 654         /*
 655          * Initialise to a known state (all timers off)
 656          */
 657         writel(0, timer0_va_base + TIMER_CTRL);
 658         writel(0, timer1_va_base + TIMER_CTRL);
 659         writel(0, timer2_va_base + TIMER_CTRL);
 660         writel(0, timer3_va_base + TIMER_CTRL);
 661
 662         /*
 663          * Make irqs happen for the system timer
 664          */
 665         setup_irq(timer_irq, &realview_timer_irq);
 666
 667         realview_clocksource_init();
 668         realview_clockevents_init(timer_irq);
 669 }