2 * linux/arch/arm/mach-realview/core.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/amba/bus.h>
27 #include <linux/amba/clcd.h>
28 #include <linux/clocksource.h>
29 #include <linux/clockchips.h>
32 #include <asm/system.h>
33 #include <mach/hardware.h>
36 #include <asm/mach-types.h>
37 #include <asm/hardware/arm_timer.h>
38 #include <asm/hardware/icst307.h>
40 #include <asm/mach/arch.h>
41 #include <asm/mach/flash.h>
42 #include <asm/mach/irq.h>
43 #include <asm/mach/map.h>
44 #include <asm/mach/mmc.h>
46 #include <asm/hardware/gic.h>
51 #define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
53 /* used by entry-macro.S and platsmp.c */
54 void __iomem
*gic_cpu_base_addr
;
57 * This is the RealView sched_clock implementation. This has
58 * a resolution of 41.7ns, and a maximum value of about 179s.
60 unsigned long long sched_clock(void)
64 v
= (unsigned long long)readl(REALVIEW_REFCOUNTER
) * 125;
71 #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
73 static int realview_flash_init(void)
77 val
= __raw_readl(REALVIEW_FLASHCTRL
);
78 val
&= ~REALVIEW_FLASHPROG_FLVPPEN
;
79 __raw_writel(val
, REALVIEW_FLASHCTRL
);
84 static void realview_flash_exit(void)
88 val
= __raw_readl(REALVIEW_FLASHCTRL
);
89 val
&= ~REALVIEW_FLASHPROG_FLVPPEN
;
90 __raw_writel(val
, REALVIEW_FLASHCTRL
);
93 static void realview_flash_set_vpp(int on
)
97 val
= __raw_readl(REALVIEW_FLASHCTRL
);
99 val
|= REALVIEW_FLASHPROG_FLVPPEN
;
101 val
&= ~REALVIEW_FLASHPROG_FLVPPEN
;
102 __raw_writel(val
, REALVIEW_FLASHCTRL
);
105 static struct flash_platform_data realview_flash_data
= {
106 .map_name
= "cfi_probe",
108 .init
= realview_flash_init
,
109 .exit
= realview_flash_exit
,
110 .set_vpp
= realview_flash_set_vpp
,
113 struct platform_device realview_flash_device
= {
117 .platform_data
= &realview_flash_data
,
121 int realview_flash_register(struct resource
*res
, u32 num
)
123 realview_flash_device
.resource
= res
;
124 realview_flash_device
.num_resources
= num
;
125 return platform_device_register(&realview_flash_device
);
128 static struct resource realview_i2c_resource
= {
129 .start
= REALVIEW_I2C_BASE
,
130 .end
= REALVIEW_I2C_BASE
+ SZ_4K
- 1,
131 .flags
= IORESOURCE_MEM
,
134 struct platform_device realview_i2c_device
= {
135 .name
= "versatile-i2c",
138 .resource
= &realview_i2c_resource
,
141 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
143 static unsigned int realview_mmc_status(struct device
*dev
)
145 struct amba_device
*adev
= container_of(dev
, struct amba_device
, dev
);
148 if (adev
->res
.start
== REALVIEW_MMCI0_BASE
)
153 return readl(REALVIEW_SYSMCI
) & mask
;
156 struct mmc_platform_data realview_mmc0_plat_data
= {
157 .ocr_mask
= MMC_VDD_32_33
|MMC_VDD_33_34
,
158 .status
= realview_mmc_status
,
161 struct mmc_platform_data realview_mmc1_plat_data
= {
162 .ocr_mask
= MMC_VDD_32_33
|MMC_VDD_33_34
,
163 .status
= realview_mmc_status
,
169 static const struct icst307_params realview_oscvco_params
= {
178 static void realview_oscvco_set(struct clk
*clk
, struct icst307_vco vco
)
180 void __iomem
*sys_lock
= __io_address(REALVIEW_SYS_BASE
) + REALVIEW_SYS_LOCK_OFFSET
;
181 void __iomem
*sys_osc
;
184 if (machine_is_realview_pb1176())
185 sys_osc
= __io_address(REALVIEW_SYS_BASE
) + REALVIEW_SYS_OSC0_OFFSET
;
187 sys_osc
= __io_address(REALVIEW_SYS_BASE
) + REALVIEW_SYS_OSC4_OFFSET
;
189 val
= readl(sys_osc
) & ~0x7ffff;
190 val
|= vco
.v
| (vco
.r
<< 9) | (vco
.s
<< 16);
192 writel(0xa05f, sys_lock
);
193 writel(val
, sys_osc
);
197 struct clk realview_clcd_clk
= {
199 .params
= &realview_oscvco_params
,
200 .setvco
= realview_oscvco_set
,
206 #define SYS_CLCD_NLCDIOON (1 << 2)
207 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
208 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
209 #define SYS_CLCD_ID_MASK (0x1f << 8)
210 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
211 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
212 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
213 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
214 #define SYS_CLCD_ID_VGA (0x1f << 8)
216 static struct clcd_panel vga
= {
230 .vmode
= FB_VMODE_NONINTERLACED
,
234 .tim2
= TIM2_BCD
| TIM2_IPC
,
235 .cntl
= CNTL_LCDTFT
| CNTL_BGR
| CNTL_LCDVCOMP(1),
239 static struct clcd_panel xvga
= {
253 .vmode
= FB_VMODE_NONINTERLACED
,
257 .tim2
= TIM2_BCD
| TIM2_IPC
,
258 .cntl
= CNTL_LCDTFT
| CNTL_BGR
| CNTL_LCDVCOMP(1),
262 static struct clcd_panel sanyo_3_8_in
= {
264 .name
= "Sanyo QVGA",
276 .vmode
= FB_VMODE_NONINTERLACED
,
281 .cntl
= CNTL_LCDTFT
| CNTL_BGR
| CNTL_LCDVCOMP(1),
285 static struct clcd_panel sanyo_2_5_in
= {
287 .name
= "Sanyo QVGA Portrait",
298 .sync
= FB_SYNC_HOR_HIGH_ACT
| FB_SYNC_VERT_HIGH_ACT
,
299 .vmode
= FB_VMODE_NONINTERLACED
,
303 .tim2
= TIM2_IVS
| TIM2_IHS
| TIM2_IPC
,
304 .cntl
= CNTL_LCDTFT
| CNTL_BGR
| CNTL_LCDVCOMP(1),
308 static struct clcd_panel epson_2_2_in
= {
310 .name
= "Epson QCIF",
322 .vmode
= FB_VMODE_NONINTERLACED
,
326 .tim2
= TIM2_BCD
| TIM2_IPC
,
327 .cntl
= CNTL_LCDTFT
| CNTL_BGR
| CNTL_LCDVCOMP(1),
332 * Detect which LCD panel is connected, and return the appropriate
333 * clcd_panel structure. Note: we do not have any information on
334 * the required timings for the 8.4in panel, so we presently assume
337 static struct clcd_panel
*realview_clcd_panel(void)
339 void __iomem
*sys_clcd
= __io_address(REALVIEW_SYS_BASE
) + REALVIEW_SYS_CLCD_OFFSET
;
340 struct clcd_panel
*vga_panel
;
341 struct clcd_panel
*panel
;
344 if (machine_is_realview_eb())
349 val
= readl(sys_clcd
) & SYS_CLCD_ID_MASK
;
350 if (val
== SYS_CLCD_ID_SANYO_3_8
)
351 panel
= &sanyo_3_8_in
;
352 else if (val
== SYS_CLCD_ID_SANYO_2_5
)
353 panel
= &sanyo_2_5_in
;
354 else if (val
== SYS_CLCD_ID_EPSON_2_2
)
355 panel
= &epson_2_2_in
;
356 else if (val
== SYS_CLCD_ID_VGA
)
359 printk(KERN_ERR
"CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
368 * Disable all display connectors on the interface module.
370 static void realview_clcd_disable(struct clcd_fb
*fb
)
372 void __iomem
*sys_clcd
= __io_address(REALVIEW_SYS_BASE
) + REALVIEW_SYS_CLCD_OFFSET
;
375 val
= readl(sys_clcd
);
376 val
&= ~SYS_CLCD_NLCDIOON
| SYS_CLCD_PWR3V5SWITCH
;
377 writel(val
, sys_clcd
);
381 * Enable the relevant connector on the interface module.
383 static void realview_clcd_enable(struct clcd_fb
*fb
)
385 void __iomem
*sys_clcd
= __io_address(REALVIEW_SYS_BASE
) + REALVIEW_SYS_CLCD_OFFSET
;
391 val
= readl(sys_clcd
);
392 val
|= SYS_CLCD_NLCDIOON
| SYS_CLCD_PWR3V5SWITCH
;
393 writel(val
, sys_clcd
);
396 static int realview_clcd_setup(struct clcd_fb
*fb
)
398 unsigned long framesize
;
401 if (machine_is_realview_eb())
403 framesize
= 640 * 480 * 2;
406 framesize
= 1024 * 768 * 2;
408 fb
->panel
= realview_clcd_panel();
410 fb
->fb
.screen_base
= dma_alloc_writecombine(&fb
->dev
->dev
, framesize
,
412 if (!fb
->fb
.screen_base
) {
413 printk(KERN_ERR
"CLCD: unable to map framebuffer\n");
417 fb
->fb
.fix
.smem_start
= dma
;
418 fb
->fb
.fix
.smem_len
= framesize
;
423 static int realview_clcd_mmap(struct clcd_fb
*fb
, struct vm_area_struct
*vma
)
425 return dma_mmap_writecombine(&fb
->dev
->dev
, vma
,
427 fb
->fb
.fix
.smem_start
,
428 fb
->fb
.fix
.smem_len
);
431 static void realview_clcd_remove(struct clcd_fb
*fb
)
433 dma_free_writecombine(&fb
->dev
->dev
, fb
->fb
.fix
.smem_len
,
434 fb
->fb
.screen_base
, fb
->fb
.fix
.smem_start
);
437 struct clcd_board clcd_plat_data
= {
439 .check
= clcdfb_check
,
440 .decode
= clcdfb_decode
,
441 .disable
= realview_clcd_disable
,
442 .enable
= realview_clcd_enable
,
443 .setup
= realview_clcd_setup
,
444 .mmap
= realview_clcd_mmap
,
445 .remove
= realview_clcd_remove
,
449 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
451 void realview_leds_event(led_event_t ledevt
)
456 local_irq_save(flags
);
457 val
= readl(VA_LEDS_BASE
);
461 val
= val
& ~REALVIEW_SYS_LED0
;
465 val
= val
| REALVIEW_SYS_LED0
;
469 val
= val
^ REALVIEW_SYS_LED1
;
480 writel(val
, VA_LEDS_BASE
);
481 local_irq_restore(flags
);
483 #endif /* CONFIG_LEDS */
486 * Where is the timer (VA)?
488 void __iomem
*timer0_va_base
;
489 void __iomem
*timer1_va_base
;
490 void __iomem
*timer2_va_base
;
491 void __iomem
*timer3_va_base
;
494 * How long is the timer interval?
496 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
497 #if TIMER_INTERVAL >= 0x100000
498 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
499 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
500 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
501 #elif TIMER_INTERVAL >= 0x10000
502 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
503 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
504 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
506 #define TIMER_RELOAD (TIMER_INTERVAL)
507 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
508 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
511 static void timer_set_mode(enum clock_event_mode mode
,
512 struct clock_event_device
*clk
)
517 case CLOCK_EVT_MODE_PERIODIC
:
518 writel(TIMER_RELOAD
, timer0_va_base
+ TIMER_LOAD
);
520 ctrl
= TIMER_CTRL_PERIODIC
;
521 ctrl
|= TIMER_CTRL_32BIT
| TIMER_CTRL_IE
| TIMER_CTRL_ENABLE
;
523 case CLOCK_EVT_MODE_ONESHOT
:
524 /* period set, and timer enabled in 'next_event' hook */
525 ctrl
= TIMER_CTRL_ONESHOT
;
526 ctrl
|= TIMER_CTRL_32BIT
| TIMER_CTRL_IE
;
528 case CLOCK_EVT_MODE_UNUSED
:
529 case CLOCK_EVT_MODE_SHUTDOWN
:
534 writel(ctrl
, timer0_va_base
+ TIMER_CTRL
);
537 static int timer_set_next_event(unsigned long evt
,
538 struct clock_event_device
*unused
)
540 unsigned long ctrl
= readl(timer0_va_base
+ TIMER_CTRL
);
542 writel(evt
, timer0_va_base
+ TIMER_LOAD
);
543 writel(ctrl
| TIMER_CTRL_ENABLE
, timer0_va_base
+ TIMER_CTRL
);
548 static struct clock_event_device timer0_clockevent
= {
551 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
552 .set_mode
= timer_set_mode
,
553 .set_next_event
= timer_set_next_event
,
555 .cpumask
= CPU_MASK_ALL
,
558 static void __init
realview_clockevents_init(unsigned int timer_irq
)
560 timer0_clockevent
.irq
= timer_irq
;
561 timer0_clockevent
.mult
=
562 div_sc(1000000, NSEC_PER_SEC
, timer0_clockevent
.shift
);
563 timer0_clockevent
.max_delta_ns
=
564 clockevent_delta2ns(0xffffffff, &timer0_clockevent
);
565 timer0_clockevent
.min_delta_ns
=
566 clockevent_delta2ns(0xf, &timer0_clockevent
);
568 clockevents_register_device(&timer0_clockevent
);
572 * IRQ handler for the timer
574 static irqreturn_t
realview_timer_interrupt(int irq
, void *dev_id
)
576 struct clock_event_device
*evt
= &timer0_clockevent
;
578 /* clear the interrupt */
579 writel(1, timer0_va_base
+ TIMER_INTCLR
);
581 evt
->event_handler(evt
);
586 static struct irqaction realview_timer_irq
= {
587 .name
= "RealView Timer Tick",
588 .flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_IRQPOLL
,
589 .handler
= realview_timer_interrupt
,
592 static cycle_t
realview_get_cycles(void)
594 return ~readl(timer3_va_base
+ TIMER_VALUE
);
597 static struct clocksource clocksource_realview
= {
600 .read
= realview_get_cycles
,
601 .mask
= CLOCKSOURCE_MASK(32),
603 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
606 static void __init
realview_clocksource_init(void)
608 /* setup timer 0 as free-running clocksource */
609 writel(0, timer3_va_base
+ TIMER_CTRL
);
610 writel(0xffffffff, timer3_va_base
+ TIMER_LOAD
);
611 writel(0xffffffff, timer3_va_base
+ TIMER_VALUE
);
612 writel(TIMER_CTRL_32BIT
| TIMER_CTRL_ENABLE
| TIMER_CTRL_PERIODIC
,
613 timer3_va_base
+ TIMER_CTRL
);
615 clocksource_realview
.mult
=
616 clocksource_khz2mult(1000, clocksource_realview
.shift
);
617 clocksource_register(&clocksource_realview
);
621 * Set up the clock source and clock events devices
623 void __init
realview_timer_init(unsigned int timer_irq
)
627 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
629 * The dummy clock device has to be registered before the main device
630 * so that the latter will broadcast the clock events
636 * set clock frequency:
637 * REALVIEW_REFCLK is 32KHz
638 * REALVIEW_TIMCLK is 1MHz
640 val
= readl(__io_address(REALVIEW_SCTL_BASE
));
641 writel((REALVIEW_TIMCLK
<< REALVIEW_TIMER1_EnSel
) |
642 (REALVIEW_TIMCLK
<< REALVIEW_TIMER2_EnSel
) |
643 (REALVIEW_TIMCLK
<< REALVIEW_TIMER3_EnSel
) |
644 (REALVIEW_TIMCLK
<< REALVIEW_TIMER4_EnSel
) | val
,
645 __io_address(REALVIEW_SCTL_BASE
));
648 * Initialise to a known state (all timers off)
650 writel(0, timer0_va_base
+ TIMER_CTRL
);
651 writel(0, timer1_va_base
+ TIMER_CTRL
);
652 writel(0, timer2_va_base
+ TIMER_CTRL
);
653 writel(0, timer3_va_base
+ TIMER_CTRL
);
656 * Make irqs happen for the system timer
658 setup_irq(timer_irq
, &realview_timer_irq
);
660 realview_clocksource_init();
661 realview_clockevents_init(timer_irq
);