arch/arm/mach-realview/core.c

   1 /*
   2  *  linux/arch/arm/mach-realview/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/sysdev.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/amba/clcd.h>
  28 #include <linux/clocksource.h>
  29 #include <linux/clockchips.h>
  30 #include <linux/io.h>
  31 #include <linux/smc911x.h>
  32
  33 #include <asm/system.h>
  34 #include <mach/hardware.h>
  35 #include <asm/irq.h>
  36 #include <asm/leds.h>
  37 #include <asm/mach-types.h>
  38 #include <asm/hardware/arm_timer.h>
  39 #include <asm/hardware/icst307.h>
  40
  41 #include <asm/mach/arch.h>
  42 #include <asm/mach/flash.h>
  43 #include <asm/mach/irq.h>
  44 #include <asm/mach/map.h>
  45 #include <asm/mach/mmc.h>
  46
  47 #include <asm/hardware/gic.h>
  48
  49 #include "core.h"
  50 #include "clock.h"
  51
  52 #define REALVIEW_REFCOUNTER     (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
  53
  54 /* used by entry-macro.S and platsmp.c */
  55 void __iomem *gic_cpu_base_addr;
  56
  57 /*
  58  * This is the RealView sched_clock implementation.  This has
  59  * a resolution of 41.7ns, and a maximum value of about 179s.
  60  */
  61 unsigned long long sched_clock(void)
  62 {
  63         unsigned long long v;
  64
  65         v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
  66         do_div(v, 3);
  67
  68         return v;
  69 }
  70
  71
  72 #define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
  73
  74 static int realview_flash_init(void)
  75 {
  76         u32 val;
  77
  78         val = __raw_readl(REALVIEW_FLASHCTRL);
  79         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  80         __raw_writel(val, REALVIEW_FLASHCTRL);
  81
  82         return 0;
  83 }
  84
  85 static void realview_flash_exit(void)
  86 {
  87         u32 val;
  88
  89         val = __raw_readl(REALVIEW_FLASHCTRL);
  90         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  91         __raw_writel(val, REALVIEW_FLASHCTRL);
  92 }
  93
  94 static void realview_flash_set_vpp(int on)
  95 {
  96         u32 val;
  97
  98         val = __raw_readl(REALVIEW_FLASHCTRL);
  99         if (on)
 100                 val |= REALVIEW_FLASHPROG_FLVPPEN;
 101         else
 102                 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
 103         __raw_writel(val, REALVIEW_FLASHCTRL);
 104 }
 105
 106 static struct flash_platform_data realview_flash_data = {
 107         .map_name               = "cfi_probe",
 108         .width                  = 4,
 109         .init                   = realview_flash_init,
 110         .exit                   = realview_flash_exit,
 111         .set_vpp                = realview_flash_set_vpp,
 112 };
 113
 114 struct platform_device realview_flash_device = {
 115         .name                   = "armflash",
 116         .id                     = 0,
 117         .dev                    = {
 118                 .platform_data  = &realview_flash_data,
 119         },
 120 };
 121
 122 int realview_flash_register(struct resource *res, u32 num)
 123 {
 124         realview_flash_device.resource = res;
 125         realview_flash_device.num_resources = num;
 126         return platform_device_register(&realview_flash_device);
 127 }
 128
 129 static struct smc911x_platdata realview_smc911x_platdata = {
 130         .flags          = SMC911X_USE_32BIT,
 131         .irq_flags      = IRQF_SHARED,
 132         .irq_polarity   = 1,
 133 };
 134
 135 static struct platform_device realview_eth_device = {
 136         .name           = "smc911x",
 137         .id             = 0,
 138         .num_resources  = 2,
 139 };
 140
 141 int realview_eth_register(const char *name, struct resource *res)
 142 {
 143         if (name)
 144                 realview_eth_device.name = name;
 145         realview_eth_device.resource = res;
 146         if (strcmp(realview_eth_device.name, "smc911x") == 0)
 147                 realview_eth_device.dev.platform_data = &realview_smc911x_platdata;
 148
 149         return platform_device_register(&realview_eth_device);
 150 }
 151
 152 static struct resource realview_i2c_resource = {
 153         .start          = REALVIEW_I2C_BASE,
 154         .end            = REALVIEW_I2C_BASE + SZ_4K - 1,
 155         .flags          = IORESOURCE_MEM,
 156 };
 157
 158 struct platform_device realview_i2c_device = {
 159         .name           = "versatile-i2c",
 160         .id             = -1,
 161         .num_resources  = 1,
 162         .resource       = &realview_i2c_resource,
 163 };
 164
 165 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
 166
 167 static unsigned int realview_mmc_status(struct device *dev)
 168 {
 169         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 170         u32 mask;
 171
 172         if (adev->res.start == REALVIEW_MMCI0_BASE)
 173                 mask = 1;
 174         else
 175                 mask = 2;
 176
 177         return readl(REALVIEW_SYSMCI) & mask;
 178 }
 179
 180 struct mmc_platform_data realview_mmc0_plat_data = {
 181         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 182         .status         = realview_mmc_status,
 183 };
 184
 185 struct mmc_platform_data realview_mmc1_plat_data = {
 186         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 187         .status         = realview_mmc_status,
 188 };
 189
 190 /*
 191  * Clock handling
 192  */
 193 static const struct icst307_params realview_oscvco_params = {
 194         .ref            = 24000,
 195         .vco_max        = 200000,
 196         .vd_min         = 4 + 8,
 197         .vd_max         = 511 + 8,
 198         .rd_min         = 1 + 2,
 199         .rd_max         = 127 + 2,
 200 };
 201
 202 static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
 203 {
 204         void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
 205         void __iomem *sys_osc;
 206         u32 val;
 207
 208         if (machine_is_realview_pb1176())
 209                 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
 210         else
 211                 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
 212
 213         val = readl(sys_osc) & ~0x7ffff;
 214         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 215
 216         writel(0xa05f, sys_lock);
 217         writel(val, sys_osc);
 218         writel(0, sys_lock);
 219 }
 220
 221 struct clk realview_clcd_clk = {
 222         .name   = "CLCDCLK",
 223         .params = &realview_oscvco_params,
 224         .setvco = realview_oscvco_set,
 225 };
 226
 227 /*
 228  * CLCD support.
 229  */
 230 #define SYS_CLCD_NLCDIOON       (1 << 2)
 231 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 232 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 233 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 234 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 235 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 236 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 237 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 238 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 239
 240 static struct clcd_panel vga = {
 241         .mode           = {
 242                 .name           = "VGA",
 243                 .refresh        = 60,
 244                 .xres           = 640,
 245                 .yres           = 480,
 246                 .pixclock       = 39721,
 247                 .left_margin    = 40,
 248                 .right_margin   = 24,
 249                 .upper_margin   = 32,
 250                 .lower_margin   = 11,
 251                 .hsync_len      = 96,
 252                 .vsync_len      = 2,
 253                 .sync           = 0,
 254                 .vmode          = FB_VMODE_NONINTERLACED,
 255         },
 256         .width          = -1,
 257         .height         = -1,
 258         .tim2           = TIM2_BCD | TIM2_IPC,
 259         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 260         .bpp            = 16,
 261 };
 262
 263 static struct clcd_panel xvga = {
 264         .mode           = {
 265                 .name           = "XVGA",
 266                 .refresh        = 60,
 267                 .xres           = 1024,
 268                 .yres           = 768,
 269                 .pixclock       = 15748,
 270                 .left_margin    = 152,
 271                 .right_margin   = 48,
 272                 .upper_margin   = 23,
 273                 .lower_margin   = 3,
 274                 .hsync_len      = 104,
 275                 .vsync_len      = 4,
 276                 .sync           = 0,
 277                 .vmode          = FB_VMODE_NONINTERLACED,
 278         },
 279         .width          = -1,
 280         .height         = -1,
 281         .tim2           = TIM2_BCD | TIM2_IPC,
 282         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 283         .bpp            = 16,
 284 };
 285
 286 static struct clcd_panel sanyo_3_8_in = {
 287         .mode           = {
 288                 .name           = "Sanyo QVGA",
 289                 .refresh        = 116,
 290                 .xres           = 320,
 291                 .yres           = 240,
 292                 .pixclock       = 100000,
 293                 .left_margin    = 6,
 294                 .right_margin   = 6,
 295                 .upper_margin   = 5,
 296                 .lower_margin   = 5,
 297                 .hsync_len      = 6,
 298                 .vsync_len      = 6,
 299                 .sync           = 0,
 300                 .vmode          = FB_VMODE_NONINTERLACED,
 301         },
 302         .width          = -1,
 303         .height         = -1,
 304         .tim2           = TIM2_BCD,
 305         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 306         .bpp            = 16,
 307 };
 308
 309 static struct clcd_panel sanyo_2_5_in = {
 310         .mode           = {
 311                 .name           = "Sanyo QVGA Portrait",
 312                 .refresh        = 116,
 313                 .xres           = 240,
 314                 .yres           = 320,
 315                 .pixclock       = 100000,
 316                 .left_margin    = 20,
 317                 .right_margin   = 10,
 318                 .upper_margin   = 2,
 319                 .lower_margin   = 2,
 320                 .hsync_len      = 10,
 321                 .vsync_len      = 2,
 322                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 323                 .vmode          = FB_VMODE_NONINTERLACED,
 324         },
 325         .width          = -1,
 326         .height         = -1,
 327         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 328         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 329         .bpp            = 16,
 330 };
 331
 332 static struct clcd_panel epson_2_2_in = {
 333         .mode           = {
 334                 .name           = "Epson QCIF",
 335                 .refresh        = 390,
 336                 .xres           = 176,
 337                 .yres           = 220,
 338                 .pixclock       = 62500,
 339                 .left_margin    = 3,
 340                 .right_margin   = 2,
 341                 .upper_margin   = 1,
 342                 .lower_margin   = 0,
 343                 .hsync_len      = 3,
 344                 .vsync_len      = 2,
 345                 .sync           = 0,
 346                 .vmode          = FB_VMODE_NONINTERLACED,
 347         },
 348         .width          = -1,
 349         .height         = -1,
 350         .tim2           = TIM2_BCD | TIM2_IPC,
 351         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 352         .bpp            = 16,
 353 };
 354
 355 /*
 356  * Detect which LCD panel is connected, and return the appropriate
 357  * clcd_panel structure.  Note: we do not have any information on
 358  * the required timings for the 8.4in panel, so we presently assume
 359  * VGA timings.
 360  */
 361 static struct clcd_panel *realview_clcd_panel(void)
 362 {
 363         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 364         struct clcd_panel *vga_panel;
 365         struct clcd_panel *panel;
 366         u32 val;
 367
 368         if (machine_is_realview_eb())
 369                 vga_panel = &vga;
 370         else
 371                 vga_panel = &xvga;
 372
 373         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 374         if (val == SYS_CLCD_ID_SANYO_3_8)
 375                 panel = &sanyo_3_8_in;
 376         else if (val == SYS_CLCD_ID_SANYO_2_5)
 377                 panel = &sanyo_2_5_in;
 378         else if (val == SYS_CLCD_ID_EPSON_2_2)
 379                 panel = &epson_2_2_in;
 380         else if (val == SYS_CLCD_ID_VGA)
 381                 panel = vga_panel;
 382         else {
 383                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 384                         val);
 385                 panel = vga_panel;
 386         }
 387
 388         return panel;
 389 }
 390
 391 /*
 392  * Disable all display connectors on the interface module.
 393  */
 394 static void realview_clcd_disable(struct clcd_fb *fb)
 395 {
 396         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 397         u32 val;
 398
 399         val = readl(sys_clcd);
 400         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 401         writel(val, sys_clcd);
 402 }
 403
 404 /*
 405  * Enable the relevant connector on the interface module.
 406  */
 407 static void realview_clcd_enable(struct clcd_fb *fb)
 408 {
 409         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 410         u32 val;
 411
 412         /*
 413          * Enable the PSUs
 414          */
 415         val = readl(sys_clcd);
 416         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 417         writel(val, sys_clcd);
 418 }
 419
 420 static int realview_clcd_setup(struct clcd_fb *fb)
 421 {
 422         unsigned long framesize;
 423         dma_addr_t dma;
 424
 425         if (machine_is_realview_eb())
 426                 /* VGA, 16bpp */
 427                 framesize = 640 * 480 * 2;
 428         else
 429                 /* XVGA, 16bpp */
 430                 framesize = 1024 * 768 * 2;
 431
 432         fb->panel               = realview_clcd_panel();
 433
 434         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 435                                                     &dma, GFP_KERNEL);
 436         if (!fb->fb.screen_base) {
 437                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 438                 return -ENOMEM;
 439         }
 440
 441         fb->fb.fix.smem_start   = dma;
 442         fb->fb.fix.smem_len     = framesize;
 443
 444         return 0;
 445 }
 446
 447 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 448 {
 449         return dma_mmap_writecombine(&fb->dev->dev, vma,
 450                                      fb->fb.screen_base,
 451                                      fb->fb.fix.smem_start,
 452                                      fb->fb.fix.smem_len);
 453 }
 454
 455 static void realview_clcd_remove(struct clcd_fb *fb)
 456 {
 457         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 458                               fb->fb.screen_base, fb->fb.fix.smem_start);
 459 }
 460
 461 struct clcd_board clcd_plat_data = {
 462         .name           = "RealView",
 463         .check          = clcdfb_check,
 464         .decode         = clcdfb_decode,
 465         .disable        = realview_clcd_disable,
 466         .enable         = realview_clcd_enable,
 467         .setup          = realview_clcd_setup,
 468         .mmap           = realview_clcd_mmap,
 469         .remove         = realview_clcd_remove,
 470 };
 471
 472 #ifdef CONFIG_LEDS
 473 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
 474
 475 void realview_leds_event(led_event_t ledevt)
 476 {
 477         unsigned long flags;
 478         u32 val;
 479
 480         local_irq_save(flags);
 481         val = readl(VA_LEDS_BASE);
 482
 483         switch (ledevt) {
 484         case led_idle_start:
 485                 val = val & ~REALVIEW_SYS_LED0;
 486                 break;
 487
 488         case led_idle_end:
 489                 val = val | REALVIEW_SYS_LED0;
 490                 break;
 491
 492         case led_timer:
 493                 val = val ^ REALVIEW_SYS_LED1;
 494                 break;
 495
 496         case led_halted:
 497                 val = 0;
 498                 break;
 499
 500         default:
 501                 break;
 502         }
 503
 504         writel(val, VA_LEDS_BASE);
 505         local_irq_restore(flags);
 506 }
 507 #endif  /* CONFIG_LEDS */
 508
 509 /*
 510  * Where is the timer (VA)?
 511  */
 512 void __iomem *timer0_va_base;
 513 void __iomem *timer1_va_base;
 514 void __iomem *timer2_va_base;
 515 void __iomem *timer3_va_base;
 516
 517 /*
 518  * How long is the timer interval?
 519  */
 520 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 521 #if TIMER_INTERVAL >= 0x100000
 522 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
 523 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
 524 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 525 #elif TIMER_INTERVAL >= 0x10000
 526 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
 527 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
 528 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 529 #else
 530 #define TIMER_RELOAD    (TIMER_INTERVAL)
 531 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
 532 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 533 #endif
 534
 535 static void timer_set_mode(enum clock_event_mode mode,
 536                            struct clock_event_device *clk)
 537 {
 538         unsigned long ctrl;
 539
 540         switch(mode) {
 541         case CLOCK_EVT_MODE_PERIODIC:
 542                 writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
 543
 544                 ctrl = TIMER_CTRL_PERIODIC;
 545                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
 546                 break;
 547         case CLOCK_EVT_MODE_ONESHOT:
 548                 /* period set, and timer enabled in 'next_event' hook */
 549                 ctrl = TIMER_CTRL_ONESHOT;
 550                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
 551                 break;
 552         case CLOCK_EVT_MODE_UNUSED:
 553         case CLOCK_EVT_MODE_SHUTDOWN:
 554         default:
 555                 ctrl = 0;
 556         }
 557
 558         writel(ctrl, timer0_va_base + TIMER_CTRL);
 559 }
 560
 561 static int timer_set_next_event(unsigned long evt,
 562                                 struct clock_event_device *unused)
 563 {
 564         unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
 565
 566         writel(evt, timer0_va_base + TIMER_LOAD);
 567         writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
 568
 569         return 0;
 570 }
 571
 572 static struct clock_event_device timer0_clockevent =     {
 573         .name           = "timer0",
 574         .shift          = 32,
 575         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 576         .set_mode       = timer_set_mode,
 577         .set_next_event = timer_set_next_event,
 578         .rating         = 300,
 579         .cpumask        = CPU_MASK_ALL,
 580 };
 581
 582 static void __init realview_clockevents_init(unsigned int timer_irq)
 583 {
 584         timer0_clockevent.irq = timer_irq;
 585         timer0_clockevent.mult =
 586                 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
 587         timer0_clockevent.max_delta_ns =
 588                 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
 589         timer0_clockevent.min_delta_ns =
 590                 clockevent_delta2ns(0xf, &timer0_clockevent);
 591
 592         clockevents_register_device(&timer0_clockevent);
 593 }
 594
 595 /*
 596  * IRQ handler for the timer
 597  */
 598 static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
 599 {
 600         struct clock_event_device *evt = &timer0_clockevent;
 601
 602         /* clear the interrupt */
 603         writel(1, timer0_va_base + TIMER_INTCLR);
 604
 605         evt->event_handler(evt);
 606
 607         return IRQ_HANDLED;
 608 }
 609
 610 static struct irqaction realview_timer_irq = {
 611         .name           = "RealView Timer Tick",
 612         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 613         .handler        = realview_timer_interrupt,
 614 };
 615
 616 static cycle_t realview_get_cycles(void)
 617 {
 618         return ~readl(timer3_va_base + TIMER_VALUE);
 619 }
 620
 621 static struct clocksource clocksource_realview = {
 622         .name   = "timer3",
 623         .rating = 200,
 624         .read   = realview_get_cycles,
 625         .mask   = CLOCKSOURCE_MASK(32),
 626         .shift  = 20,
 627         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 628 };
 629
 630 static void __init realview_clocksource_init(void)
 631 {
 632         /* setup timer 0 as free-running clocksource */
 633         writel(0, timer3_va_base + TIMER_CTRL);
 634         writel(0xffffffff, timer3_va_base + TIMER_LOAD);
 635         writel(0xffffffff, timer3_va_base + TIMER_VALUE);
 636         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
 637                 timer3_va_base + TIMER_CTRL);
 638
 639         clocksource_realview.mult =
 640                 clocksource_khz2mult(1000, clocksource_realview.shift);
 641         clocksource_register(&clocksource_realview);
 642 }
 643
 644 /*
 645  * Set up the clock source and clock events devices
 646  */
 647 void __init realview_timer_init(unsigned int timer_irq)
 648 {
 649         u32 val;
 650
 651 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
 652         /*
 653          * The dummy clock device has to be registered before the main device
 654          * so that the latter will broadcast the clock events
 655          */
 656         local_timer_setup();
 657 #endif
 658
 659         /*
 660          * set clock frequency:
 661          *      REALVIEW_REFCLK is 32KHz
 662          *      REALVIEW_TIMCLK is 1MHz
 663          */
 664         val = readl(__io_address(REALVIEW_SCTL_BASE));
 665         writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
 666                (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
 667                (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
 668                (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
 669                __io_address(REALVIEW_SCTL_BASE));
 670
 671         /*
 672          * Initialise to a known state (all timers off)
 673          */
 674         writel(0, timer0_va_base + TIMER_CTRL);
 675         writel(0, timer1_va_base + TIMER_CTRL);
 676         writel(0, timer2_va_base + TIMER_CTRL);
 677         writel(0, timer3_va_base + TIMER_CTRL);
 678
 679         /*
 680          * Make irqs happen for the system timer
 681          */
 682         setup_irq(timer_irq, &realview_timer_irq);
 683
 684         realview_clocksource_init();
 685         realview_clockevents_init(timer_irq);
 686 }