2 * arch/arm/mach-orion5x/pci.c
4 * PCI and PCIe functions for Marvell Orion System On Chip
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/mbus.h>
17 #include <video/vga.h>
19 #include <asm/mach/pci.h>
20 #include <plat/pcie.h>
21 #include <plat/addr-map.h>
22 #include <mach/orion5x.h>
25 /*****************************************************************************
26 * Orion has one PCIe controller and one PCI controller.
28 * Note1: The local PCIe bus number is '0'. The local PCI bus number
29 * follows the scanned PCIe bridged busses, if any.
31 * Note2: It is possible for PCI/PCIe agents to access many subsystem's
32 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
33 * device bus, Orion registers, etc. However this code only enable the
34 * access to DDR banks.
35 ****************************************************************************/
38 /*****************************************************************************
40 ****************************************************************************/
41 #define PCIE_BASE (ORION5X_PCIE_VIRT_BASE)
43 void __init
orion5x_pcie_id(u32
*dev
, u32
*rev
)
45 *dev
= orion_pcie_dev_id(PCIE_BASE
);
46 *rev
= orion_pcie_rev(PCIE_BASE
);
49 static int pcie_valid_config(int bus
, int dev
)
52 * Don't go out when trying to access --
53 * 1. nonexisting device on local bus
54 * 2. where there's no device connected (no link)
56 if (bus
== 0 && dev
== 0)
59 if (!orion_pcie_link_up(PCIE_BASE
))
62 if (bus
== 0 && dev
!= 1)
70 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
71 * and then reading the PCIE_CONF_DATA register. Need to make sure these
72 * transactions are atomic.
74 static DEFINE_SPINLOCK(orion5x_pcie_lock
);
76 static int pcie_rd_conf(struct pci_bus
*bus
, u32 devfn
, int where
,
82 if (pcie_valid_config(bus
->number
, PCI_SLOT(devfn
)) == 0) {
84 return PCIBIOS_DEVICE_NOT_FOUND
;
87 spin_lock_irqsave(&orion5x_pcie_lock
, flags
);
88 ret
= orion_pcie_rd_conf(PCIE_BASE
, bus
, devfn
, where
, size
, val
);
89 spin_unlock_irqrestore(&orion5x_pcie_lock
, flags
);
94 static int pcie_rd_conf_wa(struct pci_bus
*bus
, u32 devfn
,
95 int where
, int size
, u32
*val
)
99 if (pcie_valid_config(bus
->number
, PCI_SLOT(devfn
)) == 0) {
101 return PCIBIOS_DEVICE_NOT_FOUND
;
105 * We only support access to the non-extended configuration
106 * space when using the WA access method (or we would have to
107 * sacrifice 256M of CPU virtual address space.)
109 if (where
>= 0x100) {
111 return PCIBIOS_DEVICE_NOT_FOUND
;
114 ret
= orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE
,
115 bus
, devfn
, where
, size
, val
);
120 static int pcie_wr_conf(struct pci_bus
*bus
, u32 devfn
,
121 int where
, int size
, u32 val
)
126 if (pcie_valid_config(bus
->number
, PCI_SLOT(devfn
)) == 0)
127 return PCIBIOS_DEVICE_NOT_FOUND
;
129 spin_lock_irqsave(&orion5x_pcie_lock
, flags
);
130 ret
= orion_pcie_wr_conf(PCIE_BASE
, bus
, devfn
, where
, size
, val
);
131 spin_unlock_irqrestore(&orion5x_pcie_lock
, flags
);
136 static struct pci_ops pcie_ops
= {
137 .read
= pcie_rd_conf
,
138 .write
= pcie_wr_conf
,
142 static int __init
pcie_setup(struct pci_sys_data
*sys
)
144 struct resource
*res
;
148 * Generic PCIe unit setup.
150 orion_pcie_setup(PCIE_BASE
);
153 * Check whether to apply Orion-1/Orion-NAS PCIe config
154 * read transaction workaround.
156 dev
= orion_pcie_dev_id(PCIE_BASE
);
157 if (dev
== MV88F5181_DEV_ID
|| dev
== MV88F5182_DEV_ID
) {
158 printk(KERN_NOTICE
"Applying Orion-1/Orion-NAS PCIe config "
159 "read transaction workaround\n");
160 orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE
,
161 ORION5X_PCIE_WA_SIZE
);
162 pcie_ops
.read
= pcie_rd_conf_wa
;
165 pci_ioremap_io(sys
->busnr
* SZ_64K
, ORION5X_PCIE_IO_PHYS_BASE
);
170 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
172 panic("pcie_setup unable to alloc resources");
177 res
->name
= "PCIe Memory Space";
178 res
->flags
= IORESOURCE_MEM
;
179 res
->start
= ORION5X_PCIE_MEM_PHYS_BASE
;
180 res
->end
= res
->start
+ ORION5X_PCIE_MEM_SIZE
- 1;
181 if (request_resource(&iomem_resource
, res
))
182 panic("Request PCIe Memory resource failed\n");
183 pci_add_resource_offset(&sys
->resources
, res
, sys
->mem_offset
);
188 /*****************************************************************************
190 ****************************************************************************/
191 #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE + (x))
192 #define PCI_MODE ORION5X_PCI_REG(0xd00)
193 #define PCI_CMD ORION5X_PCI_REG(0xc00)
194 #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
195 #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78)
196 #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c)
201 #define PCI_MODE_64BIT (1 << 2)
202 #define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
207 #define PCI_CMD_HOST_REORDER (1 << 29)
212 #define PCI_P2P_BUS_OFFS 16
213 #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
214 #define PCI_P2P_DEV_OFFS 24
215 #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
220 #define PCI_CONF_REG(reg) ((reg) & 0xfc)
221 #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
222 #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
223 #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
224 #define PCI_CONF_ADDR_EN (1 << 31)
227 * Internal configuration space
229 #define PCI_CONF_FUNC_STAT_CMD 0
230 #define PCI_CONF_REG_STAT_CMD 4
231 #define PCIX_STAT 0x64
232 #define PCIX_STAT_BUS_OFFS 8
233 #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
236 * PCI Address Decode Windows registers
238 #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
239 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
240 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
241 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
242 #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
243 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
244 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
245 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
246 #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c)
247 #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c)
250 * PCI configuration helpers for BAR settings
252 #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
253 #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
254 #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
257 * PCI config cycles are done by programming the PCI_CONF_ADDR register
258 * and then reading the PCI_CONF_DATA register. Need to make sure these
259 * transactions are atomic.
261 static DEFINE_SPINLOCK(orion5x_pci_lock
);
263 static int orion5x_pci_cardbus_mode
;
265 static int orion5x_pci_local_bus_nr(void)
267 u32 conf
= readl(PCI_P2P_CONF
);
268 return((conf
& PCI_P2P_BUS_MASK
) >> PCI_P2P_BUS_OFFS
);
271 static int orion5x_pci_hw_rd_conf(int bus
, int dev
, u32 func
,
272 u32 where
, u32 size
, u32
*val
)
275 spin_lock_irqsave(&orion5x_pci_lock
, flags
);
277 writel(PCI_CONF_BUS(bus
) |
278 PCI_CONF_DEV(dev
) | PCI_CONF_REG(where
) |
279 PCI_CONF_FUNC(func
) | PCI_CONF_ADDR_EN
, PCI_CONF_ADDR
);
281 *val
= readl(PCI_CONF_DATA
);
284 *val
= (*val
>> (8*(where
& 0x3))) & 0xff;
286 *val
= (*val
>> (8*(where
& 0x3))) & 0xffff;
288 spin_unlock_irqrestore(&orion5x_pci_lock
, flags
);
290 return PCIBIOS_SUCCESSFUL
;
293 static int orion5x_pci_hw_wr_conf(int bus
, int dev
, u32 func
,
294 u32 where
, u32 size
, u32 val
)
297 int ret
= PCIBIOS_SUCCESSFUL
;
299 spin_lock_irqsave(&orion5x_pci_lock
, flags
);
301 writel(PCI_CONF_BUS(bus
) |
302 PCI_CONF_DEV(dev
) | PCI_CONF_REG(where
) |
303 PCI_CONF_FUNC(func
) | PCI_CONF_ADDR_EN
, PCI_CONF_ADDR
);
306 __raw_writel(val
, PCI_CONF_DATA
);
307 } else if (size
== 2) {
308 __raw_writew(val
, PCI_CONF_DATA
+ (where
& 0x3));
309 } else if (size
== 1) {
310 __raw_writeb(val
, PCI_CONF_DATA
+ (where
& 0x3));
312 ret
= PCIBIOS_BAD_REGISTER_NUMBER
;
315 spin_unlock_irqrestore(&orion5x_pci_lock
, flags
);
320 static int orion5x_pci_valid_config(int bus
, u32 devfn
)
322 if (bus
== orion5x_pci_local_bus_nr()) {
324 * Don't go out for local device
326 if (PCI_SLOT(devfn
) == 0 && PCI_FUNC(devfn
) != 0)
330 * When the PCI signals are directly connected to a
331 * Cardbus slot, ignore all but device IDs 0 and 1.
333 if (orion5x_pci_cardbus_mode
&& PCI_SLOT(devfn
) > 1)
340 static int orion5x_pci_rd_conf(struct pci_bus
*bus
, u32 devfn
,
341 int where
, int size
, u32
*val
)
343 if (!orion5x_pci_valid_config(bus
->number
, devfn
)) {
345 return PCIBIOS_DEVICE_NOT_FOUND
;
348 return orion5x_pci_hw_rd_conf(bus
->number
, PCI_SLOT(devfn
),
349 PCI_FUNC(devfn
), where
, size
, val
);
352 static int orion5x_pci_wr_conf(struct pci_bus
*bus
, u32 devfn
,
353 int where
, int size
, u32 val
)
355 if (!orion5x_pci_valid_config(bus
->number
, devfn
))
356 return PCIBIOS_DEVICE_NOT_FOUND
;
358 return orion5x_pci_hw_wr_conf(bus
->number
, PCI_SLOT(devfn
),
359 PCI_FUNC(devfn
), where
, size
, val
);
362 static struct pci_ops pci_ops
= {
363 .read
= orion5x_pci_rd_conf
,
364 .write
= orion5x_pci_wr_conf
,
367 static void __init
orion5x_pci_set_bus_nr(int nr
)
369 u32 p2p
= readl(PCI_P2P_CONF
);
371 if (readl(PCI_MODE
) & PCI_MODE_PCIX
) {
375 u32 pcix_status
, bus
, dev
;
376 bus
= (p2p
& PCI_P2P_BUS_MASK
) >> PCI_P2P_BUS_OFFS
;
377 dev
= (p2p
& PCI_P2P_DEV_MASK
) >> PCI_P2P_DEV_OFFS
;
378 orion5x_pci_hw_rd_conf(bus
, dev
, 0, PCIX_STAT
, 4, &pcix_status
);
379 pcix_status
&= ~PCIX_STAT_BUS_MASK
;
380 pcix_status
|= (nr
<< PCIX_STAT_BUS_OFFS
);
381 orion5x_pci_hw_wr_conf(bus
, dev
, 0, PCIX_STAT
, 4, pcix_status
);
384 * PCI Conventional mode
386 p2p
&= ~PCI_P2P_BUS_MASK
;
387 p2p
|= (nr
<< PCI_P2P_BUS_OFFS
);
388 writel(p2p
, PCI_P2P_CONF
);
392 static void __init
orion5x_pci_master_slave_enable(void)
394 int bus_nr
, func
, reg
;
397 bus_nr
= orion5x_pci_local_bus_nr();
398 func
= PCI_CONF_FUNC_STAT_CMD
;
399 reg
= PCI_CONF_REG_STAT_CMD
;
400 orion5x_pci_hw_rd_conf(bus_nr
, 0, func
, reg
, 4, &val
);
401 val
|= (PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
402 orion5x_pci_hw_wr_conf(bus_nr
, 0, func
, reg
, 4, val
| 0x7);
405 static void __init
orion5x_setup_pci_wins(struct mbus_dram_target_info
*dram
)
412 * First, disable windows.
414 win_enable
= 0xffffffff;
415 writel(win_enable
, PCI_BAR_ENABLE
);
418 * Setup windows for DDR banks.
420 bus
= orion5x_pci_local_bus_nr();
422 for (i
= 0; i
< dram
->num_cs
; i
++) {
423 struct mbus_dram_window
*cs
= dram
->cs
+ i
;
424 u32 func
= PCI_CONF_FUNC_BAR_CS(cs
->cs_index
);
429 * Write DRAM bank base address register.
431 reg
= PCI_CONF_REG_BAR_LO_CS(cs
->cs_index
);
432 orion5x_pci_hw_rd_conf(bus
, 0, func
, reg
, 4, &val
);
433 val
= (cs
->base
& 0xfffff000) | (val
& 0xfff);
434 orion5x_pci_hw_wr_conf(bus
, 0, func
, reg
, 4, val
);
437 * Write DRAM bank size register.
439 reg
= PCI_CONF_REG_BAR_HI_CS(cs
->cs_index
);
440 orion5x_pci_hw_wr_conf(bus
, 0, func
, reg
, 4, 0);
441 writel((cs
->size
- 1) & 0xfffff000,
442 PCI_BAR_SIZE_DDR_CS(cs
->cs_index
));
443 writel(cs
->base
& 0xfffff000,
444 PCI_BAR_REMAP_DDR_CS(cs
->cs_index
));
447 * Enable decode window for this chip select.
449 win_enable
&= ~(1 << cs
->cs_index
);
453 * Re-enable decode windows.
455 writel(win_enable
, PCI_BAR_ENABLE
);
458 * Disable automatic update of address remapping when writing to BARs.
460 orion5x_setbits(PCI_ADDR_DECODE_CTRL
, 1);
463 static int __init
pci_setup(struct pci_sys_data
*sys
)
465 struct resource
*res
;
468 * Point PCI unit MBUS decode windows to DRAM space.
470 orion5x_setup_pci_wins(&orion_mbus_dram_info
);
473 * Master + Slave enable
475 orion5x_pci_master_slave_enable();
480 orion5x_setbits(PCI_CMD
, PCI_CMD_HOST_REORDER
);
482 pci_ioremap_io(sys
->busnr
* SZ_64K
, ORION5X_PCI_IO_PHYS_BASE
);
487 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
489 panic("pci_setup unable to alloc resources");
494 res
->name
= "PCI Memory Space";
495 res
->flags
= IORESOURCE_MEM
;
496 res
->start
= ORION5X_PCI_MEM_PHYS_BASE
;
497 res
->end
= res
->start
+ ORION5X_PCI_MEM_SIZE
- 1;
498 if (request_resource(&iomem_resource
, res
))
499 panic("Request PCI Memory resource failed\n");
500 pci_add_resource_offset(&sys
->resources
, res
, sys
->mem_offset
);
506 /*****************************************************************************
508 ****************************************************************************/
509 static void __devinit
rc_pci_fixup(struct pci_dev
*dev
)
512 * Prevent enumeration of root complex.
514 if (dev
->bus
->parent
== NULL
&& dev
->devfn
== 0) {
517 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
518 dev
->resource
[i
].start
= 0;
519 dev
->resource
[i
].end
= 0;
520 dev
->resource
[i
].flags
= 0;
524 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL
, PCI_ANY_ID
, rc_pci_fixup
);
526 static int orion5x_pci_disabled __initdata
;
528 void __init
orion5x_pci_disable(void)
530 orion5x_pci_disabled
= 1;
533 void __init
orion5x_pci_set_cardbus_mode(void)
535 orion5x_pci_cardbus_mode
= 1;
538 int __init
orion5x_pci_sys_setup(int nr
, struct pci_sys_data
*sys
)
542 vga_base
= ORION5X_PCIE_MEM_PHYS_BASE
;
545 orion_pcie_set_local_bus_nr(PCIE_BASE
, sys
->busnr
);
546 ret
= pcie_setup(sys
);
547 } else if (nr
== 1 && !orion5x_pci_disabled
) {
548 orion5x_pci_set_bus_nr(sys
->busnr
);
549 ret
= pci_setup(sys
);
555 struct pci_bus __init
*orion5x_pci_sys_scan_bus(int nr
, struct pci_sys_data
*sys
)
560 bus
= pci_scan_root_bus(NULL
, sys
->busnr
, &pcie_ops
, sys
,
562 } else if (nr
== 1 && !orion5x_pci_disabled
) {
563 bus
= pci_scan_root_bus(NULL
, sys
->busnr
, &pci_ops
, sys
,
573 int __init
orion5x_pci_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
)
575 int bus
= dev
->bus
->number
;
580 if (orion5x_pci_disabled
|| bus
< orion5x_pci_local_bus_nr())
581 return IRQ_ORION5X_PCIE0_INT
;