2 * linux/arch/arm/mach-omap2/timer.c
4 * OMAP2 GP timer support.
6 * Copyright (C) 2009 Nokia Corporation
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
18 * Some parts based off of TI's 24xx code:
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
29 #include <linux/init.h>
30 #include <linux/time.h>
31 #include <linux/interrupt.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/clocksource.h>
37 #include <linux/clockchips.h>
38 #include <linux/slab.h>
40 #include <linux/of_address.h>
41 #include <linux/of_irq.h>
42 #include <linux/platform_device.h>
43 #include <linux/platform_data/dmtimer-omap.h>
45 #include <asm/mach/time.h>
46 #include <asm/smp_twd.h>
47 #include <asm/sched_clock.h>
49 #include <asm/arch_timer.h>
50 #include "omap_hwmod.h"
51 #include "omap_device.h"
52 #include <plat/counter-32k.h>
53 #include <plat/dmtimer.h>
58 #include "powerdomain.h"
60 #define REALTIME_COUNTER_BASE 0x48243200
61 #define INCREMENTER_NUMERATOR_OFFSET 0x10
62 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
63 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000
67 static struct omap_dm_timer clkev
;
68 static struct clock_event_device clockevent_gpt
;
70 static irqreturn_t
omap2_gp_timer_interrupt(int irq
, void *dev_id
)
72 struct clock_event_device
*evt
= &clockevent_gpt
;
74 __omap_dm_timer_write_status(&clkev
, OMAP_TIMER_INT_OVERFLOW
);
76 evt
->event_handler(evt
);
80 static struct irqaction omap2_gp_timer_irq
= {
82 .flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_IRQPOLL
,
83 .handler
= omap2_gp_timer_interrupt
,
86 static int omap2_gp_timer_set_next_event(unsigned long cycles
,
87 struct clock_event_device
*evt
)
89 __omap_dm_timer_load_start(&clkev
, OMAP_TIMER_CTRL_ST
,
90 0xffffffff - cycles
, OMAP_TIMER_POSTED
);
95 static void omap2_gp_timer_set_mode(enum clock_event_mode mode
,
96 struct clock_event_device
*evt
)
100 __omap_dm_timer_stop(&clkev
, OMAP_TIMER_POSTED
, clkev
.rate
);
103 case CLOCK_EVT_MODE_PERIODIC
:
104 period
= clkev
.rate
/ HZ
;
106 /* Looks like we need to first set the load value separately */
107 __omap_dm_timer_write(&clkev
, OMAP_TIMER_LOAD_REG
,
108 0xffffffff - period
, OMAP_TIMER_POSTED
);
109 __omap_dm_timer_load_start(&clkev
,
110 OMAP_TIMER_CTRL_AR
| OMAP_TIMER_CTRL_ST
,
111 0xffffffff - period
, OMAP_TIMER_POSTED
);
113 case CLOCK_EVT_MODE_ONESHOT
:
115 case CLOCK_EVT_MODE_UNUSED
:
116 case CLOCK_EVT_MODE_SHUTDOWN
:
117 case CLOCK_EVT_MODE_RESUME
:
122 static struct clock_event_device clockevent_gpt
= {
123 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
125 .set_next_event
= omap2_gp_timer_set_next_event
,
126 .set_mode
= omap2_gp_timer_set_mode
,
129 static struct property device_disabled
= {
131 .length
= sizeof("disabled"),
135 static struct of_device_id omap_timer_match
[] __initdata
= {
136 { .compatible
= "ti,omap2-timer", },
141 * omap_get_timer_dt - get a timer using device-tree
142 * @match - device-tree match structure for matching a device type
143 * @property - optional timer property to match
145 * Helper function to get a timer during early boot using device-tree for use
146 * as kernel system timer. Optionally, the property argument can be used to
147 * select a timer with a specific property. Once a timer is found then mark
148 * the timer node in device-tree as disabled, to prevent the kernel from
149 * registering this timer as a platform device and so no one else can use it.
151 static struct device_node
* __init
omap_get_timer_dt(struct of_device_id
*match
,
152 const char *property
)
154 struct device_node
*np
;
156 for_each_matching_node(np
, match
) {
157 if (!of_device_is_available(np
))
160 if (property
&& !of_get_property(np
, property
, NULL
))
163 if (!property
&& (of_get_property(np
, "ti,timer-alwon", NULL
) ||
164 of_get_property(np
, "ti,timer-dsp", NULL
) ||
165 of_get_property(np
, "ti,timer-pwm", NULL
) ||
166 of_get_property(np
, "ti,timer-secure", NULL
)))
169 of_add_property(np
, &device_disabled
);
177 * omap_dmtimer_init - initialisation function when device tree is used
179 * For secure OMAP3 devices, timers with device type "timer-secure" cannot
180 * be used by the kernel as they are reserved. Therefore, to prevent the
181 * kernel registering these devices remove them dynamically from the device
184 static void __init
omap_dmtimer_init(void)
186 struct device_node
*np
;
188 if (!cpu_is_omap34xx())
191 /* If we are a secure device, remove any secure timer nodes */
192 if ((omap_type() != OMAP2_DEVICE_TYPE_GP
)) {
193 np
= omap_get_timer_dt(omap_timer_match
, "ti,timer-secure");
200 * omap_dm_timer_get_errata - get errata flags for a timer
202 * Get the timer errata flags that are specific to the OMAP device being used.
204 static u32 __init
omap_dm_timer_get_errata(void)
206 if (cpu_is_omap24xx())
209 return OMAP_TIMER_ERRATA_I103_I767
;
212 static int __init
omap_dm_timer_init_one(struct omap_dm_timer
*timer
,
213 const char *fck_source
,
214 const char *property
,
215 const char **timer_name
,
218 char name
[10]; /* 10 = sizeof("gptXX_Xck0") */
220 struct device_node
*np
;
221 struct omap_hwmod
*oh
;
222 struct resource irq
, mem
;
226 if (of_have_populated_dt()) {
227 np
= omap_get_timer_dt(omap_timer_match
, property
);
231 of_property_read_string_index(np
, "ti,hwmods", 0, &oh_name
);
235 timer
->irq
= irq_of_parse_and_map(np
, 0);
239 timer
->io_base
= of_iomap(np
, 0);
243 if (omap_dm_timer_reserve_systimer(timer
->id
))
246 sprintf(name
, "timer%d", timer
->id
);
250 oh
= omap_hwmod_lookup(oh_name
);
254 *timer_name
= oh
->name
;
256 if (!of_have_populated_dt()) {
257 r
= omap_hwmod_get_resource_byname(oh
, IORESOURCE_IRQ
, NULL
,
261 timer
->irq
= irq
.start
;
263 r
= omap_hwmod_get_resource_byname(oh
, IORESOURCE_MEM
, NULL
,
268 /* Static mapping, never released */
269 timer
->io_base
= ioremap(mem
.start
, mem
.end
- mem
.start
);
275 /* After the dmtimer is using hwmod these clocks won't be needed */
276 timer
->fclk
= clk_get(NULL
, omap_hwmod_get_main_clk(oh
));
277 if (IS_ERR(timer
->fclk
))
278 return PTR_ERR(timer
->fclk
);
280 src
= clk_get(NULL
, fck_source
);
284 if (clk_get_parent(timer
->fclk
) != src
) {
285 r
= clk_set_parent(timer
->fclk
, src
);
287 pr_warn("%s: %s cannot set source\n", __func__
,
296 omap_hwmod_setup_one(oh_name
);
297 omap_hwmod_enable(oh
);
298 __omap_dm_timer_init_regs(timer
);
301 __omap_dm_timer_enable_posted(timer
);
303 /* Check that the intended posted configuration matches the actual */
304 if (posted
!= timer
->posted
)
307 timer
->rate
= clk_get_rate(timer
->fclk
);
313 static void __init
omap2_gp_clockevent_init(int gptimer_id
,
314 const char *fck_source
,
315 const char *property
)
319 clkev
.id
= gptimer_id
;
320 clkev
.errata
= omap_dm_timer_get_errata();
323 * For clock-event timers we never read the timer counter and
324 * so we are not impacted by errata i103 and i767. Therefore,
325 * we can safely ignore this errata for clock-event timers.
327 __omap_dm_timer_override_errata(&clkev
, OMAP_TIMER_ERRATA_I103_I767
);
329 res
= omap_dm_timer_init_one(&clkev
, fck_source
, property
,
330 &clockevent_gpt
.name
, OMAP_TIMER_POSTED
);
333 omap2_gp_timer_irq
.dev_id
= &clkev
;
334 setup_irq(clkev
.irq
, &omap2_gp_timer_irq
);
336 __omap_dm_timer_int_enable(&clkev
, OMAP_TIMER_INT_OVERFLOW
);
338 clockevent_gpt
.cpumask
= cpu_possible_mask
;
339 clockevent_gpt
.irq
= omap_dm_timer_get_irq(&clkev
);
340 clockevents_config_and_register(&clockevent_gpt
, clkev
.rate
,
341 3, /* Timer internal resynch latency */
344 pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt
.name
,
348 /* Clocksource code */
349 static struct omap_dm_timer clksrc
;
350 static bool use_gptimer_clksrc
;
355 static cycle_t
clocksource_read_cycles(struct clocksource
*cs
)
357 return (cycle_t
)__omap_dm_timer_read_counter(&clksrc
,
358 OMAP_TIMER_NONPOSTED
);
361 static struct clocksource clocksource_gpt
= {
363 .read
= clocksource_read_cycles
,
364 .mask
= CLOCKSOURCE_MASK(32),
365 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
368 static u32 notrace
dmtimer_read_sched_clock(void)
371 return __omap_dm_timer_read_counter(&clksrc
,
372 OMAP_TIMER_NONPOSTED
);
377 static struct of_device_id omap_counter_match
[] __initdata
= {
378 { .compatible
= "ti,omap-counter32k", },
382 /* Setup free-running counter for clocksource */
383 static int __init __maybe_unused
omap2_sync32k_clocksource_init(void)
386 struct device_node
*np
= NULL
;
387 struct omap_hwmod
*oh
;
389 const char *oh_name
= "counter_32k";
392 * If device-tree is present, then search the DT blob
393 * to see if the 32kHz counter is supported.
395 if (of_have_populated_dt()) {
396 np
= omap_get_timer_dt(omap_counter_match
, NULL
);
400 of_property_read_string_index(np
, "ti,hwmods", 0, &oh_name
);
406 * First check hwmod data is available for sync32k counter
408 oh
= omap_hwmod_lookup(oh_name
);
409 if (!oh
|| oh
->slaves_cnt
== 0)
412 omap_hwmod_setup_one(oh_name
);
415 vbase
= of_iomap(np
, 0);
418 vbase
= omap_hwmod_get_mpu_rt_va(oh
);
422 pr_warn("%s: failed to get counter_32k resource\n", __func__
);
426 ret
= omap_hwmod_enable(oh
);
428 pr_warn("%s: failed to enable counter_32k module (%d)\n",
433 ret
= omap_init_clocksource_32k(vbase
);
435 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
443 static void __init
omap2_gptimer_clocksource_init(int gptimer_id
,
444 const char *fck_source
,
445 const char *property
)
449 clksrc
.id
= gptimer_id
;
450 clksrc
.errata
= omap_dm_timer_get_errata();
452 res
= omap_dm_timer_init_one(&clksrc
, fck_source
, property
,
453 &clocksource_gpt
.name
,
454 OMAP_TIMER_NONPOSTED
);
457 __omap_dm_timer_load_start(&clksrc
,
458 OMAP_TIMER_CTRL_ST
| OMAP_TIMER_CTRL_AR
, 0,
459 OMAP_TIMER_NONPOSTED
);
460 setup_sched_clock(dmtimer_read_sched_clock
, 32, clksrc
.rate
);
462 if (clocksource_register_hz(&clocksource_gpt
, clksrc
.rate
))
463 pr_err("Could not register clocksource %s\n",
464 clocksource_gpt
.name
);
466 pr_info("OMAP clocksource: %s at %lu Hz\n",
467 clocksource_gpt
.name
, clksrc
.rate
);
470 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
472 * The realtime counter also called master counter, is a free-running
473 * counter, which is related to real time. It produces the count used
474 * by the CPU local timer peripherals in the MPU cluster. The timer counts
475 * at a rate of 6.144 MHz. Because the device operates on different clocks
476 * in different power modes, the master counter shifts operation between
477 * clocks, adjusting the increment per clock in hardware accordingly to
478 * maintain a constant count rate.
480 static void __init
realtime_counter_init(void)
483 static struct clk
*sys_clk
;
485 unsigned int reg
, num
, den
;
487 base
= ioremap(REALTIME_COUNTER_BASE
, SZ_32
);
489 pr_err("%s: ioremap failed\n", __func__
);
492 sys_clk
= clk_get(NULL
, "sys_clkin");
493 if (IS_ERR(sys_clk
)) {
494 pr_err("%s: failed to get system clock handle\n", __func__
);
499 rate
= clk_get_rate(sys_clk
);
500 /* Numerator/denumerator values refer TRM Realtime Counter section */
524 /* Program it for 38.4 MHz */
530 /* Program numerator and denumerator registers */
531 reg
= __raw_readl(base
+ INCREMENTER_NUMERATOR_OFFSET
) &
532 NUMERATOR_DENUMERATOR_MASK
;
534 __raw_writel(reg
, base
+ INCREMENTER_NUMERATOR_OFFSET
);
536 reg
= __raw_readl(base
+ INCREMENTER_NUMERATOR_OFFSET
) &
537 NUMERATOR_DENUMERATOR_MASK
;
539 __raw_writel(reg
, base
+ INCREMENTER_DENUMERATOR_RELOAD_OFFSET
);
544 static inline void __init
realtime_counter_init(void)
548 #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
549 clksrc_nr, clksrc_src, clksrc_prop) \
550 void __init omap##name##_gptimer_timer_init(void) \
552 omap_dmtimer_init(); \
553 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
554 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \
558 #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
559 clksrc_nr, clksrc_src, clksrc_prop) \
560 void __init omap##name##_sync32k_timer_init(void) \
562 omap_dmtimer_init(); \
563 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
564 /* Enable the use of clocksource="gp_timer" kernel parameter */ \
565 if (use_gptimer_clksrc) \
566 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \
569 omap2_sync32k_clocksource_init(); \
572 #ifdef CONFIG_ARCH_OMAP2
573 OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon",
574 2, "timer_sys_ck", NULL
);
575 #endif /* CONFIG_ARCH_OMAP2 */
577 #ifdef CONFIG_ARCH_OMAP3
578 OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon",
579 2, "timer_sys_ck", NULL
);
580 OMAP_SYS_32K_TIMER_INIT(3_secure
, 12, "secure_32k_fck", "ti,timer-secure",
581 2, "timer_sys_ck", NULL
);
582 #endif /* CONFIG_ARCH_OMAP3 */
584 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
585 OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL
,
586 1, "timer_sys_ck", "ti,timer-alwon");
589 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
590 static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
591 2, "sys_clkin_ck", NULL
);
594 #ifdef CONFIG_ARCH_OMAP4
595 #ifdef CONFIG_LOCAL_TIMERS
596 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer
, OMAP44XX_LOCAL_TWD_BASE
, 29);
597 void __init
omap4_local_timer_init(void)
599 omap4_sync32k_timer_init();
600 /* Local timers are not supprted on OMAP4430 ES1.0 */
601 if (omap_rev() != OMAP4430_REV_ES1_0
) {
604 if (of_have_populated_dt()) {
605 clocksource_of_init();
609 err
= twd_local_timer_register(&twd_local_timer
);
611 pr_err("twd_local_timer_register failed %d\n", err
);
614 #else /* CONFIG_LOCAL_TIMERS */
615 void __init
omap4_local_timer_init(void)
617 omap4_sync32k_timer_init();
619 #endif /* CONFIG_LOCAL_TIMERS */
620 #endif /* CONFIG_ARCH_OMAP4 */
622 #ifdef CONFIG_SOC_OMAP5
623 void __init
omap5_realtime_timer_init(void)
627 omap4_sync32k_timer_init();
628 realtime_counter_init();
630 err
= arch_timer_of_register();
632 pr_err("%s: arch_timer_register failed %d\n", __func__
, err
);
634 #endif /* CONFIG_SOC_OMAP5 */
637 * omap_timer_init - build and register timer device with an
638 * associated timer hwmod
639 * @oh: timer hwmod pointer to be used to build timer device
640 * @user: parameter that can be passed from calling hwmod API
642 * Called by omap_hwmod_for_each_by_class to register each of the timer
643 * devices present in the system. The number of timer devices is known
644 * by parsing through the hwmod database for a given class name. At the
645 * end of function call memory is allocated for timer device and it is
646 * registered to the framework ready to be proved by the driver.
648 static int __init
omap_timer_init(struct omap_hwmod
*oh
, void *unused
)
652 char *name
= "omap_timer";
653 struct dmtimer_platform_data
*pdata
;
654 struct platform_device
*pdev
;
655 struct omap_timer_capability_dev_attr
*timer_dev_attr
;
657 pr_debug("%s: %s\n", __func__
, oh
->name
);
659 /* on secure device, do not register secure timer */
660 timer_dev_attr
= oh
->dev_attr
;
661 if (omap_type() != OMAP2_DEVICE_TYPE_GP
&& timer_dev_attr
)
662 if (timer_dev_attr
->timer_capability
== OMAP_TIMER_SECURE
)
665 pdata
= kzalloc(sizeof(*pdata
), GFP_KERNEL
);
667 pr_err("%s: No memory for [%s]\n", __func__
, oh
->name
);
672 * Extract the IDs from name field in hwmod database
673 * and use the same for constructing ids' for the
674 * timer devices. In a way, we are avoiding usage of
675 * static variable witin the function to do the same.
676 * CAUTION: We have to be careful and make sure the
677 * name in hwmod database does not change in which case
678 * we might either make corresponding change here or
679 * switch back static variable mechanism.
681 sscanf(oh
->name
, "timer%2d", &id
);
684 pdata
->timer_capability
= timer_dev_attr
->timer_capability
;
686 pdata
->timer_errata
= omap_dm_timer_get_errata();
687 pdata
->get_context_loss_count
= omap_pm_get_dev_context_loss_count
;
689 pdev
= omap_device_build(name
, id
, oh
, pdata
, sizeof(*pdata
));
692 pr_err("%s: Can't build omap_device for %s: %s.\n",
693 __func__
, name
, oh
->name
);
703 * omap2_dm_timer_init - top level regular device initialization
705 * Uses dedicated hwmod api to parse through hwmod database for
706 * given class name and then build and register the timer device.
708 static int __init
omap2_dm_timer_init(void)
712 /* If dtb is there, the devices will be created dynamically */
713 if (of_have_populated_dt())
716 ret
= omap_hwmod_for_each_by_class("timer", omap_timer_init
, NULL
);
718 pr_err("%s: device registration failed.\n", __func__
);
724 omap_arch_initcall(omap2_dm_timer_init
);
727 * omap2_override_clocksource - clocksource override with user configuration
729 * Allows user to override default clocksource, using kernel parameter
730 * clocksource="gp_timer" (For all OMAP2PLUS architectures)
732 * Note that, here we are using same standard kernel parameter "clocksource=",
733 * and not introducing any OMAP specific interface.
735 static int __init
omap2_override_clocksource(char *str
)
740 * For OMAP architecture, we only have two options
741 * - sync_32k (default)
742 * - gp_timer (sys_clk based)
744 if (!strcmp(str
, "gp_timer"))
745 use_gptimer_clksrc
= true;
749 early_param("clocksource", omap2_override_clocksource
);