arch/arm/mach-omap2/pm24xx.c

   1 /*
   2  * OMAP2 Power Management Routines
   3  *
   4  * Copyright (C) 2005 Texas Instruments, Inc.
   5  * Copyright (C) 2006-2008 Nokia Corporation
   6  *
   7  * Written by:
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Tony Lindgren
  10  * Juha Yrjola
  11  * Amit Kucheria <amit.kucheria@nokia.com>
  12  * Igor Stoppa <igor.stoppa@nokia.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/suspend.h>
  22 #include <linux/sched.h>
  23 #include <linux/proc_fs.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysfs.h>
  26 #include <linux/module.h>
  27 #include <linux/delay.h>
  28 #include <linux/clk-provider.h>
  29 #include <linux/irq.h>
  30 #include <linux/time.h>
  31 #include <linux/gpio.h>
  32 #include <linux/platform_data/gpio-omap.h>
  33
  34 #include <asm/fncpy.h>
  35
  36 #include <asm/mach/time.h>
  37 #include <asm/mach/irq.h>
  38 #include <asm/mach-types.h>
  39 #include <asm/system_misc.h>
  40
  41 #include <linux/omap-dma.h>
  42
  43 #include "soc.h"
  44 #include "common.h"
  45 #include "clock.h"
  46 #include "prm2xxx.h"
  47 #include "prm-regbits-24xx.h"
  48 #include "cm2xxx.h"
  49 #include "cm-regbits-24xx.h"
  50 #include "sdrc.h"
  51 #include "sram.h"
  52 #include "pm.h"
  53 #include "control.h"
  54 #include "powerdomain.h"
  55 #include "clockdomain.h"
  56
  57 static void (*omap2_sram_idle)(void);
  58 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
  59                                   void __iomem *sdrc_power);
  60
  61 static struct powerdomain *mpu_pwrdm, *core_pwrdm;
  62 static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
  63
  64 static struct clk *osc_ck, *emul_ck;
  65
  66 static int omap2_fclks_active(void)
  67 {
  68         u32 f1, f2;
  69
  70         f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  71         f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  72
  73         return (f1 | f2) ? 1 : 0;
  74 }
  75
  76 static int omap2_enter_full_retention(void)
  77 {
  78         u32 l;
  79
  80         /* There is 1 reference hold for all children of the oscillator
  81          * clock, the following will remove it. If no one else uses the
  82          * oscillator itself it will be disabled if/when we enter retention
  83          * mode.
  84          */
  85         clk_disable(osc_ck);
  86
  87         /* Clear old wake-up events */
  88         /* REVISIT: These write to reserved bits? */
  89         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
  90         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
  91         omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
  92
  93         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
  94         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
  95
  96         /* Workaround to kill USB */
  97         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
  98         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
  99
 100         omap2_gpio_prepare_for_idle(0);
 101
 102         /* One last check for pending IRQs to avoid extra latency due
 103          * to sleeping unnecessarily. */
 104         if (omap_irq_pending())
 105                 goto no_sleep;
 106
 107         /* Jump to SRAM suspend code */
 108         omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
 109                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
 110                            OMAP_SDRC_REGADDR(SDRC_POWER));
 111
 112 no_sleep:
 113         omap2_gpio_resume_after_idle();
 114
 115         clk_enable(osc_ck);
 116
 117         /* clear CORE wake-up events */
 118         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 119         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 120
 121         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 122         omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 123
 124         /* MPU domain wake events */
 125         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 126         if (l & 0x01)
 127                 omap2_prm_write_mod_reg(0x01, OCP_MOD,
 128                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 129         if (l & 0x20)
 130                 omap2_prm_write_mod_reg(0x20, OCP_MOD,
 131                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 132
 133         /* Mask future PRCM-to-MPU interrupts */
 134         omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 135
 136         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 137         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
 138
 139         return 0;
 140 }
 141
 142 static int sti_console_enabled;
 143
 144 static int omap2_allow_mpu_retention(void)
 145 {
 146         u32 l;
 147
 148         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 149         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 150         if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
 151                  OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
 152                  OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
 153                 return 0;
 154         /* Check for UART3. */
 155         l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 156         if (l & OMAP24XX_EN_UART3_MASK)
 157                 return 0;
 158         if (sti_console_enabled)
 159                 return 0;
 160
 161         return 1;
 162 }
 163
 164 static void omap2_enter_mpu_retention(void)
 165 {
 166         /* The peripherals seem not to be able to wake up the MPU when
 167          * it is in retention mode. */
 168         if (omap2_allow_mpu_retention()) {
 169                 /* REVISIT: These write to reserved bits? */
 170                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 171                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 172                 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 173
 174                 /* Try to enter MPU retention */
 175                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 176
 177         } else {
 178                 /* Block MPU retention */
 179                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 180         }
 181
 182         omap2_sram_idle();
 183
 184         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 185 }
 186
 187 static int omap2_can_sleep(void)
 188 {
 189         if (omap2_fclks_active())
 190                 return 0;
 191         if (__clk_is_enabled(osc_ck))
 192                 return 0;
 193         if (omap_dma_running())
 194                 return 0;
 195
 196         return 1;
 197 }
 198
 199 static void omap2_pm_idle(void)
 200 {
 201         local_fiq_disable();
 202
 203         if (!omap2_can_sleep()) {
 204                 if (omap_irq_pending())
 205                         goto out;
 206                 omap2_enter_mpu_retention();
 207                 goto out;
 208         }
 209
 210         if (omap_irq_pending())
 211                 goto out;
 212
 213         omap2_enter_full_retention();
 214
 215 out:
 216         local_fiq_enable();
 217 }
 218
 219 static void __init prcm_setup_regs(void)
 220 {
 221         int i, num_mem_banks;
 222         struct powerdomain *pwrdm;
 223
 224         /*
 225          * Enable autoidle
 226          * XXX This should be handled by hwmod code or PRCM init code
 227          */
 228         omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
 229                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 230
 231         /*
 232          * Set CORE powerdomain memory banks to retain their contents
 233          * during RETENTION
 234          */
 235         num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
 236         for (i = 0; i < num_mem_banks; i++)
 237                 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
 238
 239         pwrdm_set_logic_retst(core_pwrdm, PWRDM_POWER_RET);
 240
 241         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 242
 243         /* Force-power down DSP, GFX powerdomains */
 244
 245         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
 246         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 247
 248         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
 249         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 250
 251         /* Enable hardware-supervised idle for all clkdms */
 252         clkdm_for_each(omap_pm_clkdms_setup, NULL);
 253         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 254
 255 #ifdef CONFIG_SUSPEND
 256         omap_pm_suspend = omap2_enter_full_retention;
 257 #endif
 258
 259         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 260          * stabilisation */
 261         omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 262                                 OMAP2_PRCM_CLKSSETUP_OFFSET);
 263
 264         /* Configure automatic voltage transition */
 265         omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 266                                 OMAP2_PRCM_VOLTSETUP_OFFSET);
 267         omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
 268                                 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 269                                 OMAP24XX_MEMRETCTRL_MASK |
 270                                 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 271                                 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 272                                 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
 273
 274         /* Enable wake-up events */
 275         omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
 276                                 WKUP_MOD, PM_WKEN);
 277 }
 278
 279 int __init omap2_pm_init(void)
 280 {
 281         u32 l;
 282
 283         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 284         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
 285         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 286
 287         /* Look up important powerdomains */
 288
 289         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 290         if (!mpu_pwrdm)
 291                 pr_err("PM: mpu_pwrdm not found\n");
 292
 293         core_pwrdm = pwrdm_lookup("core_pwrdm");
 294         if (!core_pwrdm)
 295                 pr_err("PM: core_pwrdm not found\n");
 296
 297         /* Look up important clockdomains */
 298
 299         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 300         if (!mpu_clkdm)
 301                 pr_err("PM: mpu_clkdm not found\n");
 302
 303         wkup_clkdm = clkdm_lookup("wkup_clkdm");
 304         if (!wkup_clkdm)
 305                 pr_err("PM: wkup_clkdm not found\n");
 306
 307         dsp_clkdm = clkdm_lookup("dsp_clkdm");
 308         if (!dsp_clkdm)
 309                 pr_err("PM: dsp_clkdm not found\n");
 310
 311         gfx_clkdm = clkdm_lookup("gfx_clkdm");
 312         if (!gfx_clkdm)
 313                 pr_err("PM: gfx_clkdm not found\n");
 314
 315
 316         osc_ck = clk_get(NULL, "osc_ck");
 317         if (IS_ERR(osc_ck)) {
 318                 printk(KERN_ERR "could not get osc_ck\n");
 319                 return -ENODEV;
 320         }
 321
 322         if (cpu_is_omap242x()) {
 323                 emul_ck = clk_get(NULL, "emul_ck");
 324                 if (IS_ERR(emul_ck)) {
 325                         printk(KERN_ERR "could not get emul_ck\n");
 326                         clk_put(osc_ck);
 327                         return -ENODEV;
 328                 }
 329         }
 330
 331         prcm_setup_regs();
 332
 333         /*
 334          * We copy the assembler sleep/wakeup routines to SRAM.
 335          * These routines need to be in SRAM as that's the only
 336          * memory the MPU can see when it wakes up.
 337          */
 338         omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 339                                          omap24xx_idle_loop_suspend_sz);
 340
 341         omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 342                                             omap24xx_cpu_suspend_sz);
 343
 344         arm_pm_idle = omap2_pm_idle;
 345
 346         return 0;
 347 }