arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

   1 /*
   2  * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
   3  *
   4  * Copyright (C) 2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/platform_data/gpio-omap.h>
  13 #include <linux/omap-dma.h>
  14 #include <plat/dmtimer.h>
  15 #include <linux/platform_data/spi-omap2-mcspi.h>
  16
  17 #include "omap_hwmod.h"
  18 #include "omap_hwmod_common_data.h"
  19 #include "cm-regbits-24xx.h"
  20 #include "prm-regbits-24xx.h"
  21 #include "wd_timer.h"
  22
  23 struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
  24         { .irq = 48 + OMAP_INTC_START, },
  25         { .irq = -1 },
  26 };
  27
  28 struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
  29         { .name = "dispc", .dma_req = 5 },
  30         { .dma_req = -1 }
  31 };
  32
  33 /*
  34  * 'dispc' class
  35  * display controller
  36  */
  37
  38 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
  39         .rev_offs       = 0x0000,
  40         .sysc_offs      = 0x0010,
  41         .syss_offs      = 0x0014,
  42         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
  43                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  44         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  45                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  46         .sysc_fields    = &omap_hwmod_sysc_type1,
  47 };
  48
  49 struct omap_hwmod_class omap2_dispc_hwmod_class = {
  50         .name   = "dispc",
  51         .sysc   = &omap2_dispc_sysc,
  52 };
  53
  54 /* OMAP2xxx Timer Common */
  55 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
  56         .rev_offs       = 0x0000,
  57         .sysc_offs      = 0x0010,
  58         .syss_offs      = 0x0014,
  59         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
  60                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  61                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  62         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  63         .clockact       = CLOCKACT_TEST_ICLK,
  64         .sysc_fields    = &omap_hwmod_sysc_type1,
  65 };
  66
  67 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
  68         .name   = "timer",
  69         .sysc   = &omap2xxx_timer_sysc,
  70 };
  71
  72 /*
  73  * 'wd_timer' class
  74  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  75  * overflow condition
  76  */
  77
  78 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
  79         .rev_offs       = 0x0000,
  80         .sysc_offs      = 0x0010,
  81         .syss_offs      = 0x0014,
  82         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
  83                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  84         .sysc_fields    = &omap_hwmod_sysc_type1,
  85 };
  86
  87 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
  88         .name           = "wd_timer",
  89         .sysc           = &omap2xxx_wd_timer_sysc,
  90         .pre_shutdown   = &omap2_wd_timer_disable,
  91         .reset          = &omap2_wd_timer_reset,
  92 };
  93
  94 /*
  95  * 'gpio' class
  96  * general purpose io module
  97  */
  98 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
  99         .rev_offs       = 0x0000,
 100         .sysc_offs      = 0x0010,
 101         .syss_offs      = 0x0014,
 102         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 103                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 104                            SYSS_HAS_RESET_STATUS),
 105         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 106         .sysc_fields    = &omap_hwmod_sysc_type1,
 107 };
 108
 109 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
 110         .name = "gpio",
 111         .sysc = &omap2xxx_gpio_sysc,
 112         .rev = 0,
 113 };
 114
 115 /* system dma */
 116 static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
 117         .rev_offs       = 0x0000,
 118         .sysc_offs      = 0x002c,
 119         .syss_offs      = 0x0028,
 120         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
 121                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
 122                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 123         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 124         .sysc_fields    = &omap_hwmod_sysc_type1,
 125 };
 126
 127 struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
 128         .name   = "dma",
 129         .sysc   = &omap2xxx_dma_sysc,
 130 };
 131
 132 /*
 133  * 'mailbox' class
 134  * mailbox module allowing communication between the on-chip processors
 135  * using a queued mailbox-interrupt mechanism.
 136  */
 137
 138 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
 139         .rev_offs       = 0x000,
 140         .sysc_offs      = 0x010,
 141         .syss_offs      = 0x014,
 142         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 143                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 144         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 145         .sysc_fields    = &omap_hwmod_sysc_type1,
 146 };
 147
 148 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
 149         .name   = "mailbox",
 150         .sysc   = &omap2xxx_mailbox_sysc,
 151 };
 152
 153 /*
 154  * 'mcspi' class
 155  * multichannel serial port interface (mcspi) / master/slave synchronous serial
 156  * bus
 157  */
 158
 159 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
 160         .rev_offs       = 0x0000,
 161         .sysc_offs      = 0x0010,
 162         .syss_offs      = 0x0014,
 163         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 164                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 165                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 166         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 167         .sysc_fields    = &omap_hwmod_sysc_type1,
 168 };
 169
 170 struct omap_hwmod_class omap2xxx_mcspi_class = {
 171         .name   = "mcspi",
 172         .sysc   = &omap2xxx_mcspi_sysc,
 173         .rev    = OMAP2_MCSPI_REV,
 174 };
 175
 176 /*
 177  * 'gpmc' class
 178  * general purpose memory controller
 179  */
 180
 181 static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
 182         .rev_offs       = 0x0000,
 183         .sysc_offs      = 0x0010,
 184         .syss_offs      = 0x0014,
 185         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 186                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 187         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 188         .sysc_fields    = &omap_hwmod_sysc_type1,
 189 };
 190
 191 static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
 192         .name   = "gpmc",
 193         .sysc   = &omap2xxx_gpmc_sysc,
 194 };
 195
 196 /*
 197  * IP blocks
 198  */
 199
 200 /* L3 */
 201 struct omap_hwmod omap2xxx_l3_main_hwmod = {
 202         .name           = "l3_main",
 203         .class          = &l3_hwmod_class,
 204         .flags          = HWMOD_NO_IDLEST,
 205 };
 206
 207 /* L4 CORE */
 208 struct omap_hwmod omap2xxx_l4_core_hwmod = {
 209         .name           = "l4_core",
 210         .class          = &l4_hwmod_class,
 211         .flags          = HWMOD_NO_IDLEST,
 212 };
 213
 214 /* L4 WKUP */
 215 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
 216         .name           = "l4_wkup",
 217         .class          = &l4_hwmod_class,
 218         .flags          = HWMOD_NO_IDLEST,
 219 };
 220
 221 /* MPU */
 222 static struct omap_hwmod_irq_info omap2xxx_mpu_irqs[] = {
 223         { .name = "pmu", .irq = 3 + OMAP_INTC_START },
 224         { .irq = -1 }
 225 };
 226
 227 struct omap_hwmod omap2xxx_mpu_hwmod = {
 228         .name           = "mpu",
 229         .mpu_irqs       = omap2xxx_mpu_irqs,
 230         .class          = &mpu_hwmod_class,
 231         .main_clk       = "mpu_ck",
 232 };
 233
 234 /* IVA2 */
 235 struct omap_hwmod omap2xxx_iva_hwmod = {
 236         .name           = "iva",
 237         .class          = &iva_hwmod_class,
 238 };
 239
 240 /* always-on timers dev attribute */
 241 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 242         .timer_capability       = OMAP_TIMER_ALWON,
 243 };
 244
 245 /* pwm timers dev attribute */
 246 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 247         .timer_capability       = OMAP_TIMER_HAS_PWM,
 248 };
 249
 250 /* timers with DSP interrupt dev attribute */
 251 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
 252         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
 253 };
 254
 255 /* timer1 */
 256
 257 struct omap_hwmod omap2xxx_timer1_hwmod = {
 258         .name           = "timer1",
 259         .mpu_irqs       = omap2_timer1_mpu_irqs,
 260         .main_clk       = "gpt1_fck",
 261         .prcm           = {
 262                 .omap2 = {
 263                         .prcm_reg_id = 1,
 264                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 265                         .module_offs = WKUP_MOD,
 266                         .idlest_reg_id = 1,
 267                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 268                 },
 269         },
 270         .dev_attr       = &capability_alwon_dev_attr,
 271         .class          = &omap2xxx_timer_hwmod_class,
 272         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 273 };
 274
 275 /* timer2 */
 276
 277 struct omap_hwmod omap2xxx_timer2_hwmod = {
 278         .name           = "timer2",
 279         .mpu_irqs       = omap2_timer2_mpu_irqs,
 280         .main_clk       = "gpt2_fck",
 281         .prcm           = {
 282                 .omap2 = {
 283                         .prcm_reg_id = 1,
 284                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 285                         .module_offs = CORE_MOD,
 286                         .idlest_reg_id = 1,
 287                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 288                 },
 289         },
 290         .class          = &omap2xxx_timer_hwmod_class,
 291         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 292 };
 293
 294 /* timer3 */
 295
 296 struct omap_hwmod omap2xxx_timer3_hwmod = {
 297         .name           = "timer3",
 298         .mpu_irqs       = omap2_timer3_mpu_irqs,
 299         .main_clk       = "gpt3_fck",
 300         .prcm           = {
 301                 .omap2 = {
 302                         .prcm_reg_id = 1,
 303                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 304                         .module_offs = CORE_MOD,
 305                         .idlest_reg_id = 1,
 306                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 307                 },
 308         },
 309         .class          = &omap2xxx_timer_hwmod_class,
 310         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 311 };
 312
 313 /* timer4 */
 314
 315 struct omap_hwmod omap2xxx_timer4_hwmod = {
 316         .name           = "timer4",
 317         .mpu_irqs       = omap2_timer4_mpu_irqs,
 318         .main_clk       = "gpt4_fck",
 319         .prcm           = {
 320                 .omap2 = {
 321                         .prcm_reg_id = 1,
 322                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 323                         .module_offs = CORE_MOD,
 324                         .idlest_reg_id = 1,
 325                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 326                 },
 327         },
 328         .class          = &omap2xxx_timer_hwmod_class,
 329         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 330 };
 331
 332 /* timer5 */
 333
 334 struct omap_hwmod omap2xxx_timer5_hwmod = {
 335         .name           = "timer5",
 336         .mpu_irqs       = omap2_timer5_mpu_irqs,
 337         .main_clk       = "gpt5_fck",
 338         .prcm           = {
 339                 .omap2 = {
 340                         .prcm_reg_id = 1,
 341                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 342                         .module_offs = CORE_MOD,
 343                         .idlest_reg_id = 1,
 344                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 345                 },
 346         },
 347         .dev_attr       = &capability_dsp_dev_attr,
 348         .class          = &omap2xxx_timer_hwmod_class,
 349         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 350 };
 351
 352 /* timer6 */
 353
 354 struct omap_hwmod omap2xxx_timer6_hwmod = {
 355         .name           = "timer6",
 356         .mpu_irqs       = omap2_timer6_mpu_irqs,
 357         .main_clk       = "gpt6_fck",
 358         .prcm           = {
 359                 .omap2 = {
 360                         .prcm_reg_id = 1,
 361                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 362                         .module_offs = CORE_MOD,
 363                         .idlest_reg_id = 1,
 364                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 365                 },
 366         },
 367         .dev_attr       = &capability_dsp_dev_attr,
 368         .class          = &omap2xxx_timer_hwmod_class,
 369         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 370 };
 371
 372 /* timer7 */
 373
 374 struct omap_hwmod omap2xxx_timer7_hwmod = {
 375         .name           = "timer7",
 376         .mpu_irqs       = omap2_timer7_mpu_irqs,
 377         .main_clk       = "gpt7_fck",
 378         .prcm           = {
 379                 .omap2 = {
 380                         .prcm_reg_id = 1,
 381                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 382                         .module_offs = CORE_MOD,
 383                         .idlest_reg_id = 1,
 384                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 385                 },
 386         },
 387         .dev_attr       = &capability_dsp_dev_attr,
 388         .class          = &omap2xxx_timer_hwmod_class,
 389         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 390 };
 391
 392 /* timer8 */
 393
 394 struct omap_hwmod omap2xxx_timer8_hwmod = {
 395         .name           = "timer8",
 396         .mpu_irqs       = omap2_timer8_mpu_irqs,
 397         .main_clk       = "gpt8_fck",
 398         .prcm           = {
 399                 .omap2 = {
 400                         .prcm_reg_id = 1,
 401                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 402                         .module_offs = CORE_MOD,
 403                         .idlest_reg_id = 1,
 404                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 405                 },
 406         },
 407         .dev_attr       = &capability_dsp_dev_attr,
 408         .class          = &omap2xxx_timer_hwmod_class,
 409         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 410 };
 411
 412 /* timer9 */
 413
 414 struct omap_hwmod omap2xxx_timer9_hwmod = {
 415         .name           = "timer9",
 416         .mpu_irqs       = omap2_timer9_mpu_irqs,
 417         .main_clk       = "gpt9_fck",
 418         .prcm           = {
 419                 .omap2 = {
 420                         .prcm_reg_id = 1,
 421                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 422                         .module_offs = CORE_MOD,
 423                         .idlest_reg_id = 1,
 424                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 425                 },
 426         },
 427         .dev_attr       = &capability_pwm_dev_attr,
 428         .class          = &omap2xxx_timer_hwmod_class,
 429         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 430 };
 431
 432 /* timer10 */
 433
 434 struct omap_hwmod omap2xxx_timer10_hwmod = {
 435         .name           = "timer10",
 436         .mpu_irqs       = omap2_timer10_mpu_irqs,
 437         .main_clk       = "gpt10_fck",
 438         .prcm           = {
 439                 .omap2 = {
 440                         .prcm_reg_id = 1,
 441                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 442                         .module_offs = CORE_MOD,
 443                         .idlest_reg_id = 1,
 444                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 445                 },
 446         },
 447         .dev_attr       = &capability_pwm_dev_attr,
 448         .class          = &omap2xxx_timer_hwmod_class,
 449         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 450 };
 451
 452 /* timer11 */
 453
 454 struct omap_hwmod omap2xxx_timer11_hwmod = {
 455         .name           = "timer11",
 456         .mpu_irqs       = omap2_timer11_mpu_irqs,
 457         .main_clk       = "gpt11_fck",
 458         .prcm           = {
 459                 .omap2 = {
 460                         .prcm_reg_id = 1,
 461                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 462                         .module_offs = CORE_MOD,
 463                         .idlest_reg_id = 1,
 464                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 465                 },
 466         },
 467         .dev_attr       = &capability_pwm_dev_attr,
 468         .class          = &omap2xxx_timer_hwmod_class,
 469         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 470 };
 471
 472 /* timer12 */
 473
 474 struct omap_hwmod omap2xxx_timer12_hwmod = {
 475         .name           = "timer12",
 476         .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
 477         .main_clk       = "gpt12_fck",
 478         .prcm           = {
 479                 .omap2 = {
 480                         .prcm_reg_id = 1,
 481                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
 482                         .module_offs = CORE_MOD,
 483                         .idlest_reg_id = 1,
 484                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 485                 },
 486         },
 487         .dev_attr       = &capability_pwm_dev_attr,
 488         .class          = &omap2xxx_timer_hwmod_class,
 489         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 490 };
 491
 492 /* wd_timer2 */
 493 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
 494         .name           = "wd_timer2",
 495         .class          = &omap2xxx_wd_timer_hwmod_class,
 496         .main_clk       = "mpu_wdt_fck",
 497         .prcm           = {
 498                 .omap2 = {
 499                         .prcm_reg_id = 1,
 500                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 501                         .module_offs = WKUP_MOD,
 502                         .idlest_reg_id = 1,
 503                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 504                 },
 505         },
 506 };
 507
 508 /* UART1 */
 509
 510 struct omap_hwmod omap2xxx_uart1_hwmod = {
 511         .name           = "uart1",
 512         .mpu_irqs       = omap2_uart1_mpu_irqs,
 513         .sdma_reqs      = omap2_uart1_sdma_reqs,
 514         .main_clk       = "uart1_fck",
 515         .flags          = HWMOD_SWSUP_SIDLE_ACT,
 516         .prcm           = {
 517                 .omap2 = {
 518                         .module_offs = CORE_MOD,
 519                         .prcm_reg_id = 1,
 520                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
 521                         .idlest_reg_id = 1,
 522                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 523                 },
 524         },
 525         .class          = &omap2_uart_class,
 526 };
 527
 528 /* UART2 */
 529
 530 struct omap_hwmod omap2xxx_uart2_hwmod = {
 531         .name           = "uart2",
 532         .mpu_irqs       = omap2_uart2_mpu_irqs,
 533         .sdma_reqs      = omap2_uart2_sdma_reqs,
 534         .main_clk       = "uart2_fck",
 535         .flags          = HWMOD_SWSUP_SIDLE_ACT,
 536         .prcm           = {
 537                 .omap2 = {
 538                         .module_offs = CORE_MOD,
 539                         .prcm_reg_id = 1,
 540                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
 541                         .idlest_reg_id = 1,
 542                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 543                 },
 544         },
 545         .class          = &omap2_uart_class,
 546 };
 547
 548 /* UART3 */
 549
 550 struct omap_hwmod omap2xxx_uart3_hwmod = {
 551         .name           = "uart3",
 552         .mpu_irqs       = omap2_uart3_mpu_irqs,
 553         .sdma_reqs      = omap2_uart3_sdma_reqs,
 554         .main_clk       = "uart3_fck",
 555         .flags          = HWMOD_SWSUP_SIDLE_ACT,
 556         .prcm           = {
 557                 .omap2 = {
 558                         .module_offs = CORE_MOD,
 559                         .prcm_reg_id = 2,
 560                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
 561                         .idlest_reg_id = 2,
 562                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 563                 },
 564         },
 565         .class          = &omap2_uart_class,
 566 };
 567
 568 /* dss */
 569
 570 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 571         /*
 572          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 573          * driver does not use these clocks.
 574          */
 575         { .role = "tv_clk", .clk = "dss_54m_fck" },
 576         { .role = "sys_clk", .clk = "dss2_fck" },
 577 };
 578
 579 struct omap_hwmod omap2xxx_dss_core_hwmod = {
 580         .name           = "dss_core",
 581         .class          = &omap2_dss_hwmod_class,
 582         .main_clk       = "dss1_fck", /* instead of dss_fck */
 583         .sdma_reqs      = omap2xxx_dss_sdma_chs,
 584         .prcm           = {
 585                 .omap2 = {
 586                         .prcm_reg_id = 1,
 587                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 588                         .module_offs = CORE_MOD,
 589                         .idlest_reg_id = 1,
 590                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 591                 },
 592         },
 593         .opt_clks       = dss_opt_clks,
 594         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 595         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 596 };
 597
 598 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
 599         .name           = "dss_dispc",
 600         .class          = &omap2_dispc_hwmod_class,
 601         .mpu_irqs       = omap2_dispc_irqs,
 602         .main_clk       = "dss1_fck",
 603         .prcm           = {
 604                 .omap2 = {
 605                         .prcm_reg_id = 1,
 606                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 607                         .module_offs = CORE_MOD,
 608                         .idlest_reg_id = 1,
 609                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 610                 },
 611         },
 612         .flags          = HWMOD_NO_IDLEST,
 613         .dev_attr       = &omap2_3_dss_dispc_dev_attr
 614 };
 615
 616 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 617         { .role = "ick", .clk = "dss_ick" },
 618 };
 619
 620 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
 621         .name           = "dss_rfbi",
 622         .class          = &omap2_rfbi_hwmod_class,
 623         .main_clk       = "dss1_fck",
 624         .prcm           = {
 625                 .omap2 = {
 626                         .prcm_reg_id = 1,
 627                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 628                         .module_offs = CORE_MOD,
 629                 },
 630         },
 631         .opt_clks       = dss_rfbi_opt_clks,
 632         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 633         .flags          = HWMOD_NO_IDLEST,
 634 };
 635
 636 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
 637         .name           = "dss_venc",
 638         .class          = &omap2_venc_hwmod_class,
 639         .main_clk       = "dss_54m_fck",
 640         .prcm           = {
 641                 .omap2 = {
 642                         .prcm_reg_id = 1,
 643                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 644                         .module_offs = CORE_MOD,
 645                 },
 646         },
 647         .flags          = HWMOD_NO_IDLEST,
 648 };
 649
 650 /* gpio dev_attr */
 651 struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
 652         .bank_width = 32,
 653         .dbck_flag = false,
 654 };
 655
 656 /* gpio1 */
 657 struct omap_hwmod omap2xxx_gpio1_hwmod = {
 658         .name           = "gpio1",
 659         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 660         .mpu_irqs       = omap2_gpio1_irqs,
 661         .main_clk       = "gpios_fck",
 662         .prcm           = {
 663                 .omap2 = {
 664                         .prcm_reg_id = 1,
 665                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 666                         .module_offs = WKUP_MOD,
 667                         .idlest_reg_id = 1,
 668                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 669                 },
 670         },
 671         .class          = &omap2xxx_gpio_hwmod_class,
 672         .dev_attr       = &omap2xxx_gpio_dev_attr,
 673 };
 674
 675 /* gpio2 */
 676 struct omap_hwmod omap2xxx_gpio2_hwmod = {
 677         .name           = "gpio2",
 678         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 679         .mpu_irqs       = omap2_gpio2_irqs,
 680         .main_clk       = "gpios_fck",
 681         .prcm           = {
 682                 .omap2 = {
 683                         .prcm_reg_id = 1,
 684                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 685                         .module_offs = WKUP_MOD,
 686                         .idlest_reg_id = 1,
 687                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 688                 },
 689         },
 690         .class          = &omap2xxx_gpio_hwmod_class,
 691         .dev_attr       = &omap2xxx_gpio_dev_attr,
 692 };
 693
 694 /* gpio3 */
 695 struct omap_hwmod omap2xxx_gpio3_hwmod = {
 696         .name           = "gpio3",
 697         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 698         .mpu_irqs       = omap2_gpio3_irqs,
 699         .main_clk       = "gpios_fck",
 700         .prcm           = {
 701                 .omap2 = {
 702                         .prcm_reg_id = 1,
 703                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 704                         .module_offs = WKUP_MOD,
 705                         .idlest_reg_id = 1,
 706                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 707                 },
 708         },
 709         .class          = &omap2xxx_gpio_hwmod_class,
 710         .dev_attr       = &omap2xxx_gpio_dev_attr,
 711 };
 712
 713 /* gpio4 */
 714 struct omap_hwmod omap2xxx_gpio4_hwmod = {
 715         .name           = "gpio4",
 716         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 717         .mpu_irqs       = omap2_gpio4_irqs,
 718         .main_clk       = "gpios_fck",
 719         .prcm           = {
 720                 .omap2 = {
 721                         .prcm_reg_id = 1,
 722                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 723                         .module_offs = WKUP_MOD,
 724                         .idlest_reg_id = 1,
 725                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 726                 },
 727         },
 728         .class          = &omap2xxx_gpio_hwmod_class,
 729         .dev_attr       = &omap2xxx_gpio_dev_attr,
 730 };
 731
 732 /* mcspi1 */
 733 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
 734         .num_chipselect = 4,
 735 };
 736
 737 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
 738         .name           = "mcspi1",
 739         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
 740         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
 741         .main_clk       = "mcspi1_fck",
 742         .prcm           = {
 743                 .omap2 = {
 744                         .module_offs = CORE_MOD,
 745                         .prcm_reg_id = 1,
 746                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
 747                         .idlest_reg_id = 1,
 748                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
 749                 },
 750         },
 751         .class          = &omap2xxx_mcspi_class,
 752         .dev_attr       = &omap_mcspi1_dev_attr,
 753 };
 754
 755 /* mcspi2 */
 756 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
 757         .num_chipselect = 2,
 758 };
 759
 760 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
 761         .name           = "mcspi2",
 762         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
 763         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
 764         .main_clk       = "mcspi2_fck",
 765         .prcm           = {
 766                 .omap2 = {
 767                         .module_offs = CORE_MOD,
 768                         .prcm_reg_id = 1,
 769                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
 770                         .idlest_reg_id = 1,
 771                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
 772                 },
 773         },
 774         .class          = &omap2xxx_mcspi_class,
 775         .dev_attr       = &omap_mcspi2_dev_attr,
 776 };
 777
 778 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
 779         .name   = "counter",
 780 };
 781
 782 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
 783         .name           = "counter_32k",
 784         .main_clk       = "func_32k_ck",
 785         .prcm           = {
 786                 .omap2  = {
 787                         .module_offs = WKUP_MOD,
 788                         .prcm_reg_id = 1,
 789                         .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
 790                         .idlest_reg_id = 1,
 791                         .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
 792                 },
 793         },
 794         .class          = &omap2xxx_counter_hwmod_class,
 795 };
 796
 797 /* gpmc */
 798 static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = {
 799         { .irq = 20 },
 800         { .irq = -1 }
 801 };
 802
 803 struct omap_hwmod omap2xxx_gpmc_hwmod = {
 804         .name           = "gpmc",
 805         .class          = &omap2xxx_gpmc_hwmod_class,
 806         .mpu_irqs       = omap2xxx_gpmc_irqs,
 807         .main_clk       = "gpmc_fck",
 808         /*
 809          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
 810          * block.  It is not being added due to any known bugs with
 811          * resetting the GPMC IP block, but rather because any timings
 812          * set by the bootloader are not being correctly programmed by
 813          * the kernel from the board file or DT data.
 814          * HWMOD_INIT_NO_RESET should be removed ASAP.
 815          */
 816         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
 817                            HWMOD_NO_IDLEST),
 818         .prcm           = {
 819                 .omap2  = {
 820                         .prcm_reg_id = 3,
 821                         .module_bit = OMAP24XX_EN_GPMC_MASK,
 822                         .module_offs = CORE_MOD,
 823                 },
 824         },
 825 };
 826
 827 /* RNG */
 828
 829 static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
 830         .rev_offs       = 0x3c,
 831         .sysc_offs      = 0x40,
 832         .syss_offs      = 0x44,
 833         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 834                            SYSS_HAS_RESET_STATUS),
 835         .sysc_fields    = &omap_hwmod_sysc_type1,
 836 };
 837
 838 static struct omap_hwmod_class omap2_rng_hwmod_class = {
 839         .name           = "rng",
 840         .sysc           = &omap2_rng_sysc,
 841 };
 842
 843 static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = {
 844         { .irq = 52 },
 845         { .irq = -1 }
 846 };
 847
 848 struct omap_hwmod omap2xxx_rng_hwmod = {
 849         .name           = "rng",
 850         .mpu_irqs       = omap2_rng_mpu_irqs,
 851         .main_clk       = "l4_ck",
 852         .prcm           = {
 853                 .omap2 = {
 854                         .module_offs = CORE_MOD,
 855                         .prcm_reg_id = 4,
 856                         .module_bit = OMAP24XX_EN_RNG_SHIFT,
 857                         .idlest_reg_id = 4,
 858                         .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
 859                 },
 860         },
 861         /*
 862          * XXX The first read from the SYSSTATUS register of the RNG
 863          * after the SYSCONFIG SOFTRESET bit is set triggers an
 864          * imprecise external abort.  It's unclear why this happens.
 865          * Until this is analyzed, skip the IP block reset.
 866          */
 867         .flags          = HWMOD_INIT_NO_RESET,
 868         .class          = &omap2_rng_hwmod_class,
 869 };
 870
 871 /* SHAM */
 872
 873 static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
 874         .rev_offs       = 0x5c,
 875         .sysc_offs      = 0x60,
 876         .syss_offs      = 0x64,
 877         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 878                            SYSS_HAS_RESET_STATUS),
 879         .sysc_fields    = &omap_hwmod_sysc_type1,
 880 };
 881
 882 static struct omap_hwmod_class omap2xxx_sham_class = {
 883         .name   = "sham",
 884         .sysc   = &omap2_sham_sysc,
 885 };
 886
 887 static struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = {
 888         { .irq = 51 + OMAP_INTC_START, },
 889         { .irq = -1 }
 890 };
 891
 892 static struct omap_hwmod_dma_info omap2_sham_sdma_chs[] = {
 893         { .name = "rx", .dma_req = 13 },
 894         { .dma_req = -1 }
 895 };
 896
 897 struct omap_hwmod omap2xxx_sham_hwmod = {
 898         .name           = "sham",
 899         .mpu_irqs       = omap2_sham_mpu_irqs,
 900         .sdma_reqs      = omap2_sham_sdma_chs,
 901         .main_clk       = "l4_ck",
 902         .prcm           = {
 903                 .omap2 = {
 904                         .module_offs = CORE_MOD,
 905                         .prcm_reg_id = 4,
 906                         .module_bit = OMAP24XX_EN_SHA_SHIFT,
 907                         .idlest_reg_id = 4,
 908                         .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
 909                 },
 910         },
 911         .class          = &omap2xxx_sham_class,
 912 };
 913
 914 /* AES */
 915
 916 static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
 917         .rev_offs       = 0x44,
 918         .sysc_offs      = 0x48,
 919         .syss_offs      = 0x4c,
 920         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 921                            SYSS_HAS_RESET_STATUS),
 922         .sysc_fields    = &omap_hwmod_sysc_type1,
 923 };
 924
 925 static struct omap_hwmod_class omap2xxx_aes_class = {
 926         .name   = "aes",
 927         .sysc   = &omap2_aes_sysc,
 928 };
 929
 930 static struct omap_hwmod_dma_info omap2_aes_sdma_chs[] = {
 931         { .name = "tx", .dma_req = 9 },
 932         { .name = "rx", .dma_req = 10 },
 933         { .dma_req = -1 }
 934 };
 935
 936 struct omap_hwmod omap2xxx_aes_hwmod = {
 937         .name           = "aes",
 938         .sdma_reqs      = omap2_aes_sdma_chs,
 939         .main_clk       = "l4_ck",
 940         .prcm           = {
 941                 .omap2 = {
 942                         .module_offs = CORE_MOD,
 943                         .prcm_reg_id = 4,
 944                         .module_bit = OMAP24XX_EN_AES_SHIFT,
 945                         .idlest_reg_id = 4,
 946                         .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
 947                 },
 948         },
 949         .class          = &omap2xxx_aes_class,
 950 };