2 * Mailbox reservation modules for OMAP2/3
4 * Copyright (C) 2006-2009 Nokia Corporation
5 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/kernel.h>
14 #include <linux/clk.h>
15 #include <linux/err.h>
16 #include <linux/platform_device.h>
18 #include <plat/mailbox.h>
19 #include <mach/irqs.h>
21 #define MAILBOX_REVISION 0x000
22 #define MAILBOX_SYSCONFIG 0x010
23 #define MAILBOX_SYSSTATUS 0x014
24 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
25 #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
26 #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
27 #define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
28 #define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
30 #define MAILBOX_IRQ_NEWMSG(u) (1 << (2 * (u)))
31 #define MAILBOX_IRQ_NOTFULL(u) (1 << (2 * (u) + 1))
33 /* SYSCONFIG: register bit definition */
34 #define AUTOIDLE (1 << 0)
35 #define SOFTRESET (1 << 1)
36 #define SMARTIDLE (2 << 3)
38 /* SYSSTATUS: register bit definition */
39 #define RESETDONE (1 << 0)
41 #define MBOX_REG_SIZE 0x120
42 #define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
44 static void __iomem
*mbox_base
;
46 struct omap_mbox2_fifo
{
48 unsigned long fifo_stat
;
49 unsigned long msg_stat
;
52 struct omap_mbox2_priv
{
53 struct omap_mbox2_fifo tx_fifo
;
54 struct omap_mbox2_fifo rx_fifo
;
55 unsigned long irqenable
;
56 unsigned long irqstatus
;
59 u32 ctx
[MBOX_NR_REGS
];
62 static struct clk
*mbox_ick_handle
;
64 static void omap2_mbox_enable_irq(struct omap_mbox
*mbox
,
65 omap_mbox_type_t irq
);
67 static inline unsigned int mbox_read_reg(size_t ofs
)
69 return __raw_readl(mbox_base
+ ofs
);
72 static inline void mbox_write_reg(u32 val
, size_t ofs
)
74 __raw_writel(val
, mbox_base
+ ofs
);
77 /* Mailbox H/W preparations */
78 static int omap2_mbox_startup(struct omap_mbox
*mbox
)
81 unsigned long timeout
;
83 mbox_ick_handle
= clk_get(NULL
, "mailboxes_ick");
84 if (IS_ERR(mbox_ick_handle
)) {
85 pr_err("Can't get mailboxes_ick\n");
88 clk_enable(mbox_ick_handle
);
90 mbox_write_reg(SOFTRESET
, MAILBOX_SYSCONFIG
);
91 timeout
= jiffies
+ msecs_to_jiffies(20);
93 l
= mbox_read_reg(MAILBOX_SYSSTATUS
);
96 } while (!time_after(jiffies
, timeout
));
98 if (!(l
& RESETDONE
)) {
99 pr_err("Can't take mmu out of reset\n");
103 l
= mbox_read_reg(MAILBOX_REVISION
);
104 pr_info("omap mailbox rev %d.%d\n", (l
& 0xf0) >> 4, (l
& 0x0f));
106 l
= SMARTIDLE
| AUTOIDLE
;
107 mbox_write_reg(l
, MAILBOX_SYSCONFIG
);
109 omap2_mbox_enable_irq(mbox
, IRQ_RX
);
114 static void omap2_mbox_shutdown(struct omap_mbox
*mbox
)
116 clk_disable(mbox_ick_handle
);
117 clk_put(mbox_ick_handle
);
120 /* Mailbox FIFO handle functions */
121 static mbox_msg_t
omap2_mbox_fifo_read(struct omap_mbox
*mbox
)
123 struct omap_mbox2_fifo
*fifo
=
124 &((struct omap_mbox2_priv
*)mbox
->priv
)->rx_fifo
;
125 return (mbox_msg_t
) mbox_read_reg(fifo
->msg
);
128 static void omap2_mbox_fifo_write(struct omap_mbox
*mbox
, mbox_msg_t msg
)
130 struct omap_mbox2_fifo
*fifo
=
131 &((struct omap_mbox2_priv
*)mbox
->priv
)->tx_fifo
;
132 mbox_write_reg(msg
, fifo
->msg
);
135 static int omap2_mbox_fifo_empty(struct omap_mbox
*mbox
)
137 struct omap_mbox2_fifo
*fifo
=
138 &((struct omap_mbox2_priv
*)mbox
->priv
)->rx_fifo
;
139 return (mbox_read_reg(fifo
->msg_stat
) == 0);
142 static int omap2_mbox_fifo_full(struct omap_mbox
*mbox
)
144 struct omap_mbox2_fifo
*fifo
=
145 &((struct omap_mbox2_priv
*)mbox
->priv
)->tx_fifo
;
146 return (mbox_read_reg(fifo
->fifo_stat
));
149 /* Mailbox IRQ handle functions */
150 static void omap2_mbox_enable_irq(struct omap_mbox
*mbox
,
151 omap_mbox_type_t irq
)
153 struct omap_mbox2_priv
*p
= (struct omap_mbox2_priv
*)mbox
->priv
;
154 u32 l
, bit
= (irq
== IRQ_TX
) ? p
->notfull_bit
: p
->newmsg_bit
;
156 l
= mbox_read_reg(p
->irqenable
);
158 mbox_write_reg(l
, p
->irqenable
);
161 static void omap2_mbox_disable_irq(struct omap_mbox
*mbox
,
162 omap_mbox_type_t irq
)
164 struct omap_mbox2_priv
*p
= (struct omap_mbox2_priv
*)mbox
->priv
;
165 u32 l
, bit
= (irq
== IRQ_TX
) ? p
->notfull_bit
: p
->newmsg_bit
;
167 l
= mbox_read_reg(p
->irqenable
);
169 mbox_write_reg(l
, p
->irqenable
);
172 static void omap2_mbox_ack_irq(struct omap_mbox
*mbox
,
173 omap_mbox_type_t irq
)
175 struct omap_mbox2_priv
*p
= (struct omap_mbox2_priv
*)mbox
->priv
;
176 u32 bit
= (irq
== IRQ_TX
) ? p
->notfull_bit
: p
->newmsg_bit
;
178 mbox_write_reg(bit
, p
->irqstatus
);
180 /* Flush posted write for irq status to avoid spurious interrupts */
181 mbox_read_reg(p
->irqstatus
);
184 static int omap2_mbox_is_irq(struct omap_mbox
*mbox
,
185 omap_mbox_type_t irq
)
187 struct omap_mbox2_priv
*p
= (struct omap_mbox2_priv
*)mbox
->priv
;
188 u32 bit
= (irq
== IRQ_TX
) ? p
->notfull_bit
: p
->newmsg_bit
;
189 u32 enable
= mbox_read_reg(p
->irqenable
);
190 u32 status
= mbox_read_reg(p
->irqstatus
);
192 return (enable
& status
& bit
);
195 static void omap2_mbox_save_ctx(struct omap_mbox
*mbox
)
198 struct omap_mbox2_priv
*p
= mbox
->priv
;
200 for (i
= 0; i
< MBOX_NR_REGS
; i
++) {
201 p
->ctx
[i
] = mbox_read_reg(i
* sizeof(u32
));
203 dev_dbg(mbox
->dev
, "%s: [%02x] %08x\n", __func__
,
208 static void omap2_mbox_restore_ctx(struct omap_mbox
*mbox
)
211 struct omap_mbox2_priv
*p
= mbox
->priv
;
213 for (i
= 0; i
< MBOX_NR_REGS
; i
++) {
214 mbox_write_reg(p
->ctx
[i
], i
* sizeof(u32
));
216 dev_dbg(mbox
->dev
, "%s: [%02x] %08x\n", __func__
,
221 static struct omap_mbox_ops omap2_mbox_ops
= {
222 .type
= OMAP_MBOX_TYPE2
,
223 .startup
= omap2_mbox_startup
,
224 .shutdown
= omap2_mbox_shutdown
,
225 .fifo_read
= omap2_mbox_fifo_read
,
226 .fifo_write
= omap2_mbox_fifo_write
,
227 .fifo_empty
= omap2_mbox_fifo_empty
,
228 .fifo_full
= omap2_mbox_fifo_full
,
229 .enable_irq
= omap2_mbox_enable_irq
,
230 .disable_irq
= omap2_mbox_disable_irq
,
231 .ack_irq
= omap2_mbox_ack_irq
,
232 .is_irq
= omap2_mbox_is_irq
,
233 .save_ctx
= omap2_mbox_save_ctx
,
234 .restore_ctx
= omap2_mbox_restore_ctx
,
238 * MAILBOX 0: ARM -> DSP,
239 * MAILBOX 1: ARM <- DSP.
240 * MAILBOX 2: ARM -> IVA,
241 * MAILBOX 3: ARM <- IVA.
244 /* FIXME: the following structs should be filled automatically by the user id */
247 static struct omap_mbox2_priv omap2_mbox_dsp_priv
= {
249 .msg
= MAILBOX_MESSAGE(0),
250 .fifo_stat
= MAILBOX_FIFOSTATUS(0),
253 .msg
= MAILBOX_MESSAGE(1),
254 .msg_stat
= MAILBOX_MSGSTATUS(1),
256 .irqenable
= MAILBOX_IRQENABLE(0),
257 .irqstatus
= MAILBOX_IRQSTATUS(0),
258 .notfull_bit
= MAILBOX_IRQ_NOTFULL(0),
259 .newmsg_bit
= MAILBOX_IRQ_NEWMSG(1),
262 struct omap_mbox mbox_dsp_info
= {
264 .ops
= &omap2_mbox_ops
,
265 .priv
= &omap2_mbox_dsp_priv
,
267 EXPORT_SYMBOL(mbox_dsp_info
);
269 #if defined(CONFIG_ARCH_OMAP2420) /* IVA */
270 static struct omap_mbox2_priv omap2_mbox_iva_priv
= {
272 .msg
= MAILBOX_MESSAGE(2),
273 .fifo_stat
= MAILBOX_FIFOSTATUS(2),
276 .msg
= MAILBOX_MESSAGE(3),
277 .msg_stat
= MAILBOX_MSGSTATUS(3),
279 .irqenable
= MAILBOX_IRQENABLE(3),
280 .irqstatus
= MAILBOX_IRQSTATUS(3),
281 .notfull_bit
= MAILBOX_IRQ_NOTFULL(2),
282 .newmsg_bit
= MAILBOX_IRQ_NEWMSG(3),
285 static struct omap_mbox mbox_iva_info
= {
287 .ops
= &omap2_mbox_ops
,
288 .priv
= &omap2_mbox_iva_priv
,
292 static int __devinit
omap2_mbox_probe(struct platform_device
*pdev
)
294 struct resource
*res
;
298 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
299 if (unlikely(!res
)) {
300 dev_err(&pdev
->dev
, "invalid mem resource\n");
303 mbox_base
= ioremap(res
->start
, resource_size(res
));
307 /* DSP or IVA2 IRQ */
308 ret
= platform_get_irq(pdev
, 0);
310 dev_err(&pdev
->dev
, "invalid irq resource\n");
313 mbox_dsp_info
.irq
= ret
;
315 ret
= omap_mbox_register(&pdev
->dev
, &mbox_dsp_info
);
319 #if defined(CONFIG_ARCH_OMAP2420) /* IVA */
320 if (cpu_is_omap2420()) {
322 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 1);
323 if (unlikely(!res
)) {
324 dev_err(&pdev
->dev
, "invalid irq resource\n");
328 mbox_iva_info
.irq
= res
->start
;
329 ret
= omap_mbox_register(&pdev
->dev
, &mbox_iva_info
);
337 omap_mbox_unregister(&mbox_dsp_info
);
343 static int __devexit
omap2_mbox_remove(struct platform_device
*pdev
)
345 #if defined(CONFIG_ARCH_OMAP2420)
346 omap_mbox_unregister(&mbox_iva_info
);
348 omap_mbox_unregister(&mbox_dsp_info
);
353 static struct platform_driver omap2_mbox_driver
= {
354 .probe
= omap2_mbox_probe
,
355 .remove
= __devexit_p(omap2_mbox_remove
),
357 .name
= "omap2-mailbox",
361 static int __init
omap2_mbox_init(void)
363 return platform_driver_register(&omap2_mbox_driver
);
366 static void __exit
omap2_mbox_exit(void)
368 platform_driver_unregister(&omap2_mbox_driver
);
371 module_init(omap2_mbox_init
);
372 module_exit(omap2_mbox_exit
);
374 MODULE_LICENSE("GPL v2");
375 MODULE_DESCRIPTION("omap mailbox: omap2/3 architecture specific functions");
376 MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt");
377 MODULE_ALIAS("platform:omap2-mailbox");