2 * linux/arch/arm/mach-omap2/devices.c
4 * OMAP2 platform device setup/initialization
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
17 #include <linux/clk.h>
19 #include <mach/hardware.h>
20 #include <asm/mach-types.h>
21 #include <asm/mach/map.h>
23 #include <mach/control.h>
25 #include <mach/board.h>
27 #include <mach/gpio.h>
30 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
32 static struct resource cam_resources
[] = {
34 .start
= OMAP24XX_CAMERA_BASE
,
35 .end
= OMAP24XX_CAMERA_BASE
+ 0xfff,
36 .flags
= IORESOURCE_MEM
,
39 .start
= INT_24XX_CAM_IRQ
,
40 .flags
= IORESOURCE_IRQ
,
44 static struct platform_device omap_cam_device
= {
45 .name
= "omap24xxcam",
47 .num_resources
= ARRAY_SIZE(cam_resources
),
48 .resource
= cam_resources
,
51 static inline void omap_init_camera(void)
53 platform_device_register(&omap_cam_device
);
56 #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
58 static struct resource omap3isp_resources
[] = {
60 .start
= OMAP3430_ISP_BASE
,
61 .end
= OMAP3430_ISP_END
,
62 .flags
= IORESOURCE_MEM
,
65 .start
= OMAP3430_ISP_CBUFF_BASE
,
66 .end
= OMAP3430_ISP_CBUFF_END
,
67 .flags
= IORESOURCE_MEM
,
70 .start
= OMAP3430_ISP_CCP2_BASE
,
71 .end
= OMAP3430_ISP_CCP2_END
,
72 .flags
= IORESOURCE_MEM
,
75 .start
= OMAP3430_ISP_CCDC_BASE
,
76 .end
= OMAP3430_ISP_CCDC_END
,
77 .flags
= IORESOURCE_MEM
,
80 .start
= OMAP3430_ISP_HIST_BASE
,
81 .end
= OMAP3430_ISP_HIST_END
,
82 .flags
= IORESOURCE_MEM
,
85 .start
= OMAP3430_ISP_H3A_BASE
,
86 .end
= OMAP3430_ISP_H3A_END
,
87 .flags
= IORESOURCE_MEM
,
90 .start
= OMAP3430_ISP_PREV_BASE
,
91 .end
= OMAP3430_ISP_PREV_END
,
92 .flags
= IORESOURCE_MEM
,
95 .start
= OMAP3430_ISP_RESZ_BASE
,
96 .end
= OMAP3430_ISP_RESZ_END
,
97 .flags
= IORESOURCE_MEM
,
100 .start
= OMAP3430_ISP_SBL_BASE
,
101 .end
= OMAP3430_ISP_SBL_END
,
102 .flags
= IORESOURCE_MEM
,
105 .start
= OMAP3430_ISP_CSI2A_BASE
,
106 .end
= OMAP3430_ISP_CSI2A_END
,
107 .flags
= IORESOURCE_MEM
,
110 .start
= OMAP3430_ISP_CSI2PHY_BASE
,
111 .end
= OMAP3430_ISP_CSI2PHY_END
,
112 .flags
= IORESOURCE_MEM
,
115 .start
= INT_34XX_CAM_IRQ
,
116 .flags
= IORESOURCE_IRQ
,
120 static struct platform_device omap3isp_device
= {
123 .num_resources
= ARRAY_SIZE(omap3isp_resources
),
124 .resource
= omap3isp_resources
,
127 static inline void omap_init_camera(void)
129 platform_device_register(&omap3isp_device
);
132 static inline void omap_init_camera(void)
137 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
139 #define MBOX_REG_SIZE 0x120
141 static struct resource omap2_mbox_resources
[] = {
143 .start
= OMAP24XX_MAILBOX_BASE
,
144 .end
= OMAP24XX_MAILBOX_BASE
+ MBOX_REG_SIZE
- 1,
145 .flags
= IORESOURCE_MEM
,
148 .start
= INT_24XX_MAIL_U0_MPU
,
149 .flags
= IORESOURCE_IRQ
,
152 .start
= INT_24XX_MAIL_U3_MPU
,
153 .flags
= IORESOURCE_IRQ
,
157 static struct resource omap3_mbox_resources
[] = {
159 .start
= OMAP34XX_MAILBOX_BASE
,
160 .end
= OMAP34XX_MAILBOX_BASE
+ MBOX_REG_SIZE
- 1,
161 .flags
= IORESOURCE_MEM
,
164 .start
= INT_24XX_MAIL_U0_MPU
,
165 .flags
= IORESOURCE_IRQ
,
169 static struct platform_device mbox_device
= {
170 .name
= "omap2-mailbox",
174 static inline void omap_init_mbox(void)
176 if (cpu_is_omap2420()) {
177 mbox_device
.num_resources
= ARRAY_SIZE(omap2_mbox_resources
);
178 mbox_device
.resource
= omap2_mbox_resources
;
179 } else if (cpu_is_omap3430()) {
180 mbox_device
.num_resources
= ARRAY_SIZE(omap3_mbox_resources
);
181 mbox_device
.resource
= omap3_mbox_resources
;
183 pr_err("%s: platform not supported\n", __func__
);
186 platform_device_register(&mbox_device
);
189 static inline void omap_init_mbox(void) { }
190 #endif /* CONFIG_OMAP_MBOX_FWK */
192 #if defined(CONFIG_OMAP_STI)
194 #if defined(CONFIG_ARCH_OMAP2)
196 #define OMAP2_STI_BASE 0x48068000
197 #define OMAP2_STI_CHANNEL_BASE 0x54000000
198 #define OMAP2_STI_IRQ 4
200 static struct resource sti_resources
[] = {
202 .start
= OMAP2_STI_BASE
,
203 .end
= OMAP2_STI_BASE
+ 0x7ff,
204 .flags
= IORESOURCE_MEM
,
207 .start
= OMAP2_STI_CHANNEL_BASE
,
208 .end
= OMAP2_STI_CHANNEL_BASE
+ SZ_64K
- 1,
209 .flags
= IORESOURCE_MEM
,
212 .start
= OMAP2_STI_IRQ
,
213 .flags
= IORESOURCE_IRQ
,
216 #elif defined(CONFIG_ARCH_OMAP3)
218 #define OMAP3_SDTI_BASE 0x54500000
219 #define OMAP3_SDTI_CHANNEL_BASE 0x54600000
221 static struct resource sti_resources
[] = {
223 .start
= OMAP3_SDTI_BASE
,
224 .end
= OMAP3_SDTI_BASE
+ 0xFFF,
225 .flags
= IORESOURCE_MEM
,
228 .start
= OMAP3_SDTI_CHANNEL_BASE
,
229 .end
= OMAP3_SDTI_CHANNEL_BASE
+ SZ_1M
- 1,
230 .flags
= IORESOURCE_MEM
,
236 static struct platform_device sti_device
= {
239 .num_resources
= ARRAY_SIZE(sti_resources
),
240 .resource
= sti_resources
,
243 static inline void omap_init_sti(void)
245 platform_device_register(&sti_device
);
248 static inline void omap_init_sti(void) {}
251 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
253 #include <mach/mcspi.h>
255 #define OMAP2_MCSPI1_BASE 0x48098000
256 #define OMAP2_MCSPI2_BASE 0x4809a000
257 #define OMAP2_MCSPI3_BASE 0x480b8000
258 #define OMAP2_MCSPI4_BASE 0x480ba000
260 #define OMAP4_MCSPI1_BASE 0x48098100
261 #define OMAP4_MCSPI2_BASE 0x4809a100
262 #define OMAP4_MCSPI3_BASE 0x480b8100
263 #define OMAP4_MCSPI4_BASE 0x480ba100
265 static struct omap2_mcspi_platform_config omap2_mcspi1_config
= {
269 static struct resource omap2_mcspi1_resources
[] = {
271 .start
= OMAP2_MCSPI1_BASE
,
272 .end
= OMAP2_MCSPI1_BASE
+ 0xff,
273 .flags
= IORESOURCE_MEM
,
277 static struct platform_device omap2_mcspi1
= {
278 .name
= "omap2_mcspi",
280 .num_resources
= ARRAY_SIZE(omap2_mcspi1_resources
),
281 .resource
= omap2_mcspi1_resources
,
283 .platform_data
= &omap2_mcspi1_config
,
287 static struct omap2_mcspi_platform_config omap2_mcspi2_config
= {
291 static struct resource omap2_mcspi2_resources
[] = {
293 .start
= OMAP2_MCSPI2_BASE
,
294 .end
= OMAP2_MCSPI2_BASE
+ 0xff,
295 .flags
= IORESOURCE_MEM
,
299 static struct platform_device omap2_mcspi2
= {
300 .name
= "omap2_mcspi",
302 .num_resources
= ARRAY_SIZE(omap2_mcspi2_resources
),
303 .resource
= omap2_mcspi2_resources
,
305 .platform_data
= &omap2_mcspi2_config
,
309 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
310 defined(CONFIG_ARCH_OMAP4)
311 static struct omap2_mcspi_platform_config omap2_mcspi3_config
= {
315 static struct resource omap2_mcspi3_resources
[] = {
317 .start
= OMAP2_MCSPI3_BASE
,
318 .end
= OMAP2_MCSPI3_BASE
+ 0xff,
319 .flags
= IORESOURCE_MEM
,
323 static struct platform_device omap2_mcspi3
= {
324 .name
= "omap2_mcspi",
326 .num_resources
= ARRAY_SIZE(omap2_mcspi3_resources
),
327 .resource
= omap2_mcspi3_resources
,
329 .platform_data
= &omap2_mcspi3_config
,
334 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
335 static struct omap2_mcspi_platform_config omap2_mcspi4_config
= {
339 static struct resource omap2_mcspi4_resources
[] = {
341 .start
= OMAP2_MCSPI4_BASE
,
342 .end
= OMAP2_MCSPI4_BASE
+ 0xff,
343 .flags
= IORESOURCE_MEM
,
347 static struct platform_device omap2_mcspi4
= {
348 .name
= "omap2_mcspi",
350 .num_resources
= ARRAY_SIZE(omap2_mcspi4_resources
),
351 .resource
= omap2_mcspi4_resources
,
353 .platform_data
= &omap2_mcspi4_config
,
358 static void omap_init_mcspi(void)
360 if (cpu_is_omap44xx()) {
361 omap2_mcspi1_resources
[0].start
= OMAP4_MCSPI1_BASE
;
362 omap2_mcspi1_resources
[0].end
= OMAP4_MCSPI1_BASE
+ 0xff;
363 omap2_mcspi2_resources
[0].start
= OMAP4_MCSPI2_BASE
;
364 omap2_mcspi2_resources
[0].end
= OMAP4_MCSPI2_BASE
+ 0xff;
365 omap2_mcspi3_resources
[0].start
= OMAP4_MCSPI3_BASE
;
366 omap2_mcspi3_resources
[0].end
= OMAP4_MCSPI3_BASE
+ 0xff;
367 omap2_mcspi4_resources
[0].start
= OMAP4_MCSPI4_BASE
;
368 omap2_mcspi4_resources
[0].end
= OMAP4_MCSPI4_BASE
+ 0xff;
370 platform_device_register(&omap2_mcspi1
);
371 platform_device_register(&omap2_mcspi2
);
372 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
373 defined(CONFIG_ARCH_OMAP4)
374 if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
375 platform_device_register(&omap2_mcspi3
);
377 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
378 if (cpu_is_omap343x() || cpu_is_omap44xx())
379 platform_device_register(&omap2_mcspi4
);
384 static inline void omap_init_mcspi(void) {}
387 #ifdef CONFIG_OMAP_SHA1_MD5
388 static struct resource sha1_md5_resources
[] = {
390 .start
= OMAP24XX_SEC_SHA1MD5_BASE
,
391 .end
= OMAP24XX_SEC_SHA1MD5_BASE
+ 0x64,
392 .flags
= IORESOURCE_MEM
,
395 .start
= INT_24XX_SHA1MD5
,
396 .flags
= IORESOURCE_IRQ
,
400 static struct platform_device sha1_md5_device
= {
401 .name
= "OMAP SHA1/MD5",
403 .num_resources
= ARRAY_SIZE(sha1_md5_resources
),
404 .resource
= sha1_md5_resources
,
407 static void omap_init_sha1_md5(void)
409 platform_device_register(&sha1_md5_device
);
412 static inline void omap_init_sha1_md5(void) { }
415 /*-------------------------------------------------------------------------*/
417 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
419 #define MMCHS_SYSCONFIG 0x0010
420 #define MMCHS_SYSCONFIG_SWRESET (1 << 1)
421 #define MMCHS_SYSSTATUS 0x0014
422 #define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
424 static struct platform_device dummy_pdev
= {
426 .bus
= &platform_bus_type
,
431 * omap_hsmmc_reset() - Full reset of each HS-MMC controller
433 * Ensure that each MMC controller is fully reset. Controllers
434 * left in an unknown state (by bootloader) may prevent retention
435 * or OFF-mode. This is especially important in cases where the
436 * MMC driver is not enabled, _or_ built as a module.
438 * In order for reset to work, interface, functional and debounce
439 * clocks must be enabled. The debounce clock comes from func_32k_clk
440 * and is not under SW control, so we only enable i- and f-clocks.
442 static void __init
omap_hsmmc_reset(void)
444 u32 i
, nr_controllers
= cpu_is_omap44xx() ? OMAP44XX_NR_MMC
:
445 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC
: OMAP24XX_NR_MMC
);
447 for (i
= 0; i
< nr_controllers
; i
++) {
449 struct clk
*iclk
, *fclk
;
450 struct device
*dev
= &dummy_pdev
.dev
;
454 base
= OMAP2_MMC1_BASE
;
457 base
= OMAP2_MMC2_BASE
;
460 base
= OMAP3_MMC3_BASE
;
463 if (!cpu_is_omap44xx())
465 base
= OMAP4_MMC4_BASE
;
468 if (!cpu_is_omap44xx())
470 base
= OMAP4_MMC5_BASE
;
474 if (cpu_is_omap44xx())
475 base
+= OMAP4_MMC_REG_OFFSET
;
478 dev_set_name(&dummy_pdev
.dev
, "mmci-omap-hs.%d", i
);
479 iclk
= clk_get(dev
, "ick");
480 if (iclk
&& clk_enable(iclk
))
483 fclk
= clk_get(dev
, "fck");
484 if (fclk
&& clk_enable(fclk
))
487 if (!iclk
|| !fclk
) {
489 "%s: Unable to enable clocks for MMC%d, "
490 "cannot reset.\n", __func__
, i
);
494 omap_writel(MMCHS_SYSCONFIG_SWRESET
, base
+ MMCHS_SYSCONFIG
);
495 v
= omap_readl(base
+ MMCHS_SYSSTATUS
);
496 while (!(omap_readl(base
+ MMCHS_SYSSTATUS
) &
497 MMCHS_SYSSTATUS_RESETDONE
))
511 static inline void omap_hsmmc_reset(void) {}
514 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
515 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
517 static inline void omap2_mmc_mux(struct omap_mmc_platform_data
*mmc_controller
,
520 if (cpu_is_omap2420() && controller_nr
== 0) {
521 omap_cfg_reg(H18_24XX_MMC_CMD
);
522 omap_cfg_reg(H15_24XX_MMC_CLKI
);
523 omap_cfg_reg(G19_24XX_MMC_CLKO
);
524 omap_cfg_reg(F20_24XX_MMC_DAT0
);
525 omap_cfg_reg(F19_24XX_MMC_DAT_DIR0
);
526 omap_cfg_reg(G18_24XX_MMC_CMD_DIR
);
527 if (mmc_controller
->slots
[0].wires
== 4) {
528 omap_cfg_reg(H14_24XX_MMC_DAT1
);
529 omap_cfg_reg(E19_24XX_MMC_DAT2
);
530 omap_cfg_reg(D19_24XX_MMC_DAT3
);
531 omap_cfg_reg(E20_24XX_MMC_DAT_DIR1
);
532 omap_cfg_reg(F18_24XX_MMC_DAT_DIR2
);
533 omap_cfg_reg(E18_24XX_MMC_DAT_DIR3
);
537 * Use internal loop-back in MMC/SDIO Module Input Clock
540 if (mmc_controller
->slots
[0].internal_clock
) {
541 u32 v
= omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0
);
543 omap_ctrl_writel(v
, OMAP2_CONTROL_DEVCONF0
);
547 if (cpu_is_omap3430()) {
548 if (controller_nr
== 0) {
549 omap_cfg_reg(N28_3430_MMC1_CLK
);
550 omap_cfg_reg(M27_3430_MMC1_CMD
);
551 omap_cfg_reg(N27_3430_MMC1_DAT0
);
552 if (mmc_controller
->slots
[0].wires
== 4 ||
553 mmc_controller
->slots
[0].wires
== 8) {
554 omap_cfg_reg(N26_3430_MMC1_DAT1
);
555 omap_cfg_reg(N25_3430_MMC1_DAT2
);
556 omap_cfg_reg(P28_3430_MMC1_DAT3
);
558 if (mmc_controller
->slots
[0].wires
== 8) {
559 omap_cfg_reg(P27_3430_MMC1_DAT4
);
560 omap_cfg_reg(P26_3430_MMC1_DAT5
);
561 omap_cfg_reg(R27_3430_MMC1_DAT6
);
562 omap_cfg_reg(R25_3430_MMC1_DAT7
);
565 if (controller_nr
== 1) {
567 omap_cfg_reg(AE2_3430_MMC2_CLK
);
568 omap_cfg_reg(AG5_3430_MMC2_CMD
);
569 omap_cfg_reg(AH5_3430_MMC2_DAT0
);
572 * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
573 * in the board-*.c files
575 if (mmc_controller
->slots
[0].wires
== 4 ||
576 mmc_controller
->slots
[0].wires
== 8) {
577 omap_cfg_reg(AH4_3430_MMC2_DAT1
);
578 omap_cfg_reg(AG4_3430_MMC2_DAT2
);
579 omap_cfg_reg(AF4_3430_MMC2_DAT3
);
584 * For MMC3 the pins need to be muxed in the board-*.c files
589 void __init
omap2_init_mmc(struct omap_mmc_platform_data
**mmc_data
,
595 for (i
= 0; i
< nr_controllers
; i
++) {
596 unsigned long base
, size
;
597 unsigned int irq
= 0;
602 omap2_mmc_mux(mmc_data
[i
], i
);
606 base
= OMAP2_MMC1_BASE
;
607 irq
= INT_24XX_MMC_IRQ
;
610 base
= OMAP2_MMC2_BASE
;
611 irq
= INT_24XX_MMC2_IRQ
;
614 if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
616 base
= OMAP3_MMC3_BASE
;
617 irq
= INT_34XX_MMC3_IRQ
;
620 if (!cpu_is_omap44xx())
622 base
= OMAP4_MMC4_BASE
+ OMAP4_MMC_REG_OFFSET
;
623 irq
= INT_44XX_MMC4_IRQ
;
626 if (!cpu_is_omap44xx())
628 base
= OMAP4_MMC5_BASE
+ OMAP4_MMC_REG_OFFSET
;
629 irq
= INT_44XX_MMC5_IRQ
;
635 if (cpu_is_omap2420()) {
636 size
= OMAP2420_MMC_SIZE
;
638 } else if (cpu_is_omap44xx()) {
640 base
+= OMAP4_MMC_REG_OFFSET
;
641 irq
+= IRQ_GIC_START
;
643 size
= OMAP4_HSMMC_SIZE
;
644 name
= "mmci-omap-hs";
646 size
= OMAP3_HSMMC_SIZE
;
647 name
= "mmci-omap-hs";
649 omap_mmc_add(name
, i
, base
, size
, irq
, mmc_data
[i
]);
655 /*-------------------------------------------------------------------------*/
657 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
658 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
659 #define OMAP_HDQ_BASE 0x480B2000
661 static struct resource omap_hdq_resources
[] = {
663 .start
= OMAP_HDQ_BASE
,
664 .end
= OMAP_HDQ_BASE
+ 0x1C,
665 .flags
= IORESOURCE_MEM
,
668 .start
= INT_24XX_HDQ_IRQ
,
669 .flags
= IORESOURCE_IRQ
,
672 static struct platform_device omap_hdq_dev
= {
676 .platform_data
= NULL
,
678 .num_resources
= ARRAY_SIZE(omap_hdq_resources
),
679 .resource
= omap_hdq_resources
,
681 static inline void omap_hdq_init(void)
683 (void) platform_device_register(&omap_hdq_dev
);
686 static inline void omap_hdq_init(void) {}
689 /*-------------------------------------------------------------------------*/
691 static int __init
omap2_init_devices(void)
693 /* please keep these calls, and their implementations above,
694 * in alphabetical order so they're easier to sort through.
702 omap_init_sha1_md5();
706 arch_initcall(omap2_init_devices
);