arch/arm/mach-omap2/cpuidle34xx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/cpuidle34xx.c
   3  *
   4  * OMAP3 CPU IDLE Routines
   5  *
   6  * Copyright (C) 2008 Texas Instruments, Inc.
   7  * Rajendra Nayak <rnayak@ti.com>
   8  *
   9  * Copyright (C) 2007 Texas Instruments, Inc.
  10  * Karthik Dasu <karthik-dp@ti.com>
  11  *
  12  * Copyright (C) 2006 Nokia Corporation
  13  * Tony Lindgren <tony@atomide.com>
  14  *
  15  * Copyright (C) 2005 Texas Instruments, Inc.
  16  * Richard Woodruff <r-woodruff2@ti.com>
  17  *
  18  * Based on pm.c for omap2
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License version 2 as
  22  * published by the Free Software Foundation.
  23  */
  24
  25 #include <linux/sched.h>
  26 #include <linux/cpuidle.h>
  27
  28 #include <plat/prcm.h>
  29 #include <plat/irqs.h>
  30 #include "powerdomain.h"
  31 #include "clockdomain.h"
  32 #include <plat/serial.h>
  33
  34 #include "pm.h"
  35 #include "control.h"
  36
  37 #ifdef CONFIG_CPU_IDLE
  38
  39 #define OMAP3_MAX_STATES 7
  40 #define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */
  41 #define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */
  42 #define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */
  43 #define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */
  44 #define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */
  45 #define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */
  46 #define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */
  47
  48 #define OMAP3_STATE_MAX OMAP3_STATE_C7
  49
  50 struct omap3_processor_cx {
  51         u8 valid;
  52         u8 type;
  53         u32 sleep_latency;
  54         u32 wakeup_latency;
  55         u32 mpu_state;
  56         u32 core_state;
  57         u32 threshold;
  58         u32 flags;
  59 };
  60
  61 struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
  62 struct omap3_processor_cx current_cx_state;
  63 struct powerdomain *mpu_pd, *core_pd, *per_pd;
  64 struct powerdomain *cam_pd;
  65
  66 /*
  67  * The latencies/thresholds for various C states have
  68  * to be configured from the respective board files.
  69  * These are some default values (which might not provide
  70  * the best power savings) used on boards which do not
  71  * pass these details from the board file.
  72  */
  73 static struct cpuidle_params cpuidle_params_table[] = {
  74         /* C1 */
  75         {1, 2, 2, 5},
  76         /* C2 */
  77         {1, 10, 10, 30},
  78         /* C3 */
  79         {1, 50, 50, 300},
  80         /* C4 */
  81         {1, 1500, 1800, 4000},
  82         /* C5 */
  83         {1, 2500, 7500, 12000},
  84         /* C6 */
  85         {1, 3000, 8500, 15000},
  86         /* C7 */
  87         {1, 10000, 30000, 300000},
  88 };
  89
  90 static int omap3_idle_bm_check(void)
  91 {
  92         if (!omap3_can_sleep())
  93                 return 1;
  94         return 0;
  95 }
  96
  97 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
  98                                 struct clockdomain *clkdm)
  99 {
 100         omap2_clkdm_allow_idle(clkdm);
 101         return 0;
 102 }
 103
 104 static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
 105                                 struct clockdomain *clkdm)
 106 {
 107         omap2_clkdm_deny_idle(clkdm);
 108         return 0;
 109 }
 110
 111 /**
 112  * omap3_enter_idle - Programs OMAP3 to enter the specified state
 113  * @dev: cpuidle device
 114  * @state: The target state to be programmed
 115  *
 116  * Called from the CPUidle framework to program the device to the
 117  * specified target state selected by the governor.
 118  */
 119 static int omap3_enter_idle(struct cpuidle_device *dev,
 120                         struct cpuidle_state *state)
 121 {
 122         struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
 123         struct timespec ts_preidle, ts_postidle, ts_idle;
 124         u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
 125
 126         current_cx_state = *cx;
 127
 128         /* Used to keep track of the total time in idle */
 129         getnstimeofday(&ts_preidle);
 130
 131         local_irq_disable();
 132         local_fiq_disable();
 133
 134         pwrdm_set_next_pwrst(mpu_pd, mpu_state);
 135         pwrdm_set_next_pwrst(core_pd, core_state);
 136
 137         if (omap_irq_pending() || need_resched())
 138                 goto return_sleep_time;
 139
 140         if (cx->type == OMAP3_STATE_C1) {
 141                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
 142                 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
 143         }
 144
 145         /* Execute ARM wfi */
 146         omap_sram_idle();
 147
 148         if (cx->type == OMAP3_STATE_C1) {
 149                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
 150                 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
 151         }
 152
 153 return_sleep_time:
 154         getnstimeofday(&ts_postidle);
 155         ts_idle = timespec_sub(ts_postidle, ts_preidle);
 156
 157         local_irq_enable();
 158         local_fiq_enable();
 159
 160         return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
 161 }
 162
 163 /**
 164  * next_valid_state - Find next valid c-state
 165  * @dev: cpuidle device
 166  * @state: Currently selected c-state
 167  *
 168  * If the current state is valid, it is returned back to the caller.
 169  * Else, this function searches for a lower c-state which is still
 170  * valid (as defined in omap3_power_states[]).
 171  */
 172 static struct cpuidle_state *next_valid_state(struct cpuidle_device *dev,
 173                                                 struct cpuidle_state *curr)
 174 {
 175         struct cpuidle_state *next = NULL;
 176         struct omap3_processor_cx *cx;
 177
 178         cx = (struct omap3_processor_cx *)cpuidle_get_statedata(curr);
 179
 180         /* Check if current state is valid */
 181         if (cx->valid) {
 182                 return curr;
 183         } else {
 184                 u8 idx = OMAP3_STATE_MAX;
 185
 186                 /*
 187                  * Reach the current state starting at highest C-state
 188                  */
 189                 for (; idx >= OMAP3_STATE_C1; idx--) {
 190                         if (&dev->states[idx] == curr) {
 191                                 next = &dev->states[idx];
 192                                 break;
 193                         }
 194                 }
 195
 196                 /*
 197                  * Should never hit this condition.
 198                  */
 199                 WARN_ON(next == NULL);
 200
 201                 /*
 202                  * Drop to next valid state.
 203                  * Start search from the next (lower) state.
 204                  */
 205                 idx--;
 206                 for (; idx >= OMAP3_STATE_C1; idx--) {
 207                         struct omap3_processor_cx *cx;
 208
 209                         cx = cpuidle_get_statedata(&dev->states[idx]);
 210                         if (cx->valid) {
 211                                 next = &dev->states[idx];
 212                                 break;
 213                         }
 214                 }
 215                 /*
 216                  * C1 and C2 are always valid.
 217                  * So, no need to check for 'next==NULL' outside this loop.
 218                  */
 219         }
 220
 221         return next;
 222 }
 223
 224 /**
 225  * omap3_enter_idle_bm - Checks for any bus activity
 226  * @dev: cpuidle device
 227  * @state: The target state to be programmed
 228  *
 229  * Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This
 230  * function checks for any pending activity and then programs the
 231  * device to the specified or a safer state.
 232  */
 233 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 234                                struct cpuidle_state *state)
 235 {
 236         struct cpuidle_state *new_state = next_valid_state(dev, state);
 237         u32 core_next_state, per_next_state = 0, per_saved_state = 0;
 238         u32 cam_state;
 239         struct omap3_processor_cx *cx;
 240         int ret;
 241
 242         if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
 243                 BUG_ON(!dev->safe_state);
 244                 new_state = dev->safe_state;
 245                 goto select_state;
 246         }
 247
 248         cx = cpuidle_get_statedata(state);
 249         core_next_state = cx->core_state;
 250
 251         /*
 252          * FIXME: we currently manage device-specific idle states
 253          *        for PER and CORE in combination with CPU-specific
 254          *        idle states.  This is wrong, and device-specific
 255          *        idle managment needs to be separated out into
 256          *        its own code.
 257          */
 258
 259         /*
 260          * Prevent idle completely if CAM is active.
 261          * CAM does not have wakeup capability in OMAP3.
 262          */
 263         cam_state = pwrdm_read_pwrst(cam_pd);
 264         if (cam_state == PWRDM_POWER_ON) {
 265                 new_state = dev->safe_state;
 266                 goto select_state;
 267         }
 268
 269         /*
 270          * Prevent PER off if CORE is not in retention or off as this
 271          * would disable PER wakeups completely.
 272          */
 273         per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
 274         if ((per_next_state == PWRDM_POWER_OFF) &&
 275             (core_next_state > PWRDM_POWER_RET))
 276                 per_next_state = PWRDM_POWER_RET;
 277
 278         /* Are we changing PER target state? */
 279         if (per_next_state != per_saved_state)
 280                 pwrdm_set_next_pwrst(per_pd, per_next_state);
 281
 282 select_state:
 283         dev->last_state = new_state;
 284         ret = omap3_enter_idle(dev, new_state);
 285
 286         /* Restore original PER state if it was modified */
 287         if (per_next_state != per_saved_state)
 288                 pwrdm_set_next_pwrst(per_pd, per_saved_state);
 289
 290         return ret;
 291 }
 292
 293 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 294
 295 /**
 296  * omap3_cpuidle_update_states() - Update the cpuidle states
 297  * @mpu_deepest_state:  Enable states upto and including this for mpu domain
 298  * @core_deepest_state: Enable states upto and including this for core domain
 299  *
 300  * This goes through the list of states available and enables and disables the
 301  * validity of C states based on deepest state that can be achieved for the
 302  * variable domain
 303  */
 304 void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state)
 305 {
 306         int i;
 307
 308         for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
 309                 struct omap3_processor_cx *cx = &omap3_power_states[i];
 310
 311                 if ((cx->mpu_state >= mpu_deepest_state) &&
 312                     (cx->core_state >= core_deepest_state)) {
 313                         cx->valid = 1;
 314                 } else {
 315                         cx->valid = 0;
 316                 }
 317         }
 318 }
 319
 320 void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
 321 {
 322         int i;
 323
 324         if (!cpuidle_board_params)
 325                 return;
 326
 327         for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
 328                 cpuidle_params_table[i].valid =
 329                         cpuidle_board_params[i].valid;
 330                 cpuidle_params_table[i].sleep_latency =
 331                         cpuidle_board_params[i].sleep_latency;
 332                 cpuidle_params_table[i].wake_latency =
 333                         cpuidle_board_params[i].wake_latency;
 334                 cpuidle_params_table[i].threshold =
 335                         cpuidle_board_params[i].threshold;
 336         }
 337         return;
 338 }
 339
 340 /* omap3_init_power_states - Initialises the OMAP3 specific C states.
 341  *
 342  * Below is the desciption of each C state.
 343  *      C1 . MPU WFI + Core active
 344  *      C2 . MPU WFI + Core inactive
 345  *      C3 . MPU CSWR + Core inactive
 346  *      C4 . MPU OFF + Core inactive
 347  *      C5 . MPU CSWR + Core CSWR
 348  *      C6 . MPU OFF + Core CSWR
 349  *      C7 . MPU OFF + Core OFF
 350  */
 351 void omap_init_power_states(void)
 352 {
 353         /* C1 . MPU WFI + Core active */
 354         omap3_power_states[OMAP3_STATE_C1].valid =
 355                         cpuidle_params_table[OMAP3_STATE_C1].valid;
 356         omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
 357         omap3_power_states[OMAP3_STATE_C1].sleep_latency =
 358                         cpuidle_params_table[OMAP3_STATE_C1].sleep_latency;
 359         omap3_power_states[OMAP3_STATE_C1].wakeup_latency =
 360                         cpuidle_params_table[OMAP3_STATE_C1].wake_latency;
 361         omap3_power_states[OMAP3_STATE_C1].threshold =
 362                         cpuidle_params_table[OMAP3_STATE_C1].threshold;
 363         omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
 364         omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
 365         omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
 366
 367         /* C2 . MPU WFI + Core inactive */
 368         omap3_power_states[OMAP3_STATE_C2].valid =
 369                         cpuidle_params_table[OMAP3_STATE_C2].valid;
 370         omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
 371         omap3_power_states[OMAP3_STATE_C2].sleep_latency =
 372                         cpuidle_params_table[OMAP3_STATE_C2].sleep_latency;
 373         omap3_power_states[OMAP3_STATE_C2].wakeup_latency =
 374                         cpuidle_params_table[OMAP3_STATE_C2].wake_latency;
 375         omap3_power_states[OMAP3_STATE_C2].threshold =
 376                         cpuidle_params_table[OMAP3_STATE_C2].threshold;
 377         omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
 378         omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
 379         omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID |
 380                                 CPUIDLE_FLAG_CHECK_BM;
 381
 382         /* C3 . MPU CSWR + Core inactive */
 383         omap3_power_states[OMAP3_STATE_C3].valid =
 384                         cpuidle_params_table[OMAP3_STATE_C3].valid;
 385         omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
 386         omap3_power_states[OMAP3_STATE_C3].sleep_latency =
 387                         cpuidle_params_table[OMAP3_STATE_C3].sleep_latency;
 388         omap3_power_states[OMAP3_STATE_C3].wakeup_latency =
 389                         cpuidle_params_table[OMAP3_STATE_C3].wake_latency;
 390         omap3_power_states[OMAP3_STATE_C3].threshold =
 391                         cpuidle_params_table[OMAP3_STATE_C3].threshold;
 392         omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET;
 393         omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
 394         omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
 395                                 CPUIDLE_FLAG_CHECK_BM;
 396
 397         /* C4 . MPU OFF + Core inactive */
 398         omap3_power_states[OMAP3_STATE_C4].valid =
 399                         cpuidle_params_table[OMAP3_STATE_C4].valid;
 400         omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
 401         omap3_power_states[OMAP3_STATE_C4].sleep_latency =
 402                         cpuidle_params_table[OMAP3_STATE_C4].sleep_latency;
 403         omap3_power_states[OMAP3_STATE_C4].wakeup_latency =
 404                         cpuidle_params_table[OMAP3_STATE_C4].wake_latency;
 405         omap3_power_states[OMAP3_STATE_C4].threshold =
 406                         cpuidle_params_table[OMAP3_STATE_C4].threshold;
 407         omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF;
 408         omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
 409         omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
 410                                 CPUIDLE_FLAG_CHECK_BM;
 411
 412         /* C5 . MPU CSWR + Core CSWR*/
 413         omap3_power_states[OMAP3_STATE_C5].valid =
 414                         cpuidle_params_table[OMAP3_STATE_C5].valid;
 415         omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
 416         omap3_power_states[OMAP3_STATE_C5].sleep_latency =
 417                         cpuidle_params_table[OMAP3_STATE_C5].sleep_latency;
 418         omap3_power_states[OMAP3_STATE_C5].wakeup_latency =
 419                         cpuidle_params_table[OMAP3_STATE_C5].wake_latency;
 420         omap3_power_states[OMAP3_STATE_C5].threshold =
 421                         cpuidle_params_table[OMAP3_STATE_C5].threshold;
 422         omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET;
 423         omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
 424         omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
 425                                 CPUIDLE_FLAG_CHECK_BM;
 426
 427         /* C6 . MPU OFF + Core CSWR */
 428         omap3_power_states[OMAP3_STATE_C6].valid =
 429                         cpuidle_params_table[OMAP3_STATE_C6].valid;
 430         omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
 431         omap3_power_states[OMAP3_STATE_C6].sleep_latency =
 432                         cpuidle_params_table[OMAP3_STATE_C6].sleep_latency;
 433         omap3_power_states[OMAP3_STATE_C6].wakeup_latency =
 434                         cpuidle_params_table[OMAP3_STATE_C6].wake_latency;
 435         omap3_power_states[OMAP3_STATE_C6].threshold =
 436                         cpuidle_params_table[OMAP3_STATE_C6].threshold;
 437         omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
 438         omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
 439         omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
 440                                 CPUIDLE_FLAG_CHECK_BM;
 441
 442         /* C7 . MPU OFF + Core OFF */
 443         omap3_power_states[OMAP3_STATE_C7].valid =
 444                         cpuidle_params_table[OMAP3_STATE_C7].valid;
 445         omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
 446         omap3_power_states[OMAP3_STATE_C7].sleep_latency =
 447                         cpuidle_params_table[OMAP3_STATE_C7].sleep_latency;
 448         omap3_power_states[OMAP3_STATE_C7].wakeup_latency =
 449                         cpuidle_params_table[OMAP3_STATE_C7].wake_latency;
 450         omap3_power_states[OMAP3_STATE_C7].threshold =
 451                         cpuidle_params_table[OMAP3_STATE_C7].threshold;
 452         omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF;
 453         omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
 454         omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
 455                                 CPUIDLE_FLAG_CHECK_BM;
 456
 457         /*
 458          * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
 459          * enable OFF mode in a stable form for previous revisions.
 460          * we disable C7 state as a result.
 461          */
 462         if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
 463                 omap3_power_states[OMAP3_STATE_C7].valid = 0;
 464                 cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
 465                 WARN_ONCE(1, "%s: core off state C7 disabled due to i583\n",
 466                                 __func__);
 467         }
 468 }
 469
 470 struct cpuidle_driver omap3_idle_driver = {
 471         .name =         "omap3_idle",
 472         .owner =        THIS_MODULE,
 473 };
 474
 475 /**
 476  * omap3_idle_init - Init routine for OMAP3 idle
 477  *
 478  * Registers the OMAP3 specific cpuidle driver with the cpuidle
 479  * framework with the valid set of states.
 480  */
 481 int __init omap3_idle_init(void)
 482 {
 483         int i, count = 0;
 484         struct omap3_processor_cx *cx;
 485         struct cpuidle_state *state;
 486         struct cpuidle_device *dev;
 487
 488         mpu_pd = pwrdm_lookup("mpu_pwrdm");
 489         core_pd = pwrdm_lookup("core_pwrdm");
 490         per_pd = pwrdm_lookup("per_pwrdm");
 491         cam_pd = pwrdm_lookup("cam_pwrdm");
 492
 493         omap_init_power_states();
 494         cpuidle_register_driver(&omap3_idle_driver);
 495
 496         dev = &per_cpu(omap3_idle_dev, smp_processor_id());
 497
 498         for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
 499                 cx = &omap3_power_states[i];
 500                 state = &dev->states[count];
 501
 502                 if (!cx->valid)
 503                         continue;
 504                 cpuidle_set_statedata(state, cx);
 505                 state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
 506                 state->target_residency = cx->threshold;
 507                 state->flags = cx->flags;
 508                 state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
 509                         omap3_enter_idle_bm : omap3_enter_idle;
 510                 if (cx->type == OMAP3_STATE_C1)
 511                         dev->safe_state = state;
 512                 sprintf(state->name, "C%d", count+1);
 513                 count++;
 514         }
 515
 516         if (!count)
 517                 return -EINVAL;
 518         dev->state_count = count;
 519
 520         if (enable_off_mode)
 521                 omap3_cpuidle_update_states(PWRDM_POWER_OFF, PWRDM_POWER_OFF);
 522         else
 523                 omap3_cpuidle_update_states(PWRDM_POWER_RET, PWRDM_POWER_RET);
 524
 525         if (cpuidle_register_device(dev)) {
 526                 printk(KERN_ERR "%s: CPUidle register device failed\n",
 527                        __func__);
 528                 return -EIO;
 529         }
 530
 531         return 0;
 532 }
 533 #else
 534 int __init omap3_idle_init(void)
 535 {
 536         return 0;
 537 }
 538 #endif /* CONFIG_CPU_IDLE */