arch/arm/mach-omap2/cm-regbits-24xx.h

   1 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
   2 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
   3
   4 /*
   5  * OMAP24XX Clock Management register bits
   6  *
   7  * Copyright (C) 2007 Texas Instruments, Inc.
   8  * Copyright (C) 2007 Nokia Corporation
   9  *
  10  * Written by Paul Walmsley
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include "cm.h"
  18
  19 /* Bits shared between registers */
  20
  21 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
  22 #define OMAP24XX_EN_CAM_SHIFT                           31
  23 #define OMAP24XX_EN_CAM                                 (1 << 31)
  24 #define OMAP24XX_EN_WDT4_SHIFT                          29
  25 #define OMAP24XX_EN_WDT4                                (1 << 29)
  26 #define OMAP2420_EN_WDT3_SHIFT                          28
  27 #define OMAP2420_EN_WDT3                                (1 << 28)
  28 #define OMAP24XX_EN_MSPRO_SHIFT                         27
  29 #define OMAP24XX_EN_MSPRO                               (1 << 27)
  30 #define OMAP24XX_EN_FAC_SHIFT                           25
  31 #define OMAP24XX_EN_FAC                                 (1 << 25)
  32 #define OMAP2420_EN_EAC_SHIFT                           24
  33 #define OMAP2420_EN_EAC                                 (1 << 24)
  34 #define OMAP24XX_EN_HDQ_SHIFT                           23
  35 #define OMAP24XX_EN_HDQ                                 (1 << 23)
  36 #define OMAP2420_EN_I2C2_SHIFT                          20
  37 #define OMAP2420_EN_I2C2                                (1 << 20)
  38 #define OMAP2420_EN_I2C1_SHIFT                          19
  39 #define OMAP2420_EN_I2C1                                (1 << 19)
  40
  41 /* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
  42 #define OMAP2430_EN_MCBSP5_SHIFT                        5
  43 #define OMAP2430_EN_MCBSP5                              (1 << 5)
  44 #define OMAP2430_EN_MCBSP4_SHIFT                        4
  45 #define OMAP2430_EN_MCBSP4                              (1 << 4)
  46 #define OMAP2430_EN_MCBSP3_SHIFT                        3
  47 #define OMAP2430_EN_MCBSP3                              (1 << 3)
  48 #define OMAP24XX_EN_SSI_SHIFT                           1
  49 #define OMAP24XX_EN_SSI                                 (1 << 1)
  50
  51 /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
  52 #define OMAP24XX_EN_MPU_WDT_SHIFT                       3
  53 #define OMAP24XX_EN_MPU_WDT                             (1 << 3)
  54
  55 /* Bits specific to each register */
  56
  57 /* CM_IDLEST_MPU */
  58 /* 2430 only */
  59 #define OMAP2430_ST_MPU                                 (1 << 0)
  60
  61 /* CM_CLKSEL_MPU */
  62 #define OMAP24XX_CLKSEL_MPU_SHIFT                       0
  63 #define OMAP24XX_CLKSEL_MPU_MASK                        (0x1f << 0)
  64
  65 /* CM_CLKSTCTRL_MPU */
  66 #define OMAP24XX_AUTOSTATE_MPU_SHIFT                    0
  67 #define OMAP24XX_AUTOSTATE_MPU_MASK                     (1 << 0)
  68
  69 /* CM_FCLKEN1_CORE specific bits*/
  70 #define OMAP24XX_EN_TV_SHIFT                            2
  71 #define OMAP24XX_EN_TV                                  (1 << 2)
  72 #define OMAP24XX_EN_DSS2_SHIFT                          1
  73 #define OMAP24XX_EN_DSS2                                (1 << 1)
  74 #define OMAP24XX_EN_DSS1_SHIFT                          0
  75 #define OMAP24XX_EN_DSS1                                (1 << 0)
  76
  77 /* CM_FCLKEN2_CORE specific bits */
  78 #define OMAP2430_EN_I2CHS2_SHIFT                        20
  79 #define OMAP2430_EN_I2CHS2                              (1 << 20)
  80 #define OMAP2430_EN_I2CHS1_SHIFT                        19
  81 #define OMAP2430_EN_I2CHS1                              (1 << 19)
  82 #define OMAP2430_EN_MMCHSDB2_SHIFT                      17
  83 #define OMAP2430_EN_MMCHSDB2                            (1 << 17)
  84 #define OMAP2430_EN_MMCHSDB1_SHIFT                      16
  85 #define OMAP2430_EN_MMCHSDB1                            (1 << 16)
  86
  87 /* CM_ICLKEN1_CORE specific bits */
  88 #define OMAP24XX_EN_MAILBOXES_SHIFT                     30
  89 #define OMAP24XX_EN_MAILBOXES                           (1 << 30)
  90 #define OMAP24XX_EN_DSS_SHIFT                           0
  91 #define OMAP24XX_EN_DSS                                 (1 << 0)
  92
  93 /* CM_ICLKEN2_CORE specific bits */
  94
  95 /* CM_ICLKEN3_CORE */
  96 /* 2430 only */
  97 #define OMAP2430_EN_SDRC_SHIFT                          2
  98 #define OMAP2430_EN_SDRC                                (1 << 2)
  99
 100 /* CM_ICLKEN4_CORE */
 101 #define OMAP24XX_EN_PKA_SHIFT                           4
 102 #define OMAP24XX_EN_PKA                                 (1 << 4)
 103 #define OMAP24XX_EN_AES_SHIFT                           3
 104 #define OMAP24XX_EN_AES                                 (1 << 3)
 105 #define OMAP24XX_EN_RNG_SHIFT                           2
 106 #define OMAP24XX_EN_RNG                                 (1 << 2)
 107 #define OMAP24XX_EN_SHA_SHIFT                           1
 108 #define OMAP24XX_EN_SHA                                 (1 << 1)
 109 #define OMAP24XX_EN_DES_SHIFT                           0
 110 #define OMAP24XX_EN_DES                                 (1 << 0)
 111
 112 /* CM_IDLEST1_CORE specific bits */
 113 #define OMAP24XX_ST_MAILBOXES                           (1 << 30)
 114 #define OMAP24XX_ST_WDT4                                (1 << 29)
 115 #define OMAP2420_ST_WDT3                                (1 << 28)
 116 #define OMAP24XX_ST_MSPRO                               (1 << 27)
 117 #define OMAP24XX_ST_FAC                                 (1 << 25)
 118 #define OMAP2420_ST_EAC                                 (1 << 24)
 119 #define OMAP24XX_ST_HDQ                                 (1 << 23)
 120 #define OMAP24XX_ST_I2C2                                (1 << 20)
 121 #define OMAP24XX_ST_I2C1                                (1 << 19)
 122 #define OMAP24XX_ST_MCBSP2                              (1 << 16)
 123 #define OMAP24XX_ST_MCBSP1                              (1 << 15)
 124 #define OMAP24XX_ST_DSS                                 (1 << 0)
 125
 126 /* CM_IDLEST2_CORE */
 127 #define OMAP2430_ST_MCBSP5                              (1 << 5)
 128 #define OMAP2430_ST_MCBSP4                              (1 << 4)
 129 #define OMAP2430_ST_MCBSP3                              (1 << 3)
 130 #define OMAP24XX_ST_SSI                                 (1 << 1)
 131
 132 /* CM_IDLEST3_CORE */
 133 /* 2430 only */
 134 #define OMAP2430_ST_SDRC                                (1 << 2)
 135
 136 /* CM_IDLEST4_CORE */
 137 #define OMAP24XX_ST_PKA                                 (1 << 4)
 138 #define OMAP24XX_ST_AES                                 (1 << 3)
 139 #define OMAP24XX_ST_RNG                                 (1 << 2)
 140 #define OMAP24XX_ST_SHA                                 (1 << 1)
 141 #define OMAP24XX_ST_DES                                 (1 << 0)
 142
 143 /* CM_AUTOIDLE1_CORE */
 144 #define OMAP24XX_AUTO_CAM                               (1 << 31)
 145 #define OMAP24XX_AUTO_MAILBOXES                         (1 << 30)
 146 #define OMAP24XX_AUTO_WDT4                              (1 << 29)
 147 #define OMAP2420_AUTO_WDT3                              (1 << 28)
 148 #define OMAP24XX_AUTO_MSPRO                             (1 << 27)
 149 #define OMAP2420_AUTO_MMC                               (1 << 26)
 150 #define OMAP24XX_AUTO_FAC                               (1 << 25)
 151 #define OMAP2420_AUTO_EAC                               (1 << 24)
 152 #define OMAP24XX_AUTO_HDQ                               (1 << 23)
 153 #define OMAP24XX_AUTO_UART2                             (1 << 22)
 154 #define OMAP24XX_AUTO_UART1                             (1 << 21)
 155 #define OMAP24XX_AUTO_I2C2                              (1 << 20)
 156 #define OMAP24XX_AUTO_I2C1                              (1 << 19)
 157 #define OMAP24XX_AUTO_MCSPI2                            (1 << 18)
 158 #define OMAP24XX_AUTO_MCSPI1                            (1 << 17)
 159 #define OMAP24XX_AUTO_MCBSP2                            (1 << 16)
 160 #define OMAP24XX_AUTO_MCBSP1                            (1 << 15)
 161 #define OMAP24XX_AUTO_GPT12                             (1 << 14)
 162 #define OMAP24XX_AUTO_GPT11                             (1 << 13)
 163 #define OMAP24XX_AUTO_GPT10                             (1 << 12)
 164 #define OMAP24XX_AUTO_GPT9                              (1 << 11)
 165 #define OMAP24XX_AUTO_GPT8                              (1 << 10)
 166 #define OMAP24XX_AUTO_GPT7                              (1 << 9)
 167 #define OMAP24XX_AUTO_GPT6                              (1 << 8)
 168 #define OMAP24XX_AUTO_GPT5                              (1 << 7)
 169 #define OMAP24XX_AUTO_GPT4                              (1 << 6)
 170 #define OMAP24XX_AUTO_GPT3                              (1 << 5)
 171 #define OMAP24XX_AUTO_GPT2                              (1 << 4)
 172 #define OMAP2420_AUTO_VLYNQ                             (1 << 3)
 173 #define OMAP24XX_AUTO_DSS                               (1 << 0)
 174
 175 /* CM_AUTOIDLE2_CORE */
 176 #define OMAP2430_AUTO_MDM_INTC                          (1 << 11)
 177 #define OMAP2430_AUTO_GPIO5                             (1 << 10)
 178 #define OMAP2430_AUTO_MCSPI3                            (1 << 9)
 179 #define OMAP2430_AUTO_MMCHS2                            (1 << 8)
 180 #define OMAP2430_AUTO_MMCHS1                            (1 << 7)
 181 #define OMAP2430_AUTO_USBHS                             (1 << 6)
 182 #define OMAP2430_AUTO_MCBSP5                            (1 << 5)
 183 #define OMAP2430_AUTO_MCBSP4                            (1 << 4)
 184 #define OMAP2430_AUTO_MCBSP3                            (1 << 3)
 185 #define OMAP24XX_AUTO_UART3                             (1 << 2)
 186 #define OMAP24XX_AUTO_SSI                               (1 << 1)
 187 #define OMAP24XX_AUTO_USB                               (1 << 0)
 188
 189 /* CM_AUTOIDLE3_CORE */
 190 #define OMAP24XX_AUTO_SDRC                              (1 << 2)
 191 #define OMAP24XX_AUTO_GPMC                              (1 << 1)
 192 #define OMAP24XX_AUTO_SDMA                              (1 << 0)
 193
 194 /* CM_AUTOIDLE4_CORE */
 195 #define OMAP24XX_AUTO_PKA                               (1 << 4)
 196 #define OMAP24XX_AUTO_AES                               (1 << 3)
 197 #define OMAP24XX_AUTO_RNG                               (1 << 2)
 198 #define OMAP24XX_AUTO_SHA                               (1 << 1)
 199 #define OMAP24XX_AUTO_DES                               (1 << 0)
 200
 201 /* CM_CLKSEL1_CORE */
 202 #define OMAP24XX_CLKSEL_USB_SHIFT                       25
 203 #define OMAP24XX_CLKSEL_USB_MASK                        (0x7 << 25)
 204 #define OMAP24XX_CLKSEL_SSI_SHIFT                       20
 205 #define OMAP24XX_CLKSEL_SSI_MASK                        (0x1f << 20)
 206 #define OMAP2420_CLKSEL_VLYNQ_SHIFT                     15
 207 #define OMAP2420_CLKSEL_VLYNQ_MASK                      (0x1f << 15)
 208 #define OMAP24XX_CLKSEL_DSS2_SHIFT                      13
 209 #define OMAP24XX_CLKSEL_DSS2_MASK                       (0x1 << 13)
 210 #define OMAP24XX_CLKSEL_DSS1_SHIFT                      8
 211 #define OMAP24XX_CLKSEL_DSS1_MASK                       (0x1f << 8)
 212 #define OMAP24XX_CLKSEL_L4_SHIFT                        5
 213 #define OMAP24XX_CLKSEL_L4_MASK                         (0x3 << 5)
 214 #define OMAP24XX_CLKSEL_L3_SHIFT                        0
 215 #define OMAP24XX_CLKSEL_L3_MASK                         (0x1f << 0)
 216
 217 /* CM_CLKSEL2_CORE */
 218 #define OMAP24XX_CLKSEL_GPT12_SHIFT                     22
 219 #define OMAP24XX_CLKSEL_GPT12_MASK                      (0x3 << 22)
 220 #define OMAP24XX_CLKSEL_GPT11_SHIFT                     20
 221 #define OMAP24XX_CLKSEL_GPT11_MASK                      (0x3 << 20)
 222 #define OMAP24XX_CLKSEL_GPT10_SHIFT                     18
 223 #define OMAP24XX_CLKSEL_GPT10_MASK                      (0x3 << 18)
 224 #define OMAP24XX_CLKSEL_GPT9_SHIFT                      16
 225 #define OMAP24XX_CLKSEL_GPT9_MASK                       (0x3 << 16)
 226 #define OMAP24XX_CLKSEL_GPT8_SHIFT                      14
 227 #define OMAP24XX_CLKSEL_GPT8_MASK                       (0x3 << 14)
 228 #define OMAP24XX_CLKSEL_GPT7_SHIFT                      12
 229 #define OMAP24XX_CLKSEL_GPT7_MASK                       (0x3 << 12)
 230 #define OMAP24XX_CLKSEL_GPT6_SHIFT                      10
 231 #define OMAP24XX_CLKSEL_GPT6_MASK                       (0x3 << 10)
 232 #define OMAP24XX_CLKSEL_GPT5_SHIFT                      8
 233 #define OMAP24XX_CLKSEL_GPT5_MASK                       (0x3 << 8)
 234 #define OMAP24XX_CLKSEL_GPT4_SHIFT                      6
 235 #define OMAP24XX_CLKSEL_GPT4_MASK                       (0x3 << 6)
 236 #define OMAP24XX_CLKSEL_GPT3_SHIFT                      4
 237 #define OMAP24XX_CLKSEL_GPT3_MASK                       (0x3 << 4)
 238 #define OMAP24XX_CLKSEL_GPT2_SHIFT                      2
 239 #define OMAP24XX_CLKSEL_GPT2_MASK                       (0x3 << 2)
 240
 241 /* CM_CLKSTCTRL_CORE */
 242 #define OMAP24XX_AUTOSTATE_DSS_SHIFT                    2
 243 #define OMAP24XX_AUTOSTATE_DSS_MASK                     (1 << 2)
 244 #define OMAP24XX_AUTOSTATE_L4_SHIFT                     1
 245 #define OMAP24XX_AUTOSTATE_L4_MASK                      (1 << 1)
 246 #define OMAP24XX_AUTOSTATE_L3_SHIFT                     0
 247 #define OMAP24XX_AUTOSTATE_L3_MASK                      (1 << 0)
 248
 249 /* CM_FCLKEN_GFX */
 250 #define OMAP24XX_EN_3D_SHIFT                            2
 251 #define OMAP24XX_EN_3D                                  (1 << 2)
 252 #define OMAP24XX_EN_2D_SHIFT                            1
 253 #define OMAP24XX_EN_2D                                  (1 << 1)
 254
 255 /* CM_ICLKEN_GFX specific bits */
 256
 257 /* CM_IDLEST_GFX specific bits */
 258
 259 /* CM_CLKSEL_GFX specific bits */
 260
 261 /* CM_CLKSTCTRL_GFX */
 262 #define OMAP24XX_AUTOSTATE_GFX_SHIFT                    0
 263 #define OMAP24XX_AUTOSTATE_GFX_MASK                     (1 << 0)
 264
 265 /* CM_FCLKEN_WKUP specific bits */
 266
 267 /* CM_ICLKEN_WKUP specific bits */
 268 #define OMAP2430_EN_ICR_SHIFT                           6
 269 #define OMAP2430_EN_ICR                                 (1 << 6)
 270 #define OMAP24XX_EN_OMAPCTRL_SHIFT                      5
 271 #define OMAP24XX_EN_OMAPCTRL                            (1 << 5)
 272 #define OMAP24XX_EN_WDT1_SHIFT                          4
 273 #define OMAP24XX_EN_WDT1                                (1 << 4)
 274 #define OMAP24XX_EN_32KSYNC_SHIFT                       1
 275 #define OMAP24XX_EN_32KSYNC                             (1 << 1)
 276
 277 /* CM_IDLEST_WKUP specific bits */
 278 #define OMAP2430_ST_ICR                                 (1 << 6)
 279 #define OMAP24XX_ST_OMAPCTRL                            (1 << 5)
 280 #define OMAP24XX_ST_WDT1                                (1 << 4)
 281 #define OMAP24XX_ST_MPU_WDT                             (1 << 3)
 282 #define OMAP24XX_ST_32KSYNC                             (1 << 1)
 283
 284 /* CM_AUTOIDLE_WKUP */
 285 #define OMAP24XX_AUTO_OMAPCTRL                          (1 << 5)
 286 #define OMAP24XX_AUTO_WDT1                              (1 << 4)
 287 #define OMAP24XX_AUTO_MPU_WDT                           (1 << 3)
 288 #define OMAP24XX_AUTO_GPIOS                             (1 << 2)
 289 #define OMAP24XX_AUTO_32KSYNC                           (1 << 1)
 290 #define OMAP24XX_AUTO_GPT1                              (1 << 0)
 291
 292 /* CM_CLKSEL_WKUP */
 293 #define OMAP24XX_CLKSEL_GPT1_SHIFT                      0
 294 #define OMAP24XX_CLKSEL_GPT1_MASK                       (0x3 << 0)
 295
 296 /* CM_CLKEN_PLL */
 297 #define OMAP24XX_EN_54M_PLL_SHIFT                       6
 298 #define OMAP24XX_EN_54M_PLL_MASK                        (0x3 << 6)
 299 #define OMAP24XX_EN_96M_PLL_SHIFT                       2
 300 #define OMAP24XX_EN_96M_PLL_MASK                        (0x3 << 2)
 301 #define OMAP24XX_EN_DPLL_SHIFT                          0
 302 #define OMAP24XX_EN_DPLL_MASK                           (0x3 << 0)
 303
 304 /* CM_IDLEST_CKGEN */
 305 #define OMAP24XX_ST_54M_APLL                            (1 << 9)
 306 #define OMAP24XX_ST_96M_APLL                            (1 << 8)
 307 #define OMAP24XX_ST_54M_CLK                             (1 << 6)
 308 #define OMAP24XX_ST_12M_CLK                             (1 << 5)
 309 #define OMAP24XX_ST_48M_CLK                             (1 << 4)
 310 #define OMAP24XX_ST_96M_CLK                             (1 << 2)
 311 #define OMAP24XX_ST_CORE_CLK_SHIFT                      0
 312 #define OMAP24XX_ST_CORE_CLK_MASK                       (0x3 << 0)
 313
 314 /* CM_AUTOIDLE_PLL */
 315 #define OMAP24XX_AUTO_54M_SHIFT                         6
 316 #define OMAP24XX_AUTO_54M_MASK                          (0x3 << 6)
 317 #define OMAP24XX_AUTO_96M_SHIFT                         2
 318 #define OMAP24XX_AUTO_96M_MASK                          (0x3 << 2)
 319 #define OMAP24XX_AUTO_DPLL_SHIFT                        0
 320 #define OMAP24XX_AUTO_DPLL_MASK                         (0x3 << 0)
 321
 322 /* CM_CLKSEL1_PLL */
 323 #define OMAP2430_MAXDPLLFASTLOCK_SHIFT                  28
 324 #define OMAP2430_MAXDPLLFASTLOCK_MASK                   (0x7 << 28)
 325 #define OMAP24XX_APLLS_CLKIN_SHIFT                      23
 326 #define OMAP24XX_APLLS_CLKIN_MASK                       (0x7 << 23)
 327 #define OMAP24XX_DPLL_MULT_SHIFT                        12
 328 #define OMAP24XX_DPLL_MULT_MASK                         (0x3ff << 12)
 329 #define OMAP24XX_DPLL_DIV_SHIFT                         8
 330 #define OMAP24XX_DPLL_DIV_MASK                          (0xf << 8)
 331 #define OMAP24XX_54M_SOURCE_SHIFT                       5
 332 #define OMAP24XX_54M_SOURCE                             (1 << 5)
 333 #define OMAP2430_96M_SOURCE_SHIFT                       4
 334 #define OMAP2430_96M_SOURCE                             (1 << 4)
 335 #define OMAP24XX_48M_SOURCE_SHIFT                       3
 336 #define OMAP24XX_48M_SOURCE                             (1 << 3)
 337 #define OMAP2430_ALTCLK_SOURCE_SHIFT                    0
 338 #define OMAP2430_ALTCLK_SOURCE_MASK                     (0x7 << 0)
 339
 340 /* CM_CLKSEL2_PLL */
 341 #define OMAP24XX_CORE_CLK_SRC_SHIFT                     0
 342 #define OMAP24XX_CORE_CLK_SRC_MASK                      (0x3 << 0)
 343
 344 /* CM_FCLKEN_DSP */
 345 #define OMAP2420_EN_IVA_COP_SHIFT                       10
 346 #define OMAP2420_EN_IVA_COP                             (1 << 10)
 347 #define OMAP2420_EN_IVA_MPU_SHIFT                       8
 348 #define OMAP2420_EN_IVA_MPU                             (1 << 8)
 349 #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT             0
 350 #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP                   (1 << 0)
 351
 352 /* CM_ICLKEN_DSP */
 353 #define OMAP2420_EN_DSP_IPI_SHIFT                       1
 354 #define OMAP2420_EN_DSP_IPI                             (1 << 1)
 355
 356 /* CM_IDLEST_DSP */
 357 #define OMAP2420_ST_IVA                                 (1 << 8)
 358 #define OMAP2420_ST_IPI                                 (1 << 1)
 359 #define OMAP24XX_ST_DSP                                 (1 << 0)
 360
 361 /* CM_AUTOIDLE_DSP */
 362 #define OMAP2420_AUTO_DSP_IPI                           (1 << 1)
 363
 364 /* CM_CLKSEL_DSP */
 365 #define OMAP2420_SYNC_IVA                               (1 << 13)
 366 #define OMAP2420_CLKSEL_IVA_SHIFT                       8
 367 #define OMAP2420_CLKSEL_IVA_MASK                        (0x1f << 8)
 368 #define OMAP24XX_SYNC_DSP                               (1 << 7)
 369 #define OMAP24XX_CLKSEL_DSP_IF_SHIFT                    5
 370 #define OMAP24XX_CLKSEL_DSP_IF_MASK                     (0x3 << 5)
 371 #define OMAP24XX_CLKSEL_DSP_SHIFT                       0
 372 #define OMAP24XX_CLKSEL_DSP_MASK                        (0x1f << 0)
 373
 374 /* CM_CLKSTCTRL_DSP */
 375 #define OMAP2420_AUTOSTATE_IVA_SHIFT                    8
 376 #define OMAP2420_AUTOSTATE_IVA_MASK                     (1 << 8)
 377 #define OMAP24XX_AUTOSTATE_DSP_SHIFT                    0
 378 #define OMAP24XX_AUTOSTATE_DSP_MASK                     (1 << 0)
 379
 380 /* CM_FCLKEN_MDM */
 381 /* 2430 only */
 382 #define OMAP2430_EN_OSC_SHIFT                           1
 383 #define OMAP2430_EN_OSC                                 (1 << 1)
 384
 385 /* CM_ICLKEN_MDM */
 386 /* 2430 only */
 387 #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT             0
 388 #define OMAP2430_CM_ICLKEN_MDM_EN_MDM                   (1 << 0)
 389
 390 /* CM_IDLEST_MDM specific bits */
 391 /* 2430 only */
 392
 393 /* CM_AUTOIDLE_MDM */
 394 /* 2430 only */
 395 #define OMAP2430_AUTO_OSC                               (1 << 1)
 396 #define OMAP2430_AUTO_MDM                               (1 << 0)
 397
 398 /* CM_CLKSEL_MDM */
 399 /* 2430 only */
 400 #define OMAP2430_SYNC_MDM                               (1 << 4)
 401 #define OMAP2430_CLKSEL_MDM_SHIFT                       0
 402 #define OMAP2430_CLKSEL_MDM_MASK                        (0xf << 0)
 403
 404 /* CM_CLKSTCTRL_MDM */
 405 /* 2430 only */
 406 #define OMAP2430_AUTOSTATE_MDM_SHIFT                    0
 407 #define OMAP2430_AUTOSTATE_MDM_MASK                     (1 << 0)
 408
 409 #endif