2 * OMAP3 clock framework
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
22 #include <plat/control.h>
26 #include "cm-regbits-34xx.h"
28 #include "prm-regbits-34xx.h"
30 #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
32 static unsigned long omap3_dpll_recalc(struct clk
*clk
);
33 static unsigned long omap3_clkoutx2_recalc(struct clk
*clk
);
34 static void omap3_dpll_allow_idle(struct clk
*clk
);
35 static void omap3_dpll_deny_idle(struct clk
*clk
);
36 static u32
omap3_dpll_autoidle_read(struct clk
*clk
);
37 static int omap3_noncore_dpll_set_rate(struct clk
*clk
, unsigned long rate
);
38 static int omap3_dpll4_set_rate(struct clk
*clk
, unsigned long rate
);
39 static int omap3_core_dpll_m2_set_rate(struct clk
*clk
, unsigned long rate
);
41 /* Maximum DPLL multiplier, divider values for OMAP3 */
42 #define OMAP3_MAX_DPLL_MULT 2048
43 #define OMAP3_MAX_DPLL_DIV 128
46 * DPLL1 supplies clock to the MPU.
47 * DPLL2 supplies clock to the IVA2.
48 * DPLL3 supplies CORE domain clocks.
49 * DPLL4 supplies peripheral clocks.
50 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
53 /* Forward declarations for DPLL bypass clocks */
54 static struct clk dpll1_fck
;
55 static struct clk dpll2_fck
;
57 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
58 #define DPLL_LOW_POWER_STOP 0x1
59 #define DPLL_LOW_POWER_BYPASS 0x5
60 #define DPLL_LOCKED 0x7
64 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
65 static struct clk omap_32k_fck
= {
66 .name
= "omap_32k_fck",
72 static struct clk secure_32k_fck
= {
73 .name
= "secure_32k_fck",
79 /* Virtual source clocks for osc_sys_ck */
80 static struct clk virt_12m_ck
= {
81 .name
= "virt_12m_ck",
87 static struct clk virt_13m_ck
= {
88 .name
= "virt_13m_ck",
94 static struct clk virt_16_8m_ck
= {
95 .name
= "virt_16_8m_ck",
101 static struct clk virt_19_2m_ck
= {
102 .name
= "virt_19_2m_ck",
108 static struct clk virt_26m_ck
= {
109 .name
= "virt_26m_ck",
115 static struct clk virt_38_4m_ck
= {
116 .name
= "virt_38_4m_ck",
122 static const struct clksel_rate osc_sys_12m_rates
[] = {
123 { .div
= 1, .val
= 0, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
127 static const struct clksel_rate osc_sys_13m_rates
[] = {
128 { .div
= 1, .val
= 1, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
132 static const struct clksel_rate osc_sys_16_8m_rates
[] = {
133 { .div
= 1, .val
= 5, .flags
= RATE_IN_3430ES2
| DEFAULT_RATE
},
137 static const struct clksel_rate osc_sys_19_2m_rates
[] = {
138 { .div
= 1, .val
= 2, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
142 static const struct clksel_rate osc_sys_26m_rates
[] = {
143 { .div
= 1, .val
= 3, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
147 static const struct clksel_rate osc_sys_38_4m_rates
[] = {
148 { .div
= 1, .val
= 4, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
152 static const struct clksel osc_sys_clksel
[] = {
153 { .parent
= &virt_12m_ck
, .rates
= osc_sys_12m_rates
},
154 { .parent
= &virt_13m_ck
, .rates
= osc_sys_13m_rates
},
155 { .parent
= &virt_16_8m_ck
, .rates
= osc_sys_16_8m_rates
},
156 { .parent
= &virt_19_2m_ck
, .rates
= osc_sys_19_2m_rates
},
157 { .parent
= &virt_26m_ck
, .rates
= osc_sys_26m_rates
},
158 { .parent
= &virt_38_4m_ck
, .rates
= osc_sys_38_4m_rates
},
162 /* Oscillator clock */
163 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
164 static struct clk osc_sys_ck
= {
165 .name
= "osc_sys_ck",
167 .init
= &omap2_init_clksel_parent
,
168 .clksel_reg
= OMAP3430_PRM_CLKSEL
,
169 .clksel_mask
= OMAP3430_SYS_CLKIN_SEL_MASK
,
170 .clksel
= osc_sys_clksel
,
171 /* REVISIT: deal with autoextclkmode? */
173 .recalc
= &omap2_clksel_recalc
,
176 static const struct clksel_rate div2_rates
[] = {
177 { .div
= 1, .val
= 1, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
178 { .div
= 2, .val
= 2, .flags
= RATE_IN_343X
},
182 static const struct clksel sys_clksel
[] = {
183 { .parent
= &osc_sys_ck
, .rates
= div2_rates
},
187 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
188 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
189 static struct clk sys_ck
= {
192 .parent
= &osc_sys_ck
,
193 .init
= &omap2_init_clksel_parent
,
194 .clksel_reg
= OMAP3430_PRM_CLKSRC_CTRL
,
195 .clksel_mask
= OMAP_SYSCLKDIV_MASK
,
196 .clksel
= sys_clksel
,
197 .recalc
= &omap2_clksel_recalc
,
200 static struct clk sys_altclk
= {
201 .name
= "sys_altclk",
205 /* Optional external clock input for some McBSPs */
206 static struct clk mcbsp_clks
= {
207 .name
= "mcbsp_clks",
211 /* PRM EXTERNAL CLOCK OUTPUT */
213 static struct clk sys_clkout1
= {
214 .name
= "sys_clkout1",
215 .ops
= &clkops_omap2_dflt
,
216 .parent
= &osc_sys_ck
,
217 .enable_reg
= OMAP3430_PRM_CLKOUT_CTRL
,
218 .enable_bit
= OMAP3430_CLKOUT_EN_SHIFT
,
219 .recalc
= &followparent_recalc
,
226 static const struct clksel_rate div16_dpll_rates
[] = {
227 { .div
= 1, .val
= 1, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
228 { .div
= 2, .val
= 2, .flags
= RATE_IN_343X
},
229 { .div
= 3, .val
= 3, .flags
= RATE_IN_343X
},
230 { .div
= 4, .val
= 4, .flags
= RATE_IN_343X
},
231 { .div
= 5, .val
= 5, .flags
= RATE_IN_343X
},
232 { .div
= 6, .val
= 6, .flags
= RATE_IN_343X
},
233 { .div
= 7, .val
= 7, .flags
= RATE_IN_343X
},
234 { .div
= 8, .val
= 8, .flags
= RATE_IN_343X
},
235 { .div
= 9, .val
= 9, .flags
= RATE_IN_343X
},
236 { .div
= 10, .val
= 10, .flags
= RATE_IN_343X
},
237 { .div
= 11, .val
= 11, .flags
= RATE_IN_343X
},
238 { .div
= 12, .val
= 12, .flags
= RATE_IN_343X
},
239 { .div
= 13, .val
= 13, .flags
= RATE_IN_343X
},
240 { .div
= 14, .val
= 14, .flags
= RATE_IN_343X
},
241 { .div
= 15, .val
= 15, .flags
= RATE_IN_343X
},
242 { .div
= 16, .val
= 16, .flags
= RATE_IN_343X
},
247 /* MPU clock source */
249 static struct dpll_data dpll1_dd
= {
250 .mult_div1_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
251 .mult_mask
= OMAP3430_MPU_DPLL_MULT_MASK
,
252 .div1_mask
= OMAP3430_MPU_DPLL_DIV_MASK
,
253 .clk_bypass
= &dpll1_fck
,
255 .freqsel_mask
= OMAP3430_MPU_DPLL_FREQSEL_MASK
,
256 .control_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKEN_PLL
),
257 .enable_mask
= OMAP3430_EN_MPU_DPLL_MASK
,
258 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
259 .auto_recal_bit
= OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT
,
260 .recal_en_bit
= OMAP3430_MPU_DPLL_RECAL_EN_SHIFT
,
261 .recal_st_bit
= OMAP3430_MPU_DPLL_ST_SHIFT
,
262 .autoidle_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_AUTOIDLE_PLL
),
263 .autoidle_mask
= OMAP3430_AUTO_MPU_DPLL_MASK
,
264 .idlest_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_IDLEST_PLL
),
265 .idlest_mask
= OMAP3430_ST_MPU_CLK_MASK
,
266 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
268 .max_divider
= OMAP3_MAX_DPLL_DIV
,
269 .rate_tolerance
= DEFAULT_DPLL_RATE_TOLERANCE
272 static struct clk dpll1_ck
= {
276 .dpll_data
= &dpll1_dd
,
277 .round_rate
= &omap2_dpll_round_rate
,
278 .set_rate
= &omap3_noncore_dpll_set_rate
,
279 .clkdm_name
= "dpll1_clkdm",
280 .recalc
= &omap3_dpll_recalc
,
284 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
285 * DPLL isn't bypassed.
287 static struct clk dpll1_x2_ck
= {
288 .name
= "dpll1_x2_ck",
291 .clkdm_name
= "dpll1_clkdm",
292 .recalc
= &omap3_clkoutx2_recalc
,
295 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
296 static const struct clksel div16_dpll1_x2m2_clksel
[] = {
297 { .parent
= &dpll1_x2_ck
, .rates
= div16_dpll_rates
},
302 * Does not exist in the TRM - needed to separate the M2 divider from
303 * bypass selection in mpu_ck
305 static struct clk dpll1_x2m2_ck
= {
306 .name
= "dpll1_x2m2_ck",
308 .parent
= &dpll1_x2_ck
,
309 .init
= &omap2_init_clksel_parent
,
310 .clksel_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKSEL2_PLL
),
311 .clksel_mask
= OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK
,
312 .clksel
= div16_dpll1_x2m2_clksel
,
313 .clkdm_name
= "dpll1_clkdm",
314 .recalc
= &omap2_clksel_recalc
,
318 /* IVA2 clock source */
321 static struct dpll_data dpll2_dd
= {
322 .mult_div1_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
323 .mult_mask
= OMAP3430_IVA2_DPLL_MULT_MASK
,
324 .div1_mask
= OMAP3430_IVA2_DPLL_DIV_MASK
,
325 .clk_bypass
= &dpll2_fck
,
327 .freqsel_mask
= OMAP3430_IVA2_DPLL_FREQSEL_MASK
,
328 .control_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKEN_PLL
),
329 .enable_mask
= OMAP3430_EN_IVA2_DPLL_MASK
,
330 .modes
= (1 << DPLL_LOW_POWER_STOP
) | (1 << DPLL_LOCKED
) |
331 (1 << DPLL_LOW_POWER_BYPASS
),
332 .auto_recal_bit
= OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT
,
333 .recal_en_bit
= OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT
,
334 .recal_st_bit
= OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT
,
335 .autoidle_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_AUTOIDLE_PLL
),
336 .autoidle_mask
= OMAP3430_AUTO_IVA2_DPLL_MASK
,
337 .idlest_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_IDLEST_PLL
),
338 .idlest_mask
= OMAP3430_ST_IVA2_CLK_MASK
,
339 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
341 .max_divider
= OMAP3_MAX_DPLL_DIV
,
342 .rate_tolerance
= DEFAULT_DPLL_RATE_TOLERANCE
345 static struct clk dpll2_ck
= {
347 .ops
= &clkops_noncore_dpll_ops
,
349 .dpll_data
= &dpll2_dd
,
350 .round_rate
= &omap2_dpll_round_rate
,
351 .set_rate
= &omap3_noncore_dpll_set_rate
,
352 .clkdm_name
= "dpll2_clkdm",
353 .recalc
= &omap3_dpll_recalc
,
356 static const struct clksel div16_dpll2_m2x2_clksel
[] = {
357 { .parent
= &dpll2_ck
, .rates
= div16_dpll_rates
},
362 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
363 * or CLKOUTX2. CLKOUT seems most plausible.
365 static struct clk dpll2_m2_ck
= {
366 .name
= "dpll2_m2_ck",
369 .init
= &omap2_init_clksel_parent
,
370 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
,
371 OMAP3430_CM_CLKSEL2_PLL
),
372 .clksel_mask
= OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK
,
373 .clksel
= div16_dpll2_m2x2_clksel
,
374 .clkdm_name
= "dpll2_clkdm",
375 .recalc
= &omap2_clksel_recalc
,
380 * Source clock for all interfaces and for some device fclks
381 * REVISIT: Also supports fast relock bypass - not included below
383 static struct dpll_data dpll3_dd
= {
384 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
385 .mult_mask
= OMAP3430_CORE_DPLL_MULT_MASK
,
386 .div1_mask
= OMAP3430_CORE_DPLL_DIV_MASK
,
387 .clk_bypass
= &sys_ck
,
389 .freqsel_mask
= OMAP3430_CORE_DPLL_FREQSEL_MASK
,
390 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
391 .enable_mask
= OMAP3430_EN_CORE_DPLL_MASK
,
392 .auto_recal_bit
= OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT
,
393 .recal_en_bit
= OMAP3430_CORE_DPLL_RECAL_EN_SHIFT
,
394 .recal_st_bit
= OMAP3430_CORE_DPLL_ST_SHIFT
,
395 .autoidle_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_AUTOIDLE
),
396 .autoidle_mask
= OMAP3430_AUTO_CORE_DPLL_MASK
,
397 .idlest_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_IDLEST
),
398 .idlest_mask
= OMAP3430_ST_CORE_CLK_MASK
,
399 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
401 .max_divider
= OMAP3_MAX_DPLL_DIV
,
402 .rate_tolerance
= DEFAULT_DPLL_RATE_TOLERANCE
405 static struct clk dpll3_ck
= {
409 .dpll_data
= &dpll3_dd
,
410 .round_rate
= &omap2_dpll_round_rate
,
411 .clkdm_name
= "dpll3_clkdm",
412 .recalc
= &omap3_dpll_recalc
,
416 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
417 * DPLL isn't bypassed
419 static struct clk dpll3_x2_ck
= {
420 .name
= "dpll3_x2_ck",
423 .clkdm_name
= "dpll3_clkdm",
424 .recalc
= &omap3_clkoutx2_recalc
,
427 static const struct clksel_rate div31_dpll3_rates
[] = {
428 { .div
= 1, .val
= 1, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
429 { .div
= 2, .val
= 2, .flags
= RATE_IN_343X
},
430 { .div
= 3, .val
= 3, .flags
= RATE_IN_3430ES2
},
431 { .div
= 4, .val
= 4, .flags
= RATE_IN_3430ES2
},
432 { .div
= 5, .val
= 5, .flags
= RATE_IN_3430ES2
},
433 { .div
= 6, .val
= 6, .flags
= RATE_IN_3430ES2
},
434 { .div
= 7, .val
= 7, .flags
= RATE_IN_3430ES2
},
435 { .div
= 8, .val
= 8, .flags
= RATE_IN_3430ES2
},
436 { .div
= 9, .val
= 9, .flags
= RATE_IN_3430ES2
},
437 { .div
= 10, .val
= 10, .flags
= RATE_IN_3430ES2
},
438 { .div
= 11, .val
= 11, .flags
= RATE_IN_3430ES2
},
439 { .div
= 12, .val
= 12, .flags
= RATE_IN_3430ES2
},
440 { .div
= 13, .val
= 13, .flags
= RATE_IN_3430ES2
},
441 { .div
= 14, .val
= 14, .flags
= RATE_IN_3430ES2
},
442 { .div
= 15, .val
= 15, .flags
= RATE_IN_3430ES2
},
443 { .div
= 16, .val
= 16, .flags
= RATE_IN_3430ES2
},
444 { .div
= 17, .val
= 17, .flags
= RATE_IN_3430ES2
},
445 { .div
= 18, .val
= 18, .flags
= RATE_IN_3430ES2
},
446 { .div
= 19, .val
= 19, .flags
= RATE_IN_3430ES2
},
447 { .div
= 20, .val
= 20, .flags
= RATE_IN_3430ES2
},
448 { .div
= 21, .val
= 21, .flags
= RATE_IN_3430ES2
},
449 { .div
= 22, .val
= 22, .flags
= RATE_IN_3430ES2
},
450 { .div
= 23, .val
= 23, .flags
= RATE_IN_3430ES2
},
451 { .div
= 24, .val
= 24, .flags
= RATE_IN_3430ES2
},
452 { .div
= 25, .val
= 25, .flags
= RATE_IN_3430ES2
},
453 { .div
= 26, .val
= 26, .flags
= RATE_IN_3430ES2
},
454 { .div
= 27, .val
= 27, .flags
= RATE_IN_3430ES2
},
455 { .div
= 28, .val
= 28, .flags
= RATE_IN_3430ES2
},
456 { .div
= 29, .val
= 29, .flags
= RATE_IN_3430ES2
},
457 { .div
= 30, .val
= 30, .flags
= RATE_IN_3430ES2
},
458 { .div
= 31, .val
= 31, .flags
= RATE_IN_3430ES2
},
462 static const struct clksel div31_dpll3m2_clksel
[] = {
463 { .parent
= &dpll3_ck
, .rates
= div31_dpll3_rates
},
467 /* DPLL3 output M2 - primary control point for CORE speed */
468 static struct clk dpll3_m2_ck
= {
469 .name
= "dpll3_m2_ck",
472 .init
= &omap2_init_clksel_parent
,
473 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
474 .clksel_mask
= OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK
,
475 .clksel
= div31_dpll3m2_clksel
,
476 .clkdm_name
= "dpll3_clkdm",
477 .round_rate
= &omap2_clksel_round_rate
,
478 .set_rate
= &omap3_core_dpll_m2_set_rate
,
479 .recalc
= &omap2_clksel_recalc
,
482 static struct clk core_ck
= {
485 .parent
= &dpll3_m2_ck
,
486 .recalc
= &followparent_recalc
,
489 static struct clk dpll3_m2x2_ck
= {
490 .name
= "dpll3_m2x2_ck",
492 .parent
= &dpll3_m2_ck
,
493 .clkdm_name
= "dpll3_clkdm",
494 .recalc
= &omap3_clkoutx2_recalc
,
497 /* The PWRDN bit is apparently only available on 3430ES2 and above */
498 static const struct clksel div16_dpll3_clksel
[] = {
499 { .parent
= &dpll3_ck
, .rates
= div16_dpll_rates
},
503 /* This virtual clock is the source for dpll3_m3x2_ck */
504 static struct clk dpll3_m3_ck
= {
505 .name
= "dpll3_m3_ck",
508 .init
= &omap2_init_clksel_parent
,
509 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
510 .clksel_mask
= OMAP3430_DIV_DPLL3_MASK
,
511 .clksel
= div16_dpll3_clksel
,
512 .clkdm_name
= "dpll3_clkdm",
513 .recalc
= &omap2_clksel_recalc
,
516 /* The PWRDN bit is apparently only available on 3430ES2 and above */
517 static struct clk dpll3_m3x2_ck
= {
518 .name
= "dpll3_m3x2_ck",
519 .ops
= &clkops_omap2_dflt_wait
,
520 .parent
= &dpll3_m3_ck
,
521 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
522 .enable_bit
= OMAP3430_PWRDN_EMU_CORE_SHIFT
,
523 .flags
= INVERT_ENABLE
,
524 .clkdm_name
= "dpll3_clkdm",
525 .recalc
= &omap3_clkoutx2_recalc
,
528 static struct clk emu_core_alwon_ck
= {
529 .name
= "emu_core_alwon_ck",
531 .parent
= &dpll3_m3x2_ck
,
532 .clkdm_name
= "dpll3_clkdm",
533 .recalc
= &followparent_recalc
,
537 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
539 static struct dpll_data dpll4_dd
= {
540 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL2
),
541 .mult_mask
= OMAP3430_PERIPH_DPLL_MULT_MASK
,
542 .div1_mask
= OMAP3430_PERIPH_DPLL_DIV_MASK
,
543 .clk_bypass
= &sys_ck
,
545 .freqsel_mask
= OMAP3430_PERIPH_DPLL_FREQSEL_MASK
,
546 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
547 .enable_mask
= OMAP3430_EN_PERIPH_DPLL_MASK
,
548 .modes
= (1 << DPLL_LOW_POWER_STOP
) | (1 << DPLL_LOCKED
),
549 .auto_recal_bit
= OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT
,
550 .recal_en_bit
= OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT
,
551 .recal_st_bit
= OMAP3430_PERIPH_DPLL_ST_SHIFT
,
552 .autoidle_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_AUTOIDLE
),
553 .autoidle_mask
= OMAP3430_AUTO_PERIPH_DPLL_MASK
,
554 .idlest_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_IDLEST
),
555 .idlest_mask
= OMAP3430_ST_PERIPH_CLK_MASK
,
556 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
558 .max_divider
= OMAP3_MAX_DPLL_DIV
,
559 .rate_tolerance
= DEFAULT_DPLL_RATE_TOLERANCE
562 static struct clk dpll4_ck
= {
564 .ops
= &clkops_noncore_dpll_ops
,
566 .dpll_data
= &dpll4_dd
,
567 .round_rate
= &omap2_dpll_round_rate
,
568 .set_rate
= &omap3_dpll4_set_rate
,
569 .clkdm_name
= "dpll4_clkdm",
570 .recalc
= &omap3_dpll_recalc
,
574 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
575 * DPLL isn't bypassed --
576 * XXX does this serve any downstream clocks?
578 static struct clk dpll4_x2_ck
= {
579 .name
= "dpll4_x2_ck",
582 .clkdm_name
= "dpll4_clkdm",
583 .recalc
= &omap3_clkoutx2_recalc
,
586 static const struct clksel div16_dpll4_clksel
[] = {
587 { .parent
= &dpll4_ck
, .rates
= div16_dpll_rates
},
591 /* This virtual clock is the source for dpll4_m2x2_ck */
592 static struct clk dpll4_m2_ck
= {
593 .name
= "dpll4_m2_ck",
596 .init
= &omap2_init_clksel_parent
,
597 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430_CM_CLKSEL3
),
598 .clksel_mask
= OMAP3430_DIV_96M_MASK
,
599 .clksel
= div16_dpll4_clksel
,
600 .clkdm_name
= "dpll4_clkdm",
601 .recalc
= &omap2_clksel_recalc
,
604 /* The PWRDN bit is apparently only available on 3430ES2 and above */
605 static struct clk dpll4_m2x2_ck
= {
606 .name
= "dpll4_m2x2_ck",
607 .ops
= &clkops_omap2_dflt_wait
,
608 .parent
= &dpll4_m2_ck
,
609 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
610 .enable_bit
= OMAP3430_PWRDN_96M_SHIFT
,
611 .flags
= INVERT_ENABLE
,
612 .clkdm_name
= "dpll4_clkdm",
613 .recalc
= &omap3_clkoutx2_recalc
,
617 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
618 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
619 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
622 static struct clk omap_96m_alwon_fck
= {
623 .name
= "omap_96m_alwon_fck",
625 .parent
= &dpll4_m2x2_ck
,
626 .recalc
= &followparent_recalc
,
629 static struct clk cm_96m_fck
= {
630 .name
= "cm_96m_fck",
632 .parent
= &omap_96m_alwon_fck
,
633 .recalc
= &followparent_recalc
,
636 static const struct clksel_rate omap_96m_dpll_rates
[] = {
637 { .div
= 1, .val
= 0, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
641 static const struct clksel_rate omap_96m_sys_rates
[] = {
642 { .div
= 1, .val
= 1, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
646 static const struct clksel omap_96m_fck_clksel
[] = {
647 { .parent
= &cm_96m_fck
, .rates
= omap_96m_dpll_rates
},
648 { .parent
= &sys_ck
, .rates
= omap_96m_sys_rates
},
652 static struct clk omap_96m_fck
= {
653 .name
= "omap_96m_fck",
656 .init
= &omap2_init_clksel_parent
,
657 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
658 .clksel_mask
= OMAP3430_SOURCE_96M_MASK
,
659 .clksel
= omap_96m_fck_clksel
,
660 .recalc
= &omap2_clksel_recalc
,
663 /* This virtual clock is the source for dpll4_m3x2_ck */
664 static struct clk dpll4_m3_ck
= {
665 .name
= "dpll4_m3_ck",
668 .init
= &omap2_init_clksel_parent
,
669 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_CLKSEL
),
670 .clksel_mask
= OMAP3430_CLKSEL_TV_MASK
,
671 .clksel
= div16_dpll4_clksel
,
672 .clkdm_name
= "dpll4_clkdm",
673 .recalc
= &omap2_clksel_recalc
,
676 /* The PWRDN bit is apparently only available on 3430ES2 and above */
677 static struct clk dpll4_m3x2_ck
= {
678 .name
= "dpll4_m3x2_ck",
679 .ops
= &clkops_omap2_dflt_wait
,
680 .parent
= &dpll4_m3_ck
,
681 .init
= &omap2_init_clksel_parent
,
682 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
683 .enable_bit
= OMAP3430_PWRDN_TV_SHIFT
,
684 .flags
= INVERT_ENABLE
,
685 .clkdm_name
= "dpll4_clkdm",
686 .recalc
= &omap3_clkoutx2_recalc
,
689 static const struct clksel_rate omap_54m_d4m3x2_rates
[] = {
690 { .div
= 1, .val
= 0, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
694 static const struct clksel_rate omap_54m_alt_rates
[] = {
695 { .div
= 1, .val
= 1, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
699 static const struct clksel omap_54m_clksel
[] = {
700 { .parent
= &dpll4_m3x2_ck
, .rates
= omap_54m_d4m3x2_rates
},
701 { .parent
= &sys_altclk
, .rates
= omap_54m_alt_rates
},
705 static struct clk omap_54m_fck
= {
706 .name
= "omap_54m_fck",
708 .init
= &omap2_init_clksel_parent
,
709 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
710 .clksel_mask
= OMAP3430_SOURCE_54M_MASK
,
711 .clksel
= omap_54m_clksel
,
712 .recalc
= &omap2_clksel_recalc
,
715 static const struct clksel_rate omap_48m_cm96m_rates
[] = {
716 { .div
= 2, .val
= 0, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
720 static const struct clksel_rate omap_48m_alt_rates
[] = {
721 { .div
= 1, .val
= 1, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
725 static const struct clksel omap_48m_clksel
[] = {
726 { .parent
= &cm_96m_fck
, .rates
= omap_48m_cm96m_rates
},
727 { .parent
= &sys_altclk
, .rates
= omap_48m_alt_rates
},
731 static struct clk omap_48m_fck
= {
732 .name
= "omap_48m_fck",
734 .init
= &omap2_init_clksel_parent
,
735 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
736 .clksel_mask
= OMAP3430_SOURCE_48M_MASK
,
737 .clksel
= omap_48m_clksel
,
738 .recalc
= &omap2_clksel_recalc
,
741 static struct clk omap_12m_fck
= {
742 .name
= "omap_12m_fck",
744 .parent
= &omap_48m_fck
,
746 .recalc
= &omap2_fixed_divisor_recalc
,
749 /* This virstual clock is the source for dpll4_m4x2_ck */
750 static struct clk dpll4_m4_ck
= {
751 .name
= "dpll4_m4_ck",
754 .init
= &omap2_init_clksel_parent
,
755 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_CLKSEL
),
756 .clksel_mask
= OMAP3430_CLKSEL_DSS1_MASK
,
757 .clksel
= div16_dpll4_clksel
,
758 .clkdm_name
= "dpll4_clkdm",
759 .recalc
= &omap2_clksel_recalc
,
760 .set_rate
= &omap2_clksel_set_rate
,
761 .round_rate
= &omap2_clksel_round_rate
,
764 /* The PWRDN bit is apparently only available on 3430ES2 and above */
765 static struct clk dpll4_m4x2_ck
= {
766 .name
= "dpll4_m4x2_ck",
767 .ops
= &clkops_omap2_dflt_wait
,
768 .parent
= &dpll4_m4_ck
,
769 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
770 .enable_bit
= OMAP3430_PWRDN_CAM_SHIFT
,
771 .flags
= INVERT_ENABLE
,
772 .clkdm_name
= "dpll4_clkdm",
773 .recalc
= &omap3_clkoutx2_recalc
,
776 /* This virtual clock is the source for dpll4_m5x2_ck */
777 static struct clk dpll4_m5_ck
= {
778 .name
= "dpll4_m5_ck",
781 .init
= &omap2_init_clksel_parent
,
782 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_CLKSEL
),
783 .clksel_mask
= OMAP3430_CLKSEL_CAM_MASK
,
784 .clksel
= div16_dpll4_clksel
,
785 .clkdm_name
= "dpll4_clkdm",
786 .recalc
= &omap2_clksel_recalc
,
789 /* The PWRDN bit is apparently only available on 3430ES2 and above */
790 static struct clk dpll4_m5x2_ck
= {
791 .name
= "dpll4_m5x2_ck",
792 .ops
= &clkops_omap2_dflt_wait
,
793 .parent
= &dpll4_m5_ck
,
794 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
795 .enable_bit
= OMAP3430_PWRDN_CAM_SHIFT
,
796 .flags
= INVERT_ENABLE
,
797 .clkdm_name
= "dpll4_clkdm",
798 .recalc
= &omap3_clkoutx2_recalc
,
801 /* This virtual clock is the source for dpll4_m6x2_ck */
802 static struct clk dpll4_m6_ck
= {
803 .name
= "dpll4_m6_ck",
806 .init
= &omap2_init_clksel_parent
,
807 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
808 .clksel_mask
= OMAP3430_DIV_DPLL4_MASK
,
809 .clksel
= div16_dpll4_clksel
,
810 .clkdm_name
= "dpll4_clkdm",
811 .recalc
= &omap2_clksel_recalc
,
814 /* The PWRDN bit is apparently only available on 3430ES2 and above */
815 static struct clk dpll4_m6x2_ck
= {
816 .name
= "dpll4_m6x2_ck",
817 .ops
= &clkops_omap2_dflt_wait
,
818 .parent
= &dpll4_m6_ck
,
819 .init
= &omap2_init_clksel_parent
,
820 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
821 .enable_bit
= OMAP3430_PWRDN_EMU_PERIPH_SHIFT
,
822 .flags
= INVERT_ENABLE
,
823 .clkdm_name
= "dpll4_clkdm",
824 .recalc
= &omap3_clkoutx2_recalc
,
827 static struct clk emu_per_alwon_ck
= {
828 .name
= "emu_per_alwon_ck",
830 .parent
= &dpll4_m6x2_ck
,
831 .clkdm_name
= "dpll4_clkdm",
832 .recalc
= &followparent_recalc
,
836 /* Supplies 120MHz clock, USIM source clock */
839 static struct dpll_data dpll5_dd
= {
840 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_CLKSEL4
),
841 .mult_mask
= OMAP3430ES2_PERIPH2_DPLL_MULT_MASK
,
842 .div1_mask
= OMAP3430ES2_PERIPH2_DPLL_DIV_MASK
,
843 .clk_bypass
= &sys_ck
,
845 .freqsel_mask
= OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK
,
846 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_CLKEN2
),
847 .enable_mask
= OMAP3430ES2_EN_PERIPH2_DPLL_MASK
,
848 .modes
= (1 << DPLL_LOW_POWER_STOP
) | (1 << DPLL_LOCKED
),
849 .auto_recal_bit
= OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT
,
850 .recal_en_bit
= OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT
,
851 .recal_st_bit
= OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT
,
852 .autoidle_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_AUTOIDLE2_PLL
),
853 .autoidle_mask
= OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK
,
854 .idlest_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_IDLEST2
),
855 .idlest_mask
= OMAP3430ES2_ST_PERIPH2_CLK_MASK
,
856 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
858 .max_divider
= OMAP3_MAX_DPLL_DIV
,
859 .rate_tolerance
= DEFAULT_DPLL_RATE_TOLERANCE
862 static struct clk dpll5_ck
= {
864 .ops
= &clkops_noncore_dpll_ops
,
866 .dpll_data
= &dpll5_dd
,
867 .round_rate
= &omap2_dpll_round_rate
,
868 .set_rate
= &omap3_noncore_dpll_set_rate
,
869 .clkdm_name
= "dpll5_clkdm",
870 .recalc
= &omap3_dpll_recalc
,
873 static const struct clksel div16_dpll5_clksel
[] = {
874 { .parent
= &dpll5_ck
, .rates
= div16_dpll_rates
},
878 static struct clk dpll5_m2_ck
= {
879 .name
= "dpll5_m2_ck",
882 .init
= &omap2_init_clksel_parent
,
883 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_CLKSEL5
),
884 .clksel_mask
= OMAP3430ES2_DIV_120M_MASK
,
885 .clksel
= div16_dpll5_clksel
,
886 .clkdm_name
= "dpll5_clkdm",
887 .recalc
= &omap2_clksel_recalc
,
890 /* CM EXTERNAL CLOCK OUTPUTS */
892 static const struct clksel_rate clkout2_src_core_rates
[] = {
893 { .div
= 1, .val
= 0, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
897 static const struct clksel_rate clkout2_src_sys_rates
[] = {
898 { .div
= 1, .val
= 1, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
902 static const struct clksel_rate clkout2_src_96m_rates
[] = {
903 { .div
= 1, .val
= 2, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
907 static const struct clksel_rate clkout2_src_54m_rates
[] = {
908 { .div
= 1, .val
= 3, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
912 static const struct clksel clkout2_src_clksel
[] = {
913 { .parent
= &core_ck
, .rates
= clkout2_src_core_rates
},
914 { .parent
= &sys_ck
, .rates
= clkout2_src_sys_rates
},
915 { .parent
= &cm_96m_fck
, .rates
= clkout2_src_96m_rates
},
916 { .parent
= &omap_54m_fck
, .rates
= clkout2_src_54m_rates
},
920 static struct clk clkout2_src_ck
= {
921 .name
= "clkout2_src_ck",
922 .ops
= &clkops_omap2_dflt
,
923 .init
= &omap2_init_clksel_parent
,
924 .enable_reg
= OMAP3430_CM_CLKOUT_CTRL
,
925 .enable_bit
= OMAP3430_CLKOUT2_EN_SHIFT
,
926 .clksel_reg
= OMAP3430_CM_CLKOUT_CTRL
,
927 .clksel_mask
= OMAP3430_CLKOUT2SOURCE_MASK
,
928 .clksel
= clkout2_src_clksel
,
929 .clkdm_name
= "core_clkdm",
930 .recalc
= &omap2_clksel_recalc
,
933 static const struct clksel_rate sys_clkout2_rates
[] = {
934 { .div
= 1, .val
= 0, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
935 { .div
= 2, .val
= 1, .flags
= RATE_IN_343X
},
936 { .div
= 4, .val
= 2, .flags
= RATE_IN_343X
},
937 { .div
= 8, .val
= 3, .flags
= RATE_IN_343X
},
938 { .div
= 16, .val
= 4, .flags
= RATE_IN_343X
},
942 static const struct clksel sys_clkout2_clksel
[] = {
943 { .parent
= &clkout2_src_ck
, .rates
= sys_clkout2_rates
},
947 static struct clk sys_clkout2
= {
948 .name
= "sys_clkout2",
950 .init
= &omap2_init_clksel_parent
,
951 .clksel_reg
= OMAP3430_CM_CLKOUT_CTRL
,
952 .clksel_mask
= OMAP3430_CLKOUT2_DIV_MASK
,
953 .clksel
= sys_clkout2_clksel
,
954 .recalc
= &omap2_clksel_recalc
,
957 /* CM OUTPUT CLOCKS */
959 static struct clk corex2_fck
= {
960 .name
= "corex2_fck",
962 .parent
= &dpll3_m2x2_ck
,
963 .recalc
= &followparent_recalc
,
966 /* DPLL power domain clock controls */
968 static const struct clksel_rate div4_rates
[] = {
969 { .div
= 1, .val
= 1, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
970 { .div
= 2, .val
= 2, .flags
= RATE_IN_343X
},
971 { .div
= 4, .val
= 4, .flags
= RATE_IN_343X
},
975 static const struct clksel div4_core_clksel
[] = {
976 { .parent
= &core_ck
, .rates
= div4_rates
},
981 * REVISIT: Are these in DPLL power domain or CM power domain? docs
982 * may be inconsistent here?
984 static struct clk dpll1_fck
= {
988 .init
= &omap2_init_clksel_parent
,
989 .clksel_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
990 .clksel_mask
= OMAP3430_MPU_CLK_SRC_MASK
,
991 .clksel
= div4_core_clksel
,
992 .recalc
= &omap2_clksel_recalc
,
995 static struct clk mpu_ck
= {
998 .parent
= &dpll1_x2m2_ck
,
999 .clkdm_name
= "mpu_clkdm",
1000 .recalc
= &followparent_recalc
,
1003 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1004 static const struct clksel_rate arm_fck_rates
[] = {
1005 { .div
= 1, .val
= 0, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
1006 { .div
= 2, .val
= 1, .flags
= RATE_IN_343X
},
1010 static const struct clksel arm_fck_clksel
[] = {
1011 { .parent
= &mpu_ck
, .rates
= arm_fck_rates
},
1015 static struct clk arm_fck
= {
1017 .ops
= &clkops_null
,
1019 .init
= &omap2_init_clksel_parent
,
1020 .clksel_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_IDLEST_PLL
),
1021 .clksel_mask
= OMAP3430_ST_MPU_CLK_MASK
,
1022 .clksel
= arm_fck_clksel
,
1023 .clkdm_name
= "mpu_clkdm",
1024 .recalc
= &omap2_clksel_recalc
,
1027 /* XXX What about neon_clkdm ? */
1030 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1031 * although it is referenced - so this is a guess
1033 static struct clk emu_mpu_alwon_ck
= {
1034 .name
= "emu_mpu_alwon_ck",
1035 .ops
= &clkops_null
,
1037 .recalc
= &followparent_recalc
,
1040 static struct clk dpll2_fck
= {
1041 .name
= "dpll2_fck",
1042 .ops
= &clkops_null
,
1044 .init
= &omap2_init_clksel_parent
,
1045 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
1046 .clksel_mask
= OMAP3430_IVA2_CLK_SRC_MASK
,
1047 .clksel
= div4_core_clksel
,
1048 .recalc
= &omap2_clksel_recalc
,
1051 static struct clk iva2_ck
= {
1053 .ops
= &clkops_omap2_dflt_wait
,
1054 .parent
= &dpll2_m2_ck
,
1055 .init
= &omap2_init_clksel_parent
,
1056 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, CM_FCLKEN
),
1057 .enable_bit
= OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT
,
1058 .clkdm_name
= "iva2_clkdm",
1059 .recalc
= &followparent_recalc
,
1062 /* Common interface clocks */
1064 static const struct clksel div2_core_clksel
[] = {
1065 { .parent
= &core_ck
, .rates
= div2_rates
},
1069 static struct clk l3_ick
= {
1071 .ops
= &clkops_null
,
1073 .init
= &omap2_init_clksel_parent
,
1074 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1075 .clksel_mask
= OMAP3430_CLKSEL_L3_MASK
,
1076 .clksel
= div2_core_clksel
,
1077 .clkdm_name
= "core_l3_clkdm",
1078 .recalc
= &omap2_clksel_recalc
,
1081 static const struct clksel div2_l3_clksel
[] = {
1082 { .parent
= &l3_ick
, .rates
= div2_rates
},
1086 static struct clk l4_ick
= {
1088 .ops
= &clkops_null
,
1090 .init
= &omap2_init_clksel_parent
,
1091 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1092 .clksel_mask
= OMAP3430_CLKSEL_L4_MASK
,
1093 .clksel
= div2_l3_clksel
,
1094 .clkdm_name
= "core_l4_clkdm",
1095 .recalc
= &omap2_clksel_recalc
,
1099 static const struct clksel div2_l4_clksel
[] = {
1100 { .parent
= &l4_ick
, .rates
= div2_rates
},
1104 static struct clk rm_ick
= {
1106 .ops
= &clkops_null
,
1108 .init
= &omap2_init_clksel_parent
,
1109 .clksel_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_CLKSEL
),
1110 .clksel_mask
= OMAP3430_CLKSEL_RM_MASK
,
1111 .clksel
= div2_l4_clksel
,
1112 .recalc
= &omap2_clksel_recalc
,
1115 /* GFX power domain */
1117 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1119 static const struct clksel gfx_l3_clksel
[] = {
1120 { .parent
= &l3_ick
, .rates
= gfx_l3_rates
},
1124 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1125 static struct clk gfx_l3_ck
= {
1126 .name
= "gfx_l3_ck",
1127 .ops
= &clkops_omap2_dflt_wait
,
1129 .init
= &omap2_init_clksel_parent
,
1130 .enable_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_ICLKEN
),
1131 .enable_bit
= OMAP_EN_GFX_SHIFT
,
1132 .recalc
= &followparent_recalc
,
1135 static struct clk gfx_l3_fck
= {
1136 .name
= "gfx_l3_fck",
1137 .ops
= &clkops_null
,
1138 .parent
= &gfx_l3_ck
,
1139 .init
= &omap2_init_clksel_parent
,
1140 .clksel_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_CLKSEL
),
1141 .clksel_mask
= OMAP_CLKSEL_GFX_MASK
,
1142 .clksel
= gfx_l3_clksel
,
1143 .clkdm_name
= "gfx_3430es1_clkdm",
1144 .recalc
= &omap2_clksel_recalc
,
1147 static struct clk gfx_l3_ick
= {
1148 .name
= "gfx_l3_ick",
1149 .ops
= &clkops_null
,
1150 .parent
= &gfx_l3_ck
,
1151 .clkdm_name
= "gfx_3430es1_clkdm",
1152 .recalc
= &followparent_recalc
,
1155 static struct clk gfx_cg1_ck
= {
1156 .name
= "gfx_cg1_ck",
1157 .ops
= &clkops_omap2_dflt_wait
,
1158 .parent
= &gfx_l3_fck
, /* REVISIT: correct? */
1159 .enable_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_FCLKEN
),
1160 .enable_bit
= OMAP3430ES1_EN_2D_SHIFT
,
1161 .clkdm_name
= "gfx_3430es1_clkdm",
1162 .recalc
= &followparent_recalc
,
1165 static struct clk gfx_cg2_ck
= {
1166 .name
= "gfx_cg2_ck",
1167 .ops
= &clkops_omap2_dflt_wait
,
1168 .parent
= &gfx_l3_fck
, /* REVISIT: correct? */
1169 .enable_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_FCLKEN
),
1170 .enable_bit
= OMAP3430ES1_EN_3D_SHIFT
,
1171 .clkdm_name
= "gfx_3430es1_clkdm",
1172 .recalc
= &followparent_recalc
,
1175 /* SGX power domain - 3430ES2 only */
1177 static const struct clksel_rate sgx_core_rates
[] = {
1178 { .div
= 3, .val
= 0, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
1179 { .div
= 4, .val
= 1, .flags
= RATE_IN_343X
},
1180 { .div
= 6, .val
= 2, .flags
= RATE_IN_343X
},
1184 static const struct clksel_rate sgx_96m_rates
[] = {
1185 { .div
= 1, .val
= 3, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
1189 static const struct clksel sgx_clksel
[] = {
1190 { .parent
= &core_ck
, .rates
= sgx_core_rates
},
1191 { .parent
= &cm_96m_fck
, .rates
= sgx_96m_rates
},
1195 static struct clk sgx_fck
= {
1197 .ops
= &clkops_omap2_dflt_wait
,
1198 .init
= &omap2_init_clksel_parent
,
1199 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD
, CM_FCLKEN
),
1200 .enable_bit
= OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT
,
1201 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD
, CM_CLKSEL
),
1202 .clksel_mask
= OMAP3430ES2_CLKSEL_SGX_MASK
,
1203 .clksel
= sgx_clksel
,
1204 .clkdm_name
= "sgx_clkdm",
1205 .recalc
= &omap2_clksel_recalc
,
1208 static struct clk sgx_ick
= {
1210 .ops
= &clkops_omap2_dflt_wait
,
1212 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD
, CM_ICLKEN
),
1213 .enable_bit
= OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT
,
1214 .clkdm_name
= "sgx_clkdm",
1215 .recalc
= &followparent_recalc
,
1218 /* CORE power domain */
1220 static struct clk d2d_26m_fck
= {
1221 .name
= "d2d_26m_fck",
1222 .ops
= &clkops_omap2_dflt_wait
,
1224 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1225 .enable_bit
= OMAP3430ES1_EN_D2D_SHIFT
,
1226 .clkdm_name
= "d2d_clkdm",
1227 .recalc
= &followparent_recalc
,
1230 static struct clk modem_fck
= {
1231 .name
= "modem_fck",
1232 .ops
= &clkops_omap2_dflt_wait
,
1234 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1235 .enable_bit
= OMAP3430_EN_MODEM_SHIFT
,
1236 .clkdm_name
= "d2d_clkdm",
1237 .recalc
= &followparent_recalc
,
1240 static struct clk sad2d_ick
= {
1241 .name
= "sad2d_ick",
1242 .ops
= &clkops_omap2_dflt_wait
,
1244 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1245 .enable_bit
= OMAP3430_EN_SAD2D_SHIFT
,
1246 .clkdm_name
= "d2d_clkdm",
1247 .recalc
= &followparent_recalc
,
1250 static struct clk mad2d_ick
= {
1251 .name
= "mad2d_ick",
1252 .ops
= &clkops_omap2_dflt_wait
,
1254 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN3
),
1255 .enable_bit
= OMAP3430_EN_MAD2D_SHIFT
,
1256 .clkdm_name
= "d2d_clkdm",
1257 .recalc
= &followparent_recalc
,
1260 static const struct clksel omap343x_gpt_clksel
[] = {
1261 { .parent
= &omap_32k_fck
, .rates
= gpt_32k_rates
},
1262 { .parent
= &sys_ck
, .rates
= gpt_sys_rates
},
1266 static struct clk gpt10_fck
= {
1267 .name
= "gpt10_fck",
1268 .ops
= &clkops_omap2_dflt_wait
,
1270 .init
= &omap2_init_clksel_parent
,
1271 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1272 .enable_bit
= OMAP3430_EN_GPT10_SHIFT
,
1273 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1274 .clksel_mask
= OMAP3430_CLKSEL_GPT10_MASK
,
1275 .clksel
= omap343x_gpt_clksel
,
1276 .clkdm_name
= "core_l4_clkdm",
1277 .recalc
= &omap2_clksel_recalc
,
1280 static struct clk gpt11_fck
= {
1281 .name
= "gpt11_fck",
1282 .ops
= &clkops_omap2_dflt_wait
,
1284 .init
= &omap2_init_clksel_parent
,
1285 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1286 .enable_bit
= OMAP3430_EN_GPT11_SHIFT
,
1287 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1288 .clksel_mask
= OMAP3430_CLKSEL_GPT11_MASK
,
1289 .clksel
= omap343x_gpt_clksel
,
1290 .clkdm_name
= "core_l4_clkdm",
1291 .recalc
= &omap2_clksel_recalc
,
1294 static struct clk cpefuse_fck
= {
1295 .name
= "cpefuse_fck",
1296 .ops
= &clkops_omap2_dflt
,
1298 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP3430ES2_CM_FCLKEN3
),
1299 .enable_bit
= OMAP3430ES2_EN_CPEFUSE_SHIFT
,
1300 .recalc
= &followparent_recalc
,
1303 static struct clk ts_fck
= {
1305 .ops
= &clkops_omap2_dflt
,
1306 .parent
= &omap_32k_fck
,
1307 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP3430ES2_CM_FCLKEN3
),
1308 .enable_bit
= OMAP3430ES2_EN_TS_SHIFT
,
1309 .recalc
= &followparent_recalc
,
1312 static struct clk usbtll_fck
= {
1313 .name
= "usbtll_fck",
1314 .ops
= &clkops_omap2_dflt
,
1315 .parent
= &dpll5_m2_ck
,
1316 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP3430ES2_CM_FCLKEN3
),
1317 .enable_bit
= OMAP3430ES2_EN_USBTLL_SHIFT
,
1318 .recalc
= &followparent_recalc
,
1321 /* CORE 96M FCLK-derived clocks */
1323 static struct clk core_96m_fck
= {
1324 .name
= "core_96m_fck",
1325 .ops
= &clkops_null
,
1326 .parent
= &omap_96m_fck
,
1327 .clkdm_name
= "core_l4_clkdm",
1328 .recalc
= &followparent_recalc
,
1331 static struct clk mmchs3_fck
= {
1332 .name
= "mmchs_fck",
1333 .ops
= &clkops_omap2_dflt_wait
,
1335 .parent
= &core_96m_fck
,
1336 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1337 .enable_bit
= OMAP3430ES2_EN_MMC3_SHIFT
,
1338 .clkdm_name
= "core_l4_clkdm",
1339 .recalc
= &followparent_recalc
,
1342 static struct clk mmchs2_fck
= {
1343 .name
= "mmchs_fck",
1344 .ops
= &clkops_omap2_dflt_wait
,
1346 .parent
= &core_96m_fck
,
1347 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1348 .enable_bit
= OMAP3430_EN_MMC2_SHIFT
,
1349 .clkdm_name
= "core_l4_clkdm",
1350 .recalc
= &followparent_recalc
,
1353 static struct clk mspro_fck
= {
1354 .name
= "mspro_fck",
1355 .ops
= &clkops_omap2_dflt_wait
,
1356 .parent
= &core_96m_fck
,
1357 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1358 .enable_bit
= OMAP3430_EN_MSPRO_SHIFT
,
1359 .clkdm_name
= "core_l4_clkdm",
1360 .recalc
= &followparent_recalc
,
1363 static struct clk mmchs1_fck
= {
1364 .name
= "mmchs_fck",
1365 .ops
= &clkops_omap2_dflt_wait
,
1366 .parent
= &core_96m_fck
,
1367 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1368 .enable_bit
= OMAP3430_EN_MMC1_SHIFT
,
1369 .clkdm_name
= "core_l4_clkdm",
1370 .recalc
= &followparent_recalc
,
1373 static struct clk i2c3_fck
= {
1375 .ops
= &clkops_omap2_dflt_wait
,
1377 .parent
= &core_96m_fck
,
1378 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1379 .enable_bit
= OMAP3430_EN_I2C3_SHIFT
,
1380 .clkdm_name
= "core_l4_clkdm",
1381 .recalc
= &followparent_recalc
,
1384 static struct clk i2c2_fck
= {
1386 .ops
= &clkops_omap2_dflt_wait
,
1388 .parent
= &core_96m_fck
,
1389 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1390 .enable_bit
= OMAP3430_EN_I2C2_SHIFT
,
1391 .clkdm_name
= "core_l4_clkdm",
1392 .recalc
= &followparent_recalc
,
1395 static struct clk i2c1_fck
= {
1397 .ops
= &clkops_omap2_dflt_wait
,
1399 .parent
= &core_96m_fck
,
1400 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1401 .enable_bit
= OMAP3430_EN_I2C1_SHIFT
,
1402 .clkdm_name
= "core_l4_clkdm",
1403 .recalc
= &followparent_recalc
,
1407 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1408 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1410 static const struct clksel_rate common_mcbsp_96m_rates
[] = {
1411 { .div
= 1, .val
= 0, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
1415 static const struct clksel_rate common_mcbsp_mcbsp_rates
[] = {
1416 { .div
= 1, .val
= 1, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
1420 static const struct clksel mcbsp_15_clksel
[] = {
1421 { .parent
= &core_96m_fck
, .rates
= common_mcbsp_96m_rates
},
1422 { .parent
= &mcbsp_clks
, .rates
= common_mcbsp_mcbsp_rates
},
1426 static struct clk mcbsp5_fck
= {
1427 .name
= "mcbsp_fck",
1428 .ops
= &clkops_omap2_dflt_wait
,
1430 .init
= &omap2_init_clksel_parent
,
1431 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1432 .enable_bit
= OMAP3430_EN_MCBSP5_SHIFT
,
1433 .clksel_reg
= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1
),
1434 .clksel_mask
= OMAP2_MCBSP5_CLKS_MASK
,
1435 .clksel
= mcbsp_15_clksel
,
1436 .clkdm_name
= "core_l4_clkdm",
1437 .recalc
= &omap2_clksel_recalc
,
1440 static struct clk mcbsp1_fck
= {
1441 .name
= "mcbsp_fck",
1442 .ops
= &clkops_omap2_dflt_wait
,
1444 .init
= &omap2_init_clksel_parent
,
1445 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1446 .enable_bit
= OMAP3430_EN_MCBSP1_SHIFT
,
1447 .clksel_reg
= OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0
),
1448 .clksel_mask
= OMAP2_MCBSP1_CLKS_MASK
,
1449 .clksel
= mcbsp_15_clksel
,
1450 .clkdm_name
= "core_l4_clkdm",
1451 .recalc
= &omap2_clksel_recalc
,
1454 /* CORE_48M_FCK-derived clocks */
1456 static struct clk core_48m_fck
= {
1457 .name
= "core_48m_fck",
1458 .ops
= &clkops_null
,
1459 .parent
= &omap_48m_fck
,
1460 .clkdm_name
= "core_l4_clkdm",
1461 .recalc
= &followparent_recalc
,
1464 static struct clk mcspi4_fck
= {
1465 .name
= "mcspi_fck",
1466 .ops
= &clkops_omap2_dflt_wait
,
1468 .parent
= &core_48m_fck
,
1469 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1470 .enable_bit
= OMAP3430_EN_MCSPI4_SHIFT
,
1471 .recalc
= &followparent_recalc
,
1474 static struct clk mcspi3_fck
= {
1475 .name
= "mcspi_fck",
1476 .ops
= &clkops_omap2_dflt_wait
,
1478 .parent
= &core_48m_fck
,
1479 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1480 .enable_bit
= OMAP3430_EN_MCSPI3_SHIFT
,
1481 .recalc
= &followparent_recalc
,
1484 static struct clk mcspi2_fck
= {
1485 .name
= "mcspi_fck",
1486 .ops
= &clkops_omap2_dflt_wait
,
1488 .parent
= &core_48m_fck
,
1489 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1490 .enable_bit
= OMAP3430_EN_MCSPI2_SHIFT
,
1491 .recalc
= &followparent_recalc
,
1494 static struct clk mcspi1_fck
= {
1495 .name
= "mcspi_fck",
1496 .ops
= &clkops_omap2_dflt_wait
,
1498 .parent
= &core_48m_fck
,
1499 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1500 .enable_bit
= OMAP3430_EN_MCSPI1_SHIFT
,
1501 .recalc
= &followparent_recalc
,
1504 static struct clk uart2_fck
= {
1505 .name
= "uart2_fck",
1506 .ops
= &clkops_omap2_dflt_wait
,
1507 .parent
= &core_48m_fck
,
1508 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1509 .enable_bit
= OMAP3430_EN_UART2_SHIFT
,
1510 .recalc
= &followparent_recalc
,
1513 static struct clk uart1_fck
= {
1514 .name
= "uart1_fck",
1515 .ops
= &clkops_omap2_dflt_wait
,
1516 .parent
= &core_48m_fck
,
1517 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1518 .enable_bit
= OMAP3430_EN_UART1_SHIFT
,
1519 .recalc
= &followparent_recalc
,
1522 static struct clk fshostusb_fck
= {
1523 .name
= "fshostusb_fck",
1524 .ops
= &clkops_omap2_dflt_wait
,
1525 .parent
= &core_48m_fck
,
1526 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1527 .enable_bit
= OMAP3430ES1_EN_FSHOSTUSB_SHIFT
,
1528 .recalc
= &followparent_recalc
,
1531 /* CORE_12M_FCK based clocks */
1533 static struct clk core_12m_fck
= {
1534 .name
= "core_12m_fck",
1535 .ops
= &clkops_null
,
1536 .parent
= &omap_12m_fck
,
1537 .clkdm_name
= "core_l4_clkdm",
1538 .recalc
= &followparent_recalc
,
1541 static struct clk hdq_fck
= {
1543 .ops
= &clkops_omap2_dflt_wait
,
1544 .parent
= &core_12m_fck
,
1545 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1546 .enable_bit
= OMAP3430_EN_HDQ_SHIFT
,
1547 .recalc
= &followparent_recalc
,
1550 /* DPLL3-derived clock */
1552 static const struct clksel_rate ssi_ssr_corex2_rates
[] = {
1553 { .div
= 1, .val
= 1, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
1554 { .div
= 2, .val
= 2, .flags
= RATE_IN_343X
},
1555 { .div
= 3, .val
= 3, .flags
= RATE_IN_343X
},
1556 { .div
= 4, .val
= 4, .flags
= RATE_IN_343X
},
1557 { .div
= 6, .val
= 6, .flags
= RATE_IN_343X
},
1558 { .div
= 8, .val
= 8, .flags
= RATE_IN_343X
},
1562 static const struct clksel ssi_ssr_clksel
[] = {
1563 { .parent
= &corex2_fck
, .rates
= ssi_ssr_corex2_rates
},
1567 static struct clk ssi_ssr_fck_3430es1
= {
1568 .name
= "ssi_ssr_fck",
1569 .ops
= &clkops_omap2_dflt
,
1570 .init
= &omap2_init_clksel_parent
,
1571 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1572 .enable_bit
= OMAP3430_EN_SSI_SHIFT
,
1573 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1574 .clksel_mask
= OMAP3430_CLKSEL_SSI_MASK
,
1575 .clksel
= ssi_ssr_clksel
,
1576 .clkdm_name
= "core_l4_clkdm",
1577 .recalc
= &omap2_clksel_recalc
,
1580 static struct clk ssi_ssr_fck_3430es2
= {
1581 .name
= "ssi_ssr_fck",
1582 .ops
= &clkops_omap3430es2_ssi_wait
,
1583 .init
= &omap2_init_clksel_parent
,
1584 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1585 .enable_bit
= OMAP3430_EN_SSI_SHIFT
,
1586 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1587 .clksel_mask
= OMAP3430_CLKSEL_SSI_MASK
,
1588 .clksel
= ssi_ssr_clksel
,
1589 .clkdm_name
= "core_l4_clkdm",
1590 .recalc
= &omap2_clksel_recalc
,
1593 static struct clk ssi_sst_fck_3430es1
= {
1594 .name
= "ssi_sst_fck",
1595 .ops
= &clkops_null
,
1596 .parent
= &ssi_ssr_fck_3430es1
,
1598 .recalc
= &omap2_fixed_divisor_recalc
,
1601 static struct clk ssi_sst_fck_3430es2
= {
1602 .name
= "ssi_sst_fck",
1603 .ops
= &clkops_null
,
1604 .parent
= &ssi_ssr_fck_3430es2
,
1606 .recalc
= &omap2_fixed_divisor_recalc
,
1611 /* CORE_L3_ICK based clocks */
1614 * XXX must add clk_enable/clk_disable for these if standard code won't
1617 static struct clk core_l3_ick
= {
1618 .name
= "core_l3_ick",
1619 .ops
= &clkops_null
,
1621 .clkdm_name
= "core_l3_clkdm",
1622 .recalc
= &followparent_recalc
,
1625 static struct clk hsotgusb_ick_3430es1
= {
1626 .name
= "hsotgusb_ick",
1627 .ops
= &clkops_omap2_dflt
,
1628 .parent
= &core_l3_ick
,
1629 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1630 .enable_bit
= OMAP3430_EN_HSOTGUSB_SHIFT
,
1631 .clkdm_name
= "core_l3_clkdm",
1632 .recalc
= &followparent_recalc
,
1635 static struct clk hsotgusb_ick_3430es2
= {
1636 .name
= "hsotgusb_ick",
1637 .ops
= &clkops_omap3430es2_hsotgusb_wait
,
1638 .parent
= &core_l3_ick
,
1639 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1640 .enable_bit
= OMAP3430_EN_HSOTGUSB_SHIFT
,
1641 .clkdm_name
= "core_l3_clkdm",
1642 .recalc
= &followparent_recalc
,
1645 static struct clk sdrc_ick
= {
1647 .ops
= &clkops_omap2_dflt_wait
,
1648 .parent
= &core_l3_ick
,
1649 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1650 .enable_bit
= OMAP3430_EN_SDRC_SHIFT
,
1651 .flags
= ENABLE_ON_INIT
,
1652 .clkdm_name
= "core_l3_clkdm",
1653 .recalc
= &followparent_recalc
,
1656 static struct clk gpmc_fck
= {
1658 .ops
= &clkops_null
,
1659 .parent
= &core_l3_ick
,
1660 .flags
= ENABLE_ON_INIT
, /* huh? */
1661 .clkdm_name
= "core_l3_clkdm",
1662 .recalc
= &followparent_recalc
,
1665 /* SECURITY_L3_ICK based clocks */
1667 static struct clk security_l3_ick
= {
1668 .name
= "security_l3_ick",
1669 .ops
= &clkops_null
,
1671 .recalc
= &followparent_recalc
,
1674 static struct clk pka_ick
= {
1676 .ops
= &clkops_omap2_dflt_wait
,
1677 .parent
= &security_l3_ick
,
1678 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
1679 .enable_bit
= OMAP3430_EN_PKA_SHIFT
,
1680 .recalc
= &followparent_recalc
,
1683 /* CORE_L4_ICK based clocks */
1685 static struct clk core_l4_ick
= {
1686 .name
= "core_l4_ick",
1687 .ops
= &clkops_null
,
1689 .clkdm_name
= "core_l4_clkdm",
1690 .recalc
= &followparent_recalc
,
1693 static struct clk usbtll_ick
= {
1694 .name
= "usbtll_ick",
1695 .ops
= &clkops_omap2_dflt_wait
,
1696 .parent
= &core_l4_ick
,
1697 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN3
),
1698 .enable_bit
= OMAP3430ES2_EN_USBTLL_SHIFT
,
1699 .clkdm_name
= "core_l4_clkdm",
1700 .recalc
= &followparent_recalc
,
1703 static struct clk mmchs3_ick
= {
1704 .name
= "mmchs_ick",
1705 .ops
= &clkops_omap2_dflt_wait
,
1707 .parent
= &core_l4_ick
,
1708 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1709 .enable_bit
= OMAP3430ES2_EN_MMC3_SHIFT
,
1710 .clkdm_name
= "core_l4_clkdm",
1711 .recalc
= &followparent_recalc
,
1714 /* Intersystem Communication Registers - chassis mode only */
1715 static struct clk icr_ick
= {
1717 .ops
= &clkops_omap2_dflt_wait
,
1718 .parent
= &core_l4_ick
,
1719 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1720 .enable_bit
= OMAP3430_EN_ICR_SHIFT
,
1721 .clkdm_name
= "core_l4_clkdm",
1722 .recalc
= &followparent_recalc
,
1725 static struct clk aes2_ick
= {
1727 .ops
= &clkops_omap2_dflt_wait
,
1728 .parent
= &core_l4_ick
,
1729 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1730 .enable_bit
= OMAP3430_EN_AES2_SHIFT
,
1731 .clkdm_name
= "core_l4_clkdm",
1732 .recalc
= &followparent_recalc
,
1735 static struct clk sha12_ick
= {
1736 .name
= "sha12_ick",
1737 .ops
= &clkops_omap2_dflt_wait
,
1738 .parent
= &core_l4_ick
,
1739 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1740 .enable_bit
= OMAP3430_EN_SHA12_SHIFT
,
1741 .clkdm_name
= "core_l4_clkdm",
1742 .recalc
= &followparent_recalc
,
1745 static struct clk des2_ick
= {
1747 .ops
= &clkops_omap2_dflt_wait
,
1748 .parent
= &core_l4_ick
,
1749 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1750 .enable_bit
= OMAP3430_EN_DES2_SHIFT
,
1751 .clkdm_name
= "core_l4_clkdm",
1752 .recalc
= &followparent_recalc
,
1755 static struct clk mmchs2_ick
= {
1756 .name
= "mmchs_ick",
1757 .ops
= &clkops_omap2_dflt_wait
,
1759 .parent
= &core_l4_ick
,
1760 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1761 .enable_bit
= OMAP3430_EN_MMC2_SHIFT
,
1762 .clkdm_name
= "core_l4_clkdm",
1763 .recalc
= &followparent_recalc
,
1766 static struct clk mmchs1_ick
= {
1767 .name
= "mmchs_ick",
1768 .ops
= &clkops_omap2_dflt_wait
,
1769 .parent
= &core_l4_ick
,
1770 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1771 .enable_bit
= OMAP3430_EN_MMC1_SHIFT
,
1772 .clkdm_name
= "core_l4_clkdm",
1773 .recalc
= &followparent_recalc
,
1776 static struct clk mspro_ick
= {
1777 .name
= "mspro_ick",
1778 .ops
= &clkops_omap2_dflt_wait
,
1779 .parent
= &core_l4_ick
,
1780 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1781 .enable_bit
= OMAP3430_EN_MSPRO_SHIFT
,
1782 .clkdm_name
= "core_l4_clkdm",
1783 .recalc
= &followparent_recalc
,
1786 static struct clk hdq_ick
= {
1788 .ops
= &clkops_omap2_dflt_wait
,
1789 .parent
= &core_l4_ick
,
1790 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1791 .enable_bit
= OMAP3430_EN_HDQ_SHIFT
,
1792 .clkdm_name
= "core_l4_clkdm",
1793 .recalc
= &followparent_recalc
,
1796 static struct clk mcspi4_ick
= {
1797 .name
= "mcspi_ick",
1798 .ops
= &clkops_omap2_dflt_wait
,
1800 .parent
= &core_l4_ick
,
1801 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1802 .enable_bit
= OMAP3430_EN_MCSPI4_SHIFT
,
1803 .clkdm_name
= "core_l4_clkdm",
1804 .recalc
= &followparent_recalc
,
1807 static struct clk mcspi3_ick
= {
1808 .name
= "mcspi_ick",
1809 .ops
= &clkops_omap2_dflt_wait
,
1811 .parent
= &core_l4_ick
,
1812 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1813 .enable_bit
= OMAP3430_EN_MCSPI3_SHIFT
,
1814 .clkdm_name
= "core_l4_clkdm",
1815 .recalc
= &followparent_recalc
,
1818 static struct clk mcspi2_ick
= {
1819 .name
= "mcspi_ick",
1820 .ops
= &clkops_omap2_dflt_wait
,
1822 .parent
= &core_l4_ick
,
1823 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1824 .enable_bit
= OMAP3430_EN_MCSPI2_SHIFT
,
1825 .clkdm_name
= "core_l4_clkdm",
1826 .recalc
= &followparent_recalc
,
1829 static struct clk mcspi1_ick
= {
1830 .name
= "mcspi_ick",
1831 .ops
= &clkops_omap2_dflt_wait
,
1833 .parent
= &core_l4_ick
,
1834 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1835 .enable_bit
= OMAP3430_EN_MCSPI1_SHIFT
,
1836 .clkdm_name
= "core_l4_clkdm",
1837 .recalc
= &followparent_recalc
,
1840 static struct clk i2c3_ick
= {
1842 .ops
= &clkops_omap2_dflt_wait
,
1844 .parent
= &core_l4_ick
,
1845 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1846 .enable_bit
= OMAP3430_EN_I2C3_SHIFT
,
1847 .clkdm_name
= "core_l4_clkdm",
1848 .recalc
= &followparent_recalc
,
1851 static struct clk i2c2_ick
= {
1853 .ops
= &clkops_omap2_dflt_wait
,
1855 .parent
= &core_l4_ick
,
1856 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1857 .enable_bit
= OMAP3430_EN_I2C2_SHIFT
,
1858 .clkdm_name
= "core_l4_clkdm",
1859 .recalc
= &followparent_recalc
,
1862 static struct clk i2c1_ick
= {
1864 .ops
= &clkops_omap2_dflt_wait
,
1866 .parent
= &core_l4_ick
,
1867 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1868 .enable_bit
= OMAP3430_EN_I2C1_SHIFT
,
1869 .clkdm_name
= "core_l4_clkdm",
1870 .recalc
= &followparent_recalc
,
1873 static struct clk uart2_ick
= {
1874 .name
= "uart2_ick",
1875 .ops
= &clkops_omap2_dflt_wait
,
1876 .parent
= &core_l4_ick
,
1877 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1878 .enable_bit
= OMAP3430_EN_UART2_SHIFT
,
1879 .clkdm_name
= "core_l4_clkdm",
1880 .recalc
= &followparent_recalc
,
1883 static struct clk uart1_ick
= {
1884 .name
= "uart1_ick",
1885 .ops
= &clkops_omap2_dflt_wait
,
1886 .parent
= &core_l4_ick
,
1887 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1888 .enable_bit
= OMAP3430_EN_UART1_SHIFT
,
1889 .clkdm_name
= "core_l4_clkdm",
1890 .recalc
= &followparent_recalc
,
1893 static struct clk gpt11_ick
= {
1894 .name
= "gpt11_ick",
1895 .ops
= &clkops_omap2_dflt_wait
,
1896 .parent
= &core_l4_ick
,
1897 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1898 .enable_bit
= OMAP3430_EN_GPT11_SHIFT
,
1899 .clkdm_name
= "core_l4_clkdm",
1900 .recalc
= &followparent_recalc
,
1903 static struct clk gpt10_ick
= {
1904 .name
= "gpt10_ick",
1905 .ops
= &clkops_omap2_dflt_wait
,
1906 .parent
= &core_l4_ick
,
1907 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1908 .enable_bit
= OMAP3430_EN_GPT10_SHIFT
,
1909 .clkdm_name
= "core_l4_clkdm",
1910 .recalc
= &followparent_recalc
,
1913 static struct clk mcbsp5_ick
= {
1914 .name
= "mcbsp_ick",
1915 .ops
= &clkops_omap2_dflt_wait
,
1917 .parent
= &core_l4_ick
,
1918 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1919 .enable_bit
= OMAP3430_EN_MCBSP5_SHIFT
,
1920 .clkdm_name
= "core_l4_clkdm",
1921 .recalc
= &followparent_recalc
,
1924 static struct clk mcbsp1_ick
= {
1925 .name
= "mcbsp_ick",
1926 .ops
= &clkops_omap2_dflt_wait
,
1928 .parent
= &core_l4_ick
,
1929 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1930 .enable_bit
= OMAP3430_EN_MCBSP1_SHIFT
,
1931 .clkdm_name
= "core_l4_clkdm",
1932 .recalc
= &followparent_recalc
,
1935 static struct clk fac_ick
= {
1937 .ops
= &clkops_omap2_dflt_wait
,
1938 .parent
= &core_l4_ick
,
1939 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1940 .enable_bit
= OMAP3430ES1_EN_FAC_SHIFT
,
1941 .clkdm_name
= "core_l4_clkdm",
1942 .recalc
= &followparent_recalc
,
1945 static struct clk mailboxes_ick
= {
1946 .name
= "mailboxes_ick",
1947 .ops
= &clkops_omap2_dflt_wait
,
1948 .parent
= &core_l4_ick
,
1949 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1950 .enable_bit
= OMAP3430_EN_MAILBOXES_SHIFT
,
1951 .clkdm_name
= "core_l4_clkdm",
1952 .recalc
= &followparent_recalc
,
1955 static struct clk omapctrl_ick
= {
1956 .name
= "omapctrl_ick",
1957 .ops
= &clkops_omap2_dflt_wait
,
1958 .parent
= &core_l4_ick
,
1959 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1960 .enable_bit
= OMAP3430_EN_OMAPCTRL_SHIFT
,
1961 .flags
= ENABLE_ON_INIT
,
1962 .recalc
= &followparent_recalc
,
1965 /* SSI_L4_ICK based clocks */
1967 static struct clk ssi_l4_ick
= {
1968 .name
= "ssi_l4_ick",
1969 .ops
= &clkops_null
,
1971 .clkdm_name
= "core_l4_clkdm",
1972 .recalc
= &followparent_recalc
,
1975 static struct clk ssi_ick_3430es1
= {
1977 .ops
= &clkops_omap2_dflt
,
1978 .parent
= &ssi_l4_ick
,
1979 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1980 .enable_bit
= OMAP3430_EN_SSI_SHIFT
,
1981 .clkdm_name
= "core_l4_clkdm",
1982 .recalc
= &followparent_recalc
,
1985 static struct clk ssi_ick_3430es2
= {
1987 .ops
= &clkops_omap3430es2_ssi_wait
,
1988 .parent
= &ssi_l4_ick
,
1989 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1990 .enable_bit
= OMAP3430_EN_SSI_SHIFT
,
1991 .clkdm_name
= "core_l4_clkdm",
1992 .recalc
= &followparent_recalc
,
1995 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1996 * but l4_ick makes more sense to me */
1998 static const struct clksel usb_l4_clksel
[] = {
1999 { .parent
= &l4_ick
, .rates
= div2_rates
},
2003 static struct clk usb_l4_ick
= {
2004 .name
= "usb_l4_ick",
2005 .ops
= &clkops_omap2_dflt_wait
,
2007 .init
= &omap2_init_clksel_parent
,
2008 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2009 .enable_bit
= OMAP3430ES1_EN_FSHOSTUSB_SHIFT
,
2010 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
2011 .clksel_mask
= OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK
,
2012 .clksel
= usb_l4_clksel
,
2013 .recalc
= &omap2_clksel_recalc
,
2016 /* SECURITY_L4_ICK2 based clocks */
2018 static struct clk security_l4_ick2
= {
2019 .name
= "security_l4_ick2",
2020 .ops
= &clkops_null
,
2022 .recalc
= &followparent_recalc
,
2025 static struct clk aes1_ick
= {
2027 .ops
= &clkops_omap2_dflt_wait
,
2028 .parent
= &security_l4_ick2
,
2029 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
2030 .enable_bit
= OMAP3430_EN_AES1_SHIFT
,
2031 .recalc
= &followparent_recalc
,
2034 static struct clk rng_ick
= {
2036 .ops
= &clkops_omap2_dflt_wait
,
2037 .parent
= &security_l4_ick2
,
2038 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
2039 .enable_bit
= OMAP3430_EN_RNG_SHIFT
,
2040 .recalc
= &followparent_recalc
,
2043 static struct clk sha11_ick
= {
2044 .name
= "sha11_ick",
2045 .ops
= &clkops_omap2_dflt_wait
,
2046 .parent
= &security_l4_ick2
,
2047 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
2048 .enable_bit
= OMAP3430_EN_SHA11_SHIFT
,
2049 .recalc
= &followparent_recalc
,
2052 static struct clk des1_ick
= {
2054 .ops
= &clkops_omap2_dflt_wait
,
2055 .parent
= &security_l4_ick2
,
2056 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
2057 .enable_bit
= OMAP3430_EN_DES1_SHIFT
,
2058 .recalc
= &followparent_recalc
,
2062 static struct clk dss1_alwon_fck_3430es1
= {
2063 .name
= "dss1_alwon_fck",
2064 .ops
= &clkops_omap2_dflt
,
2065 .parent
= &dpll4_m4x2_ck
,
2066 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
2067 .enable_bit
= OMAP3430_EN_DSS1_SHIFT
,
2068 .clkdm_name
= "dss_clkdm",
2069 .recalc
= &followparent_recalc
,
2072 static struct clk dss1_alwon_fck_3430es2
= {
2073 .name
= "dss1_alwon_fck",
2074 .ops
= &clkops_omap3430es2_dss_usbhost_wait
,
2075 .parent
= &dpll4_m4x2_ck
,
2076 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
2077 .enable_bit
= OMAP3430_EN_DSS1_SHIFT
,
2078 .clkdm_name
= "dss_clkdm",
2079 .recalc
= &followparent_recalc
,
2082 static struct clk dss_tv_fck
= {
2083 .name
= "dss_tv_fck",
2084 .ops
= &clkops_omap2_dflt
,
2085 .parent
= &omap_54m_fck
,
2086 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
2087 .enable_bit
= OMAP3430_EN_TV_SHIFT
,
2088 .clkdm_name
= "dss_clkdm",
2089 .recalc
= &followparent_recalc
,
2092 static struct clk dss_96m_fck
= {
2093 .name
= "dss_96m_fck",
2094 .ops
= &clkops_omap2_dflt
,
2095 .parent
= &omap_96m_fck
,
2096 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
2097 .enable_bit
= OMAP3430_EN_TV_SHIFT
,
2098 .clkdm_name
= "dss_clkdm",
2099 .recalc
= &followparent_recalc
,
2102 static struct clk dss2_alwon_fck
= {
2103 .name
= "dss2_alwon_fck",
2104 .ops
= &clkops_omap2_dflt
,
2106 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
2107 .enable_bit
= OMAP3430_EN_DSS2_SHIFT
,
2108 .clkdm_name
= "dss_clkdm",
2109 .recalc
= &followparent_recalc
,
2112 static struct clk dss_ick_3430es1
= {
2113 /* Handles both L3 and L4 clocks */
2115 .ops
= &clkops_omap2_dflt
,
2117 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_ICLKEN
),
2118 .enable_bit
= OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT
,
2119 .clkdm_name
= "dss_clkdm",
2120 .recalc
= &followparent_recalc
,
2123 static struct clk dss_ick_3430es2
= {
2124 /* Handles both L3 and L4 clocks */
2126 .ops
= &clkops_omap3430es2_dss_usbhost_wait
,
2128 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_ICLKEN
),
2129 .enable_bit
= OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT
,
2130 .clkdm_name
= "dss_clkdm",
2131 .recalc
= &followparent_recalc
,
2136 static struct clk cam_mclk
= {
2138 .ops
= &clkops_omap2_dflt
,
2139 .parent
= &dpll4_m5x2_ck
,
2140 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_FCLKEN
),
2141 .enable_bit
= OMAP3430_EN_CAM_SHIFT
,
2142 .clkdm_name
= "cam_clkdm",
2143 .recalc
= &followparent_recalc
,
2146 static struct clk cam_ick
= {
2147 /* Handles both L3 and L4 clocks */
2149 .ops
= &clkops_omap2_dflt
,
2151 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_ICLKEN
),
2152 .enable_bit
= OMAP3430_EN_CAM_SHIFT
,
2153 .clkdm_name
= "cam_clkdm",
2154 .recalc
= &followparent_recalc
,
2157 static struct clk csi2_96m_fck
= {
2158 .name
= "csi2_96m_fck",
2159 .ops
= &clkops_omap2_dflt
,
2160 .parent
= &core_96m_fck
,
2161 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_FCLKEN
),
2162 .enable_bit
= OMAP3430_EN_CSI2_SHIFT
,
2163 .clkdm_name
= "cam_clkdm",
2164 .recalc
= &followparent_recalc
,
2167 /* USBHOST - 3430ES2 only */
2169 static struct clk usbhost_120m_fck
= {
2170 .name
= "usbhost_120m_fck",
2171 .ops
= &clkops_omap2_dflt
,
2172 .parent
= &dpll5_m2_ck
,
2173 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD
, CM_FCLKEN
),
2174 .enable_bit
= OMAP3430ES2_EN_USBHOST2_SHIFT
,
2175 .clkdm_name
= "usbhost_clkdm",
2176 .recalc
= &followparent_recalc
,
2179 static struct clk usbhost_48m_fck
= {
2180 .name
= "usbhost_48m_fck",
2181 .ops
= &clkops_omap3430es2_dss_usbhost_wait
,
2182 .parent
= &omap_48m_fck
,
2183 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD
, CM_FCLKEN
),
2184 .enable_bit
= OMAP3430ES2_EN_USBHOST1_SHIFT
,
2185 .clkdm_name
= "usbhost_clkdm",
2186 .recalc
= &followparent_recalc
,
2189 static struct clk usbhost_ick
= {
2190 /* Handles both L3 and L4 clocks */
2191 .name
= "usbhost_ick",
2192 .ops
= &clkops_omap3430es2_dss_usbhost_wait
,
2194 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD
, CM_ICLKEN
),
2195 .enable_bit
= OMAP3430ES2_EN_USBHOST_SHIFT
,
2196 .clkdm_name
= "usbhost_clkdm",
2197 .recalc
= &followparent_recalc
,
2202 static const struct clksel_rate usim_96m_rates
[] = {
2203 { .div
= 2, .val
= 3, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
2204 { .div
= 4, .val
= 4, .flags
= RATE_IN_343X
},
2205 { .div
= 8, .val
= 5, .flags
= RATE_IN_343X
},
2206 { .div
= 10, .val
= 6, .flags
= RATE_IN_343X
},
2210 static const struct clksel_rate usim_120m_rates
[] = {
2211 { .div
= 4, .val
= 7, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
2212 { .div
= 8, .val
= 8, .flags
= RATE_IN_343X
},
2213 { .div
= 16, .val
= 9, .flags
= RATE_IN_343X
},
2214 { .div
= 20, .val
= 10, .flags
= RATE_IN_343X
},
2218 static const struct clksel usim_clksel
[] = {
2219 { .parent
= &omap_96m_fck
, .rates
= usim_96m_rates
},
2220 { .parent
= &dpll5_m2_ck
, .rates
= usim_120m_rates
},
2221 { .parent
= &sys_ck
, .rates
= div2_rates
},
2226 static struct clk usim_fck
= {
2228 .ops
= &clkops_omap2_dflt_wait
,
2229 .init
= &omap2_init_clksel_parent
,
2230 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
2231 .enable_bit
= OMAP3430ES2_EN_USIMOCP_SHIFT
,
2232 .clksel_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_CLKSEL
),
2233 .clksel_mask
= OMAP3430ES2_CLKSEL_USIMOCP_MASK
,
2234 .clksel
= usim_clksel
,
2235 .recalc
= &omap2_clksel_recalc
,
2238 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2239 static struct clk gpt1_fck
= {
2241 .ops
= &clkops_omap2_dflt_wait
,
2242 .init
= &omap2_init_clksel_parent
,
2243 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
2244 .enable_bit
= OMAP3430_EN_GPT1_SHIFT
,
2245 .clksel_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_CLKSEL
),
2246 .clksel_mask
= OMAP3430_CLKSEL_GPT1_MASK
,
2247 .clksel
= omap343x_gpt_clksel
,
2248 .clkdm_name
= "wkup_clkdm",
2249 .recalc
= &omap2_clksel_recalc
,
2252 static struct clk wkup_32k_fck
= {
2253 .name
= "wkup_32k_fck",
2254 .ops
= &clkops_null
,
2255 .parent
= &omap_32k_fck
,
2256 .clkdm_name
= "wkup_clkdm",
2257 .recalc
= &followparent_recalc
,
2260 static struct clk gpio1_dbck
= {
2261 .name
= "gpio1_dbck",
2262 .ops
= &clkops_omap2_dflt
,
2263 .parent
= &wkup_32k_fck
,
2264 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
2265 .enable_bit
= OMAP3430_EN_GPIO1_SHIFT
,
2266 .clkdm_name
= "wkup_clkdm",
2267 .recalc
= &followparent_recalc
,
2270 static struct clk wdt2_fck
= {
2272 .ops
= &clkops_omap2_dflt_wait
,
2273 .parent
= &wkup_32k_fck
,
2274 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
2275 .enable_bit
= OMAP3430_EN_WDT2_SHIFT
,
2276 .clkdm_name
= "wkup_clkdm",
2277 .recalc
= &followparent_recalc
,
2280 static struct clk wkup_l4_ick
= {
2281 .name
= "wkup_l4_ick",
2282 .ops
= &clkops_null
,
2284 .clkdm_name
= "wkup_clkdm",
2285 .recalc
= &followparent_recalc
,
2289 /* Never specifically named in the TRM, so we have to infer a likely name */
2290 static struct clk usim_ick
= {
2292 .ops
= &clkops_omap2_dflt_wait
,
2293 .parent
= &wkup_l4_ick
,
2294 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2295 .enable_bit
= OMAP3430ES2_EN_USIMOCP_SHIFT
,
2296 .clkdm_name
= "wkup_clkdm",
2297 .recalc
= &followparent_recalc
,
2300 static struct clk wdt2_ick
= {
2302 .ops
= &clkops_omap2_dflt_wait
,
2303 .parent
= &wkup_l4_ick
,
2304 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2305 .enable_bit
= OMAP3430_EN_WDT2_SHIFT
,
2306 .clkdm_name
= "wkup_clkdm",
2307 .recalc
= &followparent_recalc
,
2310 static struct clk wdt1_ick
= {
2312 .ops
= &clkops_omap2_dflt_wait
,
2313 .parent
= &wkup_l4_ick
,
2314 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2315 .enable_bit
= OMAP3430_EN_WDT1_SHIFT
,
2316 .clkdm_name
= "wkup_clkdm",
2317 .recalc
= &followparent_recalc
,
2320 static struct clk gpio1_ick
= {
2321 .name
= "gpio1_ick",
2322 .ops
= &clkops_omap2_dflt_wait
,
2323 .parent
= &wkup_l4_ick
,
2324 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2325 .enable_bit
= OMAP3430_EN_GPIO1_SHIFT
,
2326 .clkdm_name
= "wkup_clkdm",
2327 .recalc
= &followparent_recalc
,
2330 static struct clk omap_32ksync_ick
= {
2331 .name
= "omap_32ksync_ick",
2332 .ops
= &clkops_omap2_dflt_wait
,
2333 .parent
= &wkup_l4_ick
,
2334 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2335 .enable_bit
= OMAP3430_EN_32KSYNC_SHIFT
,
2336 .clkdm_name
= "wkup_clkdm",
2337 .recalc
= &followparent_recalc
,
2340 /* XXX This clock no longer exists in 3430 TRM rev F */
2341 static struct clk gpt12_ick
= {
2342 .name
= "gpt12_ick",
2343 .ops
= &clkops_omap2_dflt_wait
,
2344 .parent
= &wkup_l4_ick
,
2345 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2346 .enable_bit
= OMAP3430_EN_GPT12_SHIFT
,
2347 .clkdm_name
= "wkup_clkdm",
2348 .recalc
= &followparent_recalc
,
2351 static struct clk gpt1_ick
= {
2353 .ops
= &clkops_omap2_dflt_wait
,
2354 .parent
= &wkup_l4_ick
,
2355 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2356 .enable_bit
= OMAP3430_EN_GPT1_SHIFT
,
2357 .clkdm_name
= "wkup_clkdm",
2358 .recalc
= &followparent_recalc
,
2363 /* PER clock domain */
2365 static struct clk per_96m_fck
= {
2366 .name
= "per_96m_fck",
2367 .ops
= &clkops_null
,
2368 .parent
= &omap_96m_alwon_fck
,
2369 .clkdm_name
= "per_clkdm",
2370 .recalc
= &followparent_recalc
,
2373 static struct clk per_48m_fck
= {
2374 .name
= "per_48m_fck",
2375 .ops
= &clkops_null
,
2376 .parent
= &omap_48m_fck
,
2377 .clkdm_name
= "per_clkdm",
2378 .recalc
= &followparent_recalc
,
2381 static struct clk uart3_fck
= {
2382 .name
= "uart3_fck",
2383 .ops
= &clkops_omap2_dflt_wait
,
2384 .parent
= &per_48m_fck
,
2385 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2386 .enable_bit
= OMAP3430_EN_UART3_SHIFT
,
2387 .clkdm_name
= "per_clkdm",
2388 .recalc
= &followparent_recalc
,
2391 static struct clk gpt2_fck
= {
2393 .ops
= &clkops_omap2_dflt_wait
,
2394 .init
= &omap2_init_clksel_parent
,
2395 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2396 .enable_bit
= OMAP3430_EN_GPT2_SHIFT
,
2397 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2398 .clksel_mask
= OMAP3430_CLKSEL_GPT2_MASK
,
2399 .clksel
= omap343x_gpt_clksel
,
2400 .clkdm_name
= "per_clkdm",
2401 .recalc
= &omap2_clksel_recalc
,
2404 static struct clk gpt3_fck
= {
2406 .ops
= &clkops_omap2_dflt_wait
,
2407 .init
= &omap2_init_clksel_parent
,
2408 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2409 .enable_bit
= OMAP3430_EN_GPT3_SHIFT
,
2410 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2411 .clksel_mask
= OMAP3430_CLKSEL_GPT3_MASK
,
2412 .clksel
= omap343x_gpt_clksel
,
2413 .clkdm_name
= "per_clkdm",
2414 .recalc
= &omap2_clksel_recalc
,
2417 static struct clk gpt4_fck
= {
2419 .ops
= &clkops_omap2_dflt_wait
,
2420 .init
= &omap2_init_clksel_parent
,
2421 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2422 .enable_bit
= OMAP3430_EN_GPT4_SHIFT
,
2423 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2424 .clksel_mask
= OMAP3430_CLKSEL_GPT4_MASK
,
2425 .clksel
= omap343x_gpt_clksel
,
2426 .clkdm_name
= "per_clkdm",
2427 .recalc
= &omap2_clksel_recalc
,
2430 static struct clk gpt5_fck
= {
2432 .ops
= &clkops_omap2_dflt_wait
,
2433 .init
= &omap2_init_clksel_parent
,
2434 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2435 .enable_bit
= OMAP3430_EN_GPT5_SHIFT
,
2436 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2437 .clksel_mask
= OMAP3430_CLKSEL_GPT5_MASK
,
2438 .clksel
= omap343x_gpt_clksel
,
2439 .clkdm_name
= "per_clkdm",
2440 .recalc
= &omap2_clksel_recalc
,
2443 static struct clk gpt6_fck
= {
2445 .ops
= &clkops_omap2_dflt_wait
,
2446 .init
= &omap2_init_clksel_parent
,
2447 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2448 .enable_bit
= OMAP3430_EN_GPT6_SHIFT
,
2449 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2450 .clksel_mask
= OMAP3430_CLKSEL_GPT6_MASK
,
2451 .clksel
= omap343x_gpt_clksel
,
2452 .clkdm_name
= "per_clkdm",
2453 .recalc
= &omap2_clksel_recalc
,
2456 static struct clk gpt7_fck
= {
2458 .ops
= &clkops_omap2_dflt_wait
,
2459 .init
= &omap2_init_clksel_parent
,
2460 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2461 .enable_bit
= OMAP3430_EN_GPT7_SHIFT
,
2462 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2463 .clksel_mask
= OMAP3430_CLKSEL_GPT7_MASK
,
2464 .clksel
= omap343x_gpt_clksel
,
2465 .clkdm_name
= "per_clkdm",
2466 .recalc
= &omap2_clksel_recalc
,
2469 static struct clk gpt8_fck
= {
2471 .ops
= &clkops_omap2_dflt_wait
,
2472 .init
= &omap2_init_clksel_parent
,
2473 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2474 .enable_bit
= OMAP3430_EN_GPT8_SHIFT
,
2475 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2476 .clksel_mask
= OMAP3430_CLKSEL_GPT8_MASK
,
2477 .clksel
= omap343x_gpt_clksel
,
2478 .clkdm_name
= "per_clkdm",
2479 .recalc
= &omap2_clksel_recalc
,
2482 static struct clk gpt9_fck
= {
2484 .ops
= &clkops_omap2_dflt_wait
,
2485 .init
= &omap2_init_clksel_parent
,
2486 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2487 .enable_bit
= OMAP3430_EN_GPT9_SHIFT
,
2488 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2489 .clksel_mask
= OMAP3430_CLKSEL_GPT9_MASK
,
2490 .clksel
= omap343x_gpt_clksel
,
2491 .clkdm_name
= "per_clkdm",
2492 .recalc
= &omap2_clksel_recalc
,
2495 static struct clk per_32k_alwon_fck
= {
2496 .name
= "per_32k_alwon_fck",
2497 .ops
= &clkops_null
,
2498 .parent
= &omap_32k_fck
,
2499 .clkdm_name
= "per_clkdm",
2500 .recalc
= &followparent_recalc
,
2503 static struct clk gpio6_dbck
= {
2504 .name
= "gpio6_dbck",
2505 .ops
= &clkops_omap2_dflt
,
2506 .parent
= &per_32k_alwon_fck
,
2507 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2508 .enable_bit
= OMAP3430_EN_GPIO6_SHIFT
,
2509 .clkdm_name
= "per_clkdm",
2510 .recalc
= &followparent_recalc
,
2513 static struct clk gpio5_dbck
= {
2514 .name
= "gpio5_dbck",
2515 .ops
= &clkops_omap2_dflt
,
2516 .parent
= &per_32k_alwon_fck
,
2517 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2518 .enable_bit
= OMAP3430_EN_GPIO5_SHIFT
,
2519 .clkdm_name
= "per_clkdm",
2520 .recalc
= &followparent_recalc
,
2523 static struct clk gpio4_dbck
= {
2524 .name
= "gpio4_dbck",
2525 .ops
= &clkops_omap2_dflt
,
2526 .parent
= &per_32k_alwon_fck
,
2527 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2528 .enable_bit
= OMAP3430_EN_GPIO4_SHIFT
,
2529 .clkdm_name
= "per_clkdm",
2530 .recalc
= &followparent_recalc
,
2533 static struct clk gpio3_dbck
= {
2534 .name
= "gpio3_dbck",
2535 .ops
= &clkops_omap2_dflt
,
2536 .parent
= &per_32k_alwon_fck
,
2537 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2538 .enable_bit
= OMAP3430_EN_GPIO3_SHIFT
,
2539 .clkdm_name
= "per_clkdm",
2540 .recalc
= &followparent_recalc
,
2543 static struct clk gpio2_dbck
= {
2544 .name
= "gpio2_dbck",
2545 .ops
= &clkops_omap2_dflt
,
2546 .parent
= &per_32k_alwon_fck
,
2547 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2548 .enable_bit
= OMAP3430_EN_GPIO2_SHIFT
,
2549 .clkdm_name
= "per_clkdm",
2550 .recalc
= &followparent_recalc
,
2553 static struct clk wdt3_fck
= {
2555 .ops
= &clkops_omap2_dflt_wait
,
2556 .parent
= &per_32k_alwon_fck
,
2557 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2558 .enable_bit
= OMAP3430_EN_WDT3_SHIFT
,
2559 .clkdm_name
= "per_clkdm",
2560 .recalc
= &followparent_recalc
,
2563 static struct clk per_l4_ick
= {
2564 .name
= "per_l4_ick",
2565 .ops
= &clkops_null
,
2567 .clkdm_name
= "per_clkdm",
2568 .recalc
= &followparent_recalc
,
2571 static struct clk gpio6_ick
= {
2572 .name
= "gpio6_ick",
2573 .ops
= &clkops_omap2_dflt_wait
,
2574 .parent
= &per_l4_ick
,
2575 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2576 .enable_bit
= OMAP3430_EN_GPIO6_SHIFT
,
2577 .clkdm_name
= "per_clkdm",
2578 .recalc
= &followparent_recalc
,
2581 static struct clk gpio5_ick
= {
2582 .name
= "gpio5_ick",
2583 .ops
= &clkops_omap2_dflt_wait
,
2584 .parent
= &per_l4_ick
,
2585 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2586 .enable_bit
= OMAP3430_EN_GPIO5_SHIFT
,
2587 .clkdm_name
= "per_clkdm",
2588 .recalc
= &followparent_recalc
,
2591 static struct clk gpio4_ick
= {
2592 .name
= "gpio4_ick",
2593 .ops
= &clkops_omap2_dflt_wait
,
2594 .parent
= &per_l4_ick
,
2595 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2596 .enable_bit
= OMAP3430_EN_GPIO4_SHIFT
,
2597 .clkdm_name
= "per_clkdm",
2598 .recalc
= &followparent_recalc
,
2601 static struct clk gpio3_ick
= {
2602 .name
= "gpio3_ick",
2603 .ops
= &clkops_omap2_dflt_wait
,
2604 .parent
= &per_l4_ick
,
2605 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2606 .enable_bit
= OMAP3430_EN_GPIO3_SHIFT
,
2607 .clkdm_name
= "per_clkdm",
2608 .recalc
= &followparent_recalc
,
2611 static struct clk gpio2_ick
= {
2612 .name
= "gpio2_ick",
2613 .ops
= &clkops_omap2_dflt_wait
,
2614 .parent
= &per_l4_ick
,
2615 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2616 .enable_bit
= OMAP3430_EN_GPIO2_SHIFT
,
2617 .clkdm_name
= "per_clkdm",
2618 .recalc
= &followparent_recalc
,
2621 static struct clk wdt3_ick
= {
2623 .ops
= &clkops_omap2_dflt_wait
,
2624 .parent
= &per_l4_ick
,
2625 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2626 .enable_bit
= OMAP3430_EN_WDT3_SHIFT
,
2627 .clkdm_name
= "per_clkdm",
2628 .recalc
= &followparent_recalc
,
2631 static struct clk uart3_ick
= {
2632 .name
= "uart3_ick",
2633 .ops
= &clkops_omap2_dflt_wait
,
2634 .parent
= &per_l4_ick
,
2635 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2636 .enable_bit
= OMAP3430_EN_UART3_SHIFT
,
2637 .clkdm_name
= "per_clkdm",
2638 .recalc
= &followparent_recalc
,
2641 static struct clk gpt9_ick
= {
2643 .ops
= &clkops_omap2_dflt_wait
,
2644 .parent
= &per_l4_ick
,
2645 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2646 .enable_bit
= OMAP3430_EN_GPT9_SHIFT
,
2647 .clkdm_name
= "per_clkdm",
2648 .recalc
= &followparent_recalc
,
2651 static struct clk gpt8_ick
= {
2653 .ops
= &clkops_omap2_dflt_wait
,
2654 .parent
= &per_l4_ick
,
2655 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2656 .enable_bit
= OMAP3430_EN_GPT8_SHIFT
,
2657 .clkdm_name
= "per_clkdm",
2658 .recalc
= &followparent_recalc
,
2661 static struct clk gpt7_ick
= {
2663 .ops
= &clkops_omap2_dflt_wait
,
2664 .parent
= &per_l4_ick
,
2665 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2666 .enable_bit
= OMAP3430_EN_GPT7_SHIFT
,
2667 .clkdm_name
= "per_clkdm",
2668 .recalc
= &followparent_recalc
,
2671 static struct clk gpt6_ick
= {
2673 .ops
= &clkops_omap2_dflt_wait
,
2674 .parent
= &per_l4_ick
,
2675 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2676 .enable_bit
= OMAP3430_EN_GPT6_SHIFT
,
2677 .clkdm_name
= "per_clkdm",
2678 .recalc
= &followparent_recalc
,
2681 static struct clk gpt5_ick
= {
2683 .ops
= &clkops_omap2_dflt_wait
,
2684 .parent
= &per_l4_ick
,
2685 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2686 .enable_bit
= OMAP3430_EN_GPT5_SHIFT
,
2687 .clkdm_name
= "per_clkdm",
2688 .recalc
= &followparent_recalc
,
2691 static struct clk gpt4_ick
= {
2693 .ops
= &clkops_omap2_dflt_wait
,
2694 .parent
= &per_l4_ick
,
2695 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2696 .enable_bit
= OMAP3430_EN_GPT4_SHIFT
,
2697 .clkdm_name
= "per_clkdm",
2698 .recalc
= &followparent_recalc
,
2701 static struct clk gpt3_ick
= {
2703 .ops
= &clkops_omap2_dflt_wait
,
2704 .parent
= &per_l4_ick
,
2705 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2706 .enable_bit
= OMAP3430_EN_GPT3_SHIFT
,
2707 .clkdm_name
= "per_clkdm",
2708 .recalc
= &followparent_recalc
,
2711 static struct clk gpt2_ick
= {
2713 .ops
= &clkops_omap2_dflt_wait
,
2714 .parent
= &per_l4_ick
,
2715 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2716 .enable_bit
= OMAP3430_EN_GPT2_SHIFT
,
2717 .clkdm_name
= "per_clkdm",
2718 .recalc
= &followparent_recalc
,
2721 static struct clk mcbsp2_ick
= {
2722 .name
= "mcbsp_ick",
2723 .ops
= &clkops_omap2_dflt_wait
,
2725 .parent
= &per_l4_ick
,
2726 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2727 .enable_bit
= OMAP3430_EN_MCBSP2_SHIFT
,
2728 .clkdm_name
= "per_clkdm",
2729 .recalc
= &followparent_recalc
,
2732 static struct clk mcbsp3_ick
= {
2733 .name
= "mcbsp_ick",
2734 .ops
= &clkops_omap2_dflt_wait
,
2736 .parent
= &per_l4_ick
,
2737 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2738 .enable_bit
= OMAP3430_EN_MCBSP3_SHIFT
,
2739 .clkdm_name
= "per_clkdm",
2740 .recalc
= &followparent_recalc
,
2743 static struct clk mcbsp4_ick
= {
2744 .name
= "mcbsp_ick",
2745 .ops
= &clkops_omap2_dflt_wait
,
2747 .parent
= &per_l4_ick
,
2748 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2749 .enable_bit
= OMAP3430_EN_MCBSP4_SHIFT
,
2750 .clkdm_name
= "per_clkdm",
2751 .recalc
= &followparent_recalc
,
2754 static const struct clksel mcbsp_234_clksel
[] = {
2755 { .parent
= &core_96m_fck
, .rates
= common_mcbsp_96m_rates
},
2756 { .parent
= &mcbsp_clks
, .rates
= common_mcbsp_mcbsp_rates
},
2760 static struct clk mcbsp2_fck
= {
2761 .name
= "mcbsp_fck",
2762 .ops
= &clkops_omap2_dflt_wait
,
2764 .init
= &omap2_init_clksel_parent
,
2765 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2766 .enable_bit
= OMAP3430_EN_MCBSP2_SHIFT
,
2767 .clksel_reg
= OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0
),
2768 .clksel_mask
= OMAP2_MCBSP2_CLKS_MASK
,
2769 .clksel
= mcbsp_234_clksel
,
2770 .clkdm_name
= "per_clkdm",
2771 .recalc
= &omap2_clksel_recalc
,
2774 static struct clk mcbsp3_fck
= {
2775 .name
= "mcbsp_fck",
2776 .ops
= &clkops_omap2_dflt_wait
,
2778 .init
= &omap2_init_clksel_parent
,
2779 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2780 .enable_bit
= OMAP3430_EN_MCBSP3_SHIFT
,
2781 .clksel_reg
= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1
),
2782 .clksel_mask
= OMAP2_MCBSP3_CLKS_MASK
,
2783 .clksel
= mcbsp_234_clksel
,
2784 .clkdm_name
= "per_clkdm",
2785 .recalc
= &omap2_clksel_recalc
,
2788 static struct clk mcbsp4_fck
= {
2789 .name
= "mcbsp_fck",
2790 .ops
= &clkops_omap2_dflt_wait
,
2792 .init
= &omap2_init_clksel_parent
,
2793 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2794 .enable_bit
= OMAP3430_EN_MCBSP4_SHIFT
,
2795 .clksel_reg
= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1
),
2796 .clksel_mask
= OMAP2_MCBSP4_CLKS_MASK
,
2797 .clksel
= mcbsp_234_clksel
,
2798 .clkdm_name
= "per_clkdm",
2799 .recalc
= &omap2_clksel_recalc
,
2804 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2806 static const struct clksel_rate emu_src_sys_rates
[] = {
2807 { .div
= 1, .val
= 0, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
2811 static const struct clksel_rate emu_src_core_rates
[] = {
2812 { .div
= 1, .val
= 1, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
2816 static const struct clksel_rate emu_src_per_rates
[] = {
2817 { .div
= 1, .val
= 2, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
2821 static const struct clksel_rate emu_src_mpu_rates
[] = {
2822 { .div
= 1, .val
= 3, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
2826 static const struct clksel emu_src_clksel
[] = {
2827 { .parent
= &sys_ck
, .rates
= emu_src_sys_rates
},
2828 { .parent
= &emu_core_alwon_ck
, .rates
= emu_src_core_rates
},
2829 { .parent
= &emu_per_alwon_ck
, .rates
= emu_src_per_rates
},
2830 { .parent
= &emu_mpu_alwon_ck
, .rates
= emu_src_mpu_rates
},
2835 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2836 * to switch the source of some of the EMU clocks.
2837 * XXX Are there CLKEN bits for these EMU clks?
2839 static struct clk emu_src_ck
= {
2840 .name
= "emu_src_ck",
2841 .ops
= &clkops_null
,
2842 .init
= &omap2_init_clksel_parent
,
2843 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2844 .clksel_mask
= OMAP3430_MUX_CTRL_MASK
,
2845 .clksel
= emu_src_clksel
,
2846 .clkdm_name
= "emu_clkdm",
2847 .recalc
= &omap2_clksel_recalc
,
2850 static const struct clksel_rate pclk_emu_rates
[] = {
2851 { .div
= 2, .val
= 2, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
2852 { .div
= 3, .val
= 3, .flags
= RATE_IN_343X
},
2853 { .div
= 4, .val
= 4, .flags
= RATE_IN_343X
},
2854 { .div
= 6, .val
= 6, .flags
= RATE_IN_343X
},
2858 static const struct clksel pclk_emu_clksel
[] = {
2859 { .parent
= &emu_src_ck
, .rates
= pclk_emu_rates
},
2863 static struct clk pclk_fck
= {
2865 .ops
= &clkops_null
,
2866 .init
= &omap2_init_clksel_parent
,
2867 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2868 .clksel_mask
= OMAP3430_CLKSEL_PCLK_MASK
,
2869 .clksel
= pclk_emu_clksel
,
2870 .clkdm_name
= "emu_clkdm",
2871 .recalc
= &omap2_clksel_recalc
,
2874 static const struct clksel_rate pclkx2_emu_rates
[] = {
2875 { .div
= 1, .val
= 1, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
2876 { .div
= 2, .val
= 2, .flags
= RATE_IN_343X
},
2877 { .div
= 3, .val
= 3, .flags
= RATE_IN_343X
},
2881 static const struct clksel pclkx2_emu_clksel
[] = {
2882 { .parent
= &emu_src_ck
, .rates
= pclkx2_emu_rates
},
2886 static struct clk pclkx2_fck
= {
2887 .name
= "pclkx2_fck",
2888 .ops
= &clkops_null
,
2889 .init
= &omap2_init_clksel_parent
,
2890 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2891 .clksel_mask
= OMAP3430_CLKSEL_PCLKX2_MASK
,
2892 .clksel
= pclkx2_emu_clksel
,
2893 .clkdm_name
= "emu_clkdm",
2894 .recalc
= &omap2_clksel_recalc
,
2897 static const struct clksel atclk_emu_clksel
[] = {
2898 { .parent
= &emu_src_ck
, .rates
= div2_rates
},
2902 static struct clk atclk_fck
= {
2903 .name
= "atclk_fck",
2904 .ops
= &clkops_null
,
2905 .init
= &omap2_init_clksel_parent
,
2906 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2907 .clksel_mask
= OMAP3430_CLKSEL_ATCLK_MASK
,
2908 .clksel
= atclk_emu_clksel
,
2909 .clkdm_name
= "emu_clkdm",
2910 .recalc
= &omap2_clksel_recalc
,
2913 static struct clk traceclk_src_fck
= {
2914 .name
= "traceclk_src_fck",
2915 .ops
= &clkops_null
,
2916 .init
= &omap2_init_clksel_parent
,
2917 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2918 .clksel_mask
= OMAP3430_TRACE_MUX_CTRL_MASK
,
2919 .clksel
= emu_src_clksel
,
2920 .clkdm_name
= "emu_clkdm",
2921 .recalc
= &omap2_clksel_recalc
,
2924 static const struct clksel_rate traceclk_rates
[] = {
2925 { .div
= 1, .val
= 1, .flags
= RATE_IN_343X
| DEFAULT_RATE
},
2926 { .div
= 2, .val
= 2, .flags
= RATE_IN_343X
},
2927 { .div
= 4, .val
= 4, .flags
= RATE_IN_343X
},
2931 static const struct clksel traceclk_clksel
[] = {
2932 { .parent
= &traceclk_src_fck
, .rates
= traceclk_rates
},
2936 static struct clk traceclk_fck
= {
2937 .name
= "traceclk_fck",
2938 .ops
= &clkops_null
,
2939 .init
= &omap2_init_clksel_parent
,
2940 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2941 .clksel_mask
= OMAP3430_CLKSEL_TRACECLK_MASK
,
2942 .clksel
= traceclk_clksel
,
2943 .clkdm_name
= "emu_clkdm",
2944 .recalc
= &omap2_clksel_recalc
,
2949 /* SmartReflex fclk (VDD1) */
2950 static struct clk sr1_fck
= {
2952 .ops
= &clkops_omap2_dflt_wait
,
2954 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
2955 .enable_bit
= OMAP3430_EN_SR1_SHIFT
,
2956 .recalc
= &followparent_recalc
,
2959 /* SmartReflex fclk (VDD2) */
2960 static struct clk sr2_fck
= {
2962 .ops
= &clkops_omap2_dflt_wait
,
2964 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
2965 .enable_bit
= OMAP3430_EN_SR2_SHIFT
,
2966 .recalc
= &followparent_recalc
,
2969 static struct clk sr_l4_ick
= {
2970 .name
= "sr_l4_ick",
2971 .ops
= &clkops_null
, /* RMK: missing? */
2973 .clkdm_name
= "core_l4_clkdm",
2974 .recalc
= &followparent_recalc
,
2977 /* SECURE_32K_FCK clocks */
2979 static struct clk gpt12_fck
= {
2980 .name
= "gpt12_fck",
2981 .ops
= &clkops_null
,
2982 .parent
= &secure_32k_fck
,
2983 .recalc
= &followparent_recalc
,
2986 static struct clk wdt1_fck
= {
2988 .ops
= &clkops_null
,
2989 .parent
= &secure_32k_fck
,
2990 .recalc
= &followparent_recalc
,