arch/arm/mach-mxs/mach-mxs.c

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2012 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/clocksource.h>
  16 #include <linux/can/platform/flexcan.h>
  17 #include <linux/delay.h>
  18 #include <linux/err.h>
  19 #include <linux/gpio.h>
  20 #include <linux/init.h>
  21 #include <linux/irqchip.h>
  22 #include <linux/irqchip/mxs.h>
  23 #include <linux/micrel_phy.h>
  24 #include <linux/mxsfb.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/phy.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <asm/mach/arch.h>
  29 #include <asm/mach/time.h>
  30 #include <mach/common.h>
  31 #include <mach/digctl.h>
  32 #include <mach/mxs.h>
  33
  34 static struct fb_videomode mx23evk_video_modes[] = {
  35         {
  36                 .name           = "Samsung-LMS430HF02",
  37                 .refresh        = 60,
  38                 .xres           = 480,
  39                 .yres           = 272,
  40                 .pixclock       = 108096, /* picosecond (9.2 MHz) */
  41                 .left_margin    = 15,
  42                 .right_margin   = 8,
  43                 .upper_margin   = 12,
  44                 .lower_margin   = 4,
  45                 .hsync_len      = 1,
  46                 .vsync_len      = 1,
  47         },
  48 };
  49
  50 static struct fb_videomode mx28evk_video_modes[] = {
  51         {
  52                 .name           = "Seiko-43WVF1G",
  53                 .refresh        = 60,
  54                 .xres           = 800,
  55                 .yres           = 480,
  56                 .pixclock       = 29851, /* picosecond (33.5 MHz) */
  57                 .left_margin    = 89,
  58                 .right_margin   = 164,
  59                 .upper_margin   = 23,
  60                 .lower_margin   = 10,
  61                 .hsync_len      = 10,
  62                 .vsync_len      = 10,
  63         },
  64 };
  65
  66 static struct fb_videomode m28evk_video_modes[] = {
  67         {
  68                 .name           = "Ampire AM-800480R2TMQW-T01H",
  69                 .refresh        = 60,
  70                 .xres           = 800,
  71                 .yres           = 480,
  72                 .pixclock       = 30066, /* picosecond (33.26 MHz) */
  73                 .left_margin    = 0,
  74                 .right_margin   = 256,
  75                 .upper_margin   = 0,
  76                 .lower_margin   = 45,
  77                 .hsync_len      = 1,
  78                 .vsync_len      = 1,
  79         },
  80 };
  81
  82 static struct fb_videomode apx4devkit_video_modes[] = {
  83         {
  84                 .name           = "HannStar PJ70112A",
  85                 .refresh        = 60,
  86                 .xres           = 800,
  87                 .yres           = 480,
  88                 .pixclock       = 33333, /* picosecond (30.00 MHz) */
  89                 .left_margin    = 88,
  90                 .right_margin   = 40,
  91                 .upper_margin   = 32,
  92                 .lower_margin   = 13,
  93                 .hsync_len      = 48,
  94                 .vsync_len      = 3,
  95                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  96         },
  97 };
  98
  99 static struct fb_videomode apf28dev_video_modes[] = {
 100         {
 101                 .name = "LW700",
 102                 .refresh = 60,
 103                 .xres = 800,
 104                 .yres = 480,
 105                 .pixclock = 30303, /* picosecond */
 106                 .left_margin = 96,
 107                 .right_margin = 96, /* at least 3 & 1 */
 108                 .upper_margin = 0x14,
 109                 .lower_margin = 0x15,
 110                 .hsync_len = 64,
 111                 .vsync_len = 4,
 112                 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 113         },
 114 };
 115
 116 static struct fb_videomode cfa10049_video_modes[] = {
 117         {
 118                 .name           = "Himax HX8357-B",
 119                 .refresh        = 60,
 120                 .xres           = 320,
 121                 .yres           = 480,
 122                 .pixclock       = 108506, /* picosecond (9.216 MHz) */
 123                 .left_margin    = 2,
 124                 .right_margin   = 2,
 125                 .upper_margin   = 2,
 126                 .lower_margin   = 2,
 127                 .hsync_len      = 15,
 128                 .vsync_len      = 15,
 129         },
 130 };
 131
 132 static struct mxsfb_platform_data mxsfb_pdata __initdata;
 133
 134 /*
 135  * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers
 136  */
 137 #define MX28EVK_FLEXCAN_SWITCH  MXS_GPIO_NR(2, 13)
 138
 139 static int flexcan0_en, flexcan1_en;
 140
 141 static void mx28evk_flexcan_switch(void)
 142 {
 143         if (flexcan0_en || flexcan1_en)
 144                 gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
 145         else
 146                 gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
 147 }
 148
 149 static void mx28evk_flexcan0_switch(int enable)
 150 {
 151         flexcan0_en = enable;
 152         mx28evk_flexcan_switch();
 153 }
 154
 155 static void mx28evk_flexcan1_switch(int enable)
 156 {
 157         flexcan1_en = enable;
 158         mx28evk_flexcan_switch();
 159 }
 160
 161 static struct flexcan_platform_data flexcan_pdata[2];
 162
 163 static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = {
 164         OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata),
 165         OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata),
 166         OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80032000, NULL, &flexcan_pdata[0]),
 167         OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80034000, NULL, &flexcan_pdata[1]),
 168         { /* sentinel */ }
 169 };
 170
 171 static void __init imx23_timer_init(void)
 172 {
 173         mx23_clocks_init();
 174         clocksource_of_init();
 175 }
 176
 177 static void __init imx28_timer_init(void)
 178 {
 179         mx28_clocks_init();
 180         clocksource_of_init();
 181 }
 182
 183 enum mac_oui {
 184         OUI_FSL,
 185         OUI_DENX,
 186         OUI_CRYSTALFONTZ,
 187 };
 188
 189 static void __init update_fec_mac_prop(enum mac_oui oui)
 190 {
 191         struct device_node *np, *from = NULL;
 192         struct property *newmac;
 193         const u32 *ocotp = mxs_get_ocotp();
 194         u8 *macaddr;
 195         u32 val;
 196         int i;
 197
 198         for (i = 0; i < 2; i++) {
 199                 np = of_find_compatible_node(from, NULL, "fsl,imx28-fec");
 200                 if (!np)
 201                         return;
 202
 203                 from = np;
 204
 205                 if (of_get_property(np, "local-mac-address", NULL))
 206                         continue;
 207
 208                 newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
 209                 if (!newmac)
 210                         return;
 211                 newmac->value = newmac + 1;
 212                 newmac->length = 6;
 213
 214                 newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
 215                 if (!newmac->name) {
 216                         kfree(newmac);
 217                         return;
 218                 }
 219
 220                 /*
 221                  * OCOTP only stores the last 4 octets for each mac address,
 222                  * so hard-code OUI here.
 223                  */
 224                 macaddr = newmac->value;
 225                 switch (oui) {
 226                 case OUI_FSL:
 227                         macaddr[0] = 0x00;
 228                         macaddr[1] = 0x04;
 229                         macaddr[2] = 0x9f;
 230                         break;
 231                 case OUI_DENX:
 232                         macaddr[0] = 0xc0;
 233                         macaddr[1] = 0xe5;
 234                         macaddr[2] = 0x4e;
 235                         break;
 236                 case OUI_CRYSTALFONTZ:
 237                         macaddr[0] = 0x58;
 238                         macaddr[1] = 0xb9;
 239                         macaddr[2] = 0xe1;
 240                         break;
 241                 }
 242                 val = ocotp[i];
 243                 macaddr[3] = (val >> 16) & 0xff;
 244                 macaddr[4] = (val >> 8) & 0xff;
 245                 macaddr[5] = (val >> 0) & 0xff;
 246
 247                 of_update_property(np, newmac);
 248         }
 249 }
 250
 251 static void __init imx23_evk_init(void)
 252 {
 253         mxsfb_pdata.mode_list = mx23evk_video_modes;
 254         mxsfb_pdata.mode_count = ARRAY_SIZE(mx23evk_video_modes);
 255         mxsfb_pdata.default_bpp = 32;
 256         mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
 257         mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
 258                                 MXSFB_SYNC_DOTCLK_FAILING_ACT;
 259 }
 260
 261 static inline void enable_clk_enet_out(void)
 262 {
 263         struct clk *clk = clk_get_sys("enet_out", NULL);
 264
 265         if (!IS_ERR(clk))
 266                 clk_prepare_enable(clk);
 267 }
 268
 269 static void __init imx28_evk_init(void)
 270 {
 271         enable_clk_enet_out();
 272         update_fec_mac_prop(OUI_FSL);
 273
 274         mxsfb_pdata.mode_list = mx28evk_video_modes;
 275         mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes);
 276         mxsfb_pdata.default_bpp = 32;
 277         mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
 278         mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
 279                                 MXSFB_SYNC_DOTCLK_FAILING_ACT;
 280
 281         mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
 282 }
 283
 284 static void __init imx28_evk_post_init(void)
 285 {
 286         if (!gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT,
 287                               "flexcan-switch")) {
 288                 flexcan_pdata[0].transceiver_switch = mx28evk_flexcan0_switch;
 289                 flexcan_pdata[1].transceiver_switch = mx28evk_flexcan1_switch;
 290         }
 291 }
 292
 293 static void __init m28evk_init(void)
 294 {
 295         mxsfb_pdata.mode_list = m28evk_video_modes;
 296         mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes);
 297         mxsfb_pdata.default_bpp = 16;
 298         mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
 299         mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
 300 }
 301
 302 static void __init sc_sps1_init(void)
 303 {
 304         enable_clk_enet_out();
 305 }
 306
 307 static int apx4devkit_phy_fixup(struct phy_device *phy)
 308 {
 309         phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
 310         return 0;
 311 }
 312
 313 static void __init apx4devkit_init(void)
 314 {
 315         enable_clk_enet_out();
 316
 317         if (IS_BUILTIN(CONFIG_PHYLIB))
 318                 phy_register_fixup_for_uid(PHY_ID_KSZ8051, MICREL_PHY_ID_MASK,
 319                                            apx4devkit_phy_fixup);
 320
 321         mxsfb_pdata.mode_list = apx4devkit_video_modes;
 322         mxsfb_pdata.mode_count = ARRAY_SIZE(apx4devkit_video_modes);
 323         mxsfb_pdata.default_bpp = 32;
 324         mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
 325         mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
 326                                 MXSFB_SYNC_DOTCLK_FAILING_ACT;
 327 }
 328
 329 #define ENET0_MDC__GPIO_4_0     MXS_GPIO_NR(4, 0)
 330 #define ENET0_MDIO__GPIO_4_1    MXS_GPIO_NR(4, 1)
 331 #define ENET0_RX_EN__GPIO_4_2   MXS_GPIO_NR(4, 2)
 332 #define ENET0_RXD0__GPIO_4_3    MXS_GPIO_NR(4, 3)
 333 #define ENET0_RXD1__GPIO_4_4    MXS_GPIO_NR(4, 4)
 334 #define ENET0_TX_EN__GPIO_4_6   MXS_GPIO_NR(4, 6)
 335 #define ENET0_TXD0__GPIO_4_7    MXS_GPIO_NR(4, 7)
 336 #define ENET0_TXD1__GPIO_4_8    MXS_GPIO_NR(4, 8)
 337 #define ENET_CLK__GPIO_4_16     MXS_GPIO_NR(4, 16)
 338
 339 #define TX28_FEC_PHY_POWER      MXS_GPIO_NR(3, 29)
 340 #define TX28_FEC_PHY_RESET      MXS_GPIO_NR(4, 13)
 341 #define TX28_FEC_nINT           MXS_GPIO_NR(4, 5)
 342
 343 static const struct gpio tx28_gpios[] __initconst = {
 344         { ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" },
 345         { ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" },
 346         { ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" },
 347         { ENET0_RXD0__GPIO_4_3, GPIOF_OUT_INIT_LOW, "GPIO_4_3" },
 348         { ENET0_RXD1__GPIO_4_4, GPIOF_OUT_INIT_LOW, "GPIO_4_4" },
 349         { ENET0_TX_EN__GPIO_4_6, GPIOF_OUT_INIT_LOW, "GPIO_4_6" },
 350         { ENET0_TXD0__GPIO_4_7, GPIOF_OUT_INIT_LOW, "GPIO_4_7" },
 351         { ENET0_TXD1__GPIO_4_8, GPIOF_OUT_INIT_LOW, "GPIO_4_8" },
 352         { ENET_CLK__GPIO_4_16, GPIOF_OUT_INIT_LOW, "GPIO_4_16" },
 353         { TX28_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" },
 354         { TX28_FEC_PHY_RESET, GPIOF_OUT_INIT_LOW, "fec-phy-reset" },
 355         { TX28_FEC_nINT, GPIOF_DIR_IN, "fec-int" },
 356 };
 357
 358 static void __init tx28_post_init(void)
 359 {
 360         struct device_node *np;
 361         struct platform_device *pdev;
 362         struct pinctrl *pctl;
 363         int ret;
 364
 365         enable_clk_enet_out();
 366
 367         np = of_find_compatible_node(NULL, NULL, "fsl,imx28-fec");
 368         pdev = of_find_device_by_node(np);
 369         if (!pdev) {
 370                 pr_err("%s: failed to find fec device\n", __func__);
 371                 return;
 372         }
 373
 374         pctl = pinctrl_get_select(&pdev->dev, "gpio_mode");
 375         if (IS_ERR(pctl)) {
 376                 pr_err("%s: failed to get pinctrl state\n", __func__);
 377                 return;
 378         }
 379
 380         ret = gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
 381         if (ret) {
 382                 pr_err("%s: failed to request gpios: %d\n", __func__, ret);
 383                 return;
 384         }
 385
 386         /* Power up fec phy */
 387         gpio_set_value(TX28_FEC_PHY_POWER, 1);
 388         msleep(26); /* 25ms according to data sheet */
 389
 390         /* Mode strap pins */
 391         gpio_set_value(ENET0_RX_EN__GPIO_4_2, 1);
 392         gpio_set_value(ENET0_RXD0__GPIO_4_3, 1);
 393         gpio_set_value(ENET0_RXD1__GPIO_4_4, 1);
 394
 395         udelay(100); /* minimum assertion time for nRST */
 396
 397         /* Deasserting FEC PHY RESET */
 398         gpio_set_value(TX28_FEC_PHY_RESET, 1);
 399
 400         pinctrl_put(pctl);
 401 }
 402
 403 static void __init cfa10049_init(void)
 404 {
 405         enable_clk_enet_out();
 406         update_fec_mac_prop(OUI_CRYSTALFONTZ);
 407
 408         mxsfb_pdata.mode_list = cfa10049_video_modes;
 409         mxsfb_pdata.mode_count = ARRAY_SIZE(cfa10049_video_modes);
 410         mxsfb_pdata.default_bpp = 32;
 411         mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
 412         mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
 413 }
 414
 415 static void __init cfa10037_init(void)
 416 {
 417         enable_clk_enet_out();
 418         update_fec_mac_prop(OUI_CRYSTALFONTZ);
 419 }
 420
 421 static void __init apf28_init(void)
 422 {
 423         enable_clk_enet_out();
 424
 425         mxsfb_pdata.mode_list = apf28dev_video_modes;
 426         mxsfb_pdata.mode_count = ARRAY_SIZE(apf28dev_video_modes);
 427         mxsfb_pdata.default_bpp = 16;
 428         mxsfb_pdata.ld_intf_width = STMLCDIF_16BIT;
 429         mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
 430                                 MXSFB_SYNC_DOTCLK_FAILING_ACT;
 431 }
 432
 433 static void __init mxs_machine_init(void)
 434 {
 435         if (of_machine_is_compatible("fsl,imx28-evk"))
 436                 imx28_evk_init();
 437         else if (of_machine_is_compatible("fsl,imx23-evk"))
 438                 imx23_evk_init();
 439         else if (of_machine_is_compatible("denx,m28evk"))
 440                 m28evk_init();
 441         else if (of_machine_is_compatible("bluegiga,apx4devkit"))
 442                 apx4devkit_init();
 443         else if (of_machine_is_compatible("crystalfontz,cfa10037"))
 444                 cfa10037_init();
 445         else if (of_machine_is_compatible("crystalfontz,cfa10049"))
 446                 cfa10049_init();
 447         else if (of_machine_is_compatible("armadeus,imx28-apf28"))
 448                 apf28_init();
 449         else if (of_machine_is_compatible("schulercontrol,imx28-sps1"))
 450                 sc_sps1_init();
 451
 452         of_platform_populate(NULL, of_default_bus_match_table,
 453                              mxs_auxdata_lookup, NULL);
 454
 455         if (of_machine_is_compatible("karo,tx28"))
 456                 tx28_post_init();
 457
 458         if (of_machine_is_compatible("fsl,imx28-evk"))
 459                 imx28_evk_post_init();
 460 }
 461
 462 static const char *imx23_dt_compat[] __initdata = {
 463         "fsl,imx23",
 464         NULL,
 465 };
 466
 467 static const char *imx28_dt_compat[] __initdata = {
 468         "fsl,imx28",
 469         NULL,
 470 };
 471
 472 DT_MACHINE_START(IMX23, "Freescale i.MX23 (Device Tree)")
 473         .map_io         = mx23_map_io,
 474         .init_irq       = irqchip_init,
 475         .handle_irq     = icoll_handle_irq,
 476         .init_time      = imx23_timer_init,
 477         .init_machine   = mxs_machine_init,
 478         .dt_compat      = imx23_dt_compat,
 479         .restart        = mxs_restart,
 480 MACHINE_END
 481
 482 DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
 483         .map_io         = mx28_map_io,
 484         .init_irq       = irqchip_init,
 485         .handle_irq     = icoll_handle_irq,
 486         .init_time      = imx28_timer_init,
 487         .init_machine   = mxs_machine_init,
 488         .dt_compat      = imx28_dt_compat,
 489         .restart        = mxs_restart,
 490 MACHINE_END