2 * arch/arm/mach-kirkwood/pcie.c
4 * PCIe functions for Marvell Kirkwood SoCs
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/mbus.h>
15 #include <asm/mach/pci.h>
16 #include <plat/pcie.h>
17 #include <mach/bridge-regs.h>
21 #define PCIE_BASE ((void __iomem *)PCIE_VIRT_BASE)
23 void __init
kirkwood_pcie_id(u32
*dev
, u32
*rev
)
25 *dev
= orion_pcie_dev_id(PCIE_BASE
);
26 *rev
= orion_pcie_rev(PCIE_BASE
);
29 static int pcie_valid_config(int bus
, int dev
)
32 * Don't go out when trying to access --
33 * 1. nonexisting device on local bus
34 * 2. where there's no device connected (no link)
36 if (bus
== 0 && dev
== 0)
39 if (!orion_pcie_link_up(PCIE_BASE
))
42 if (bus
== 0 && dev
!= 1)
50 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
51 * and then reading the PCIE_CONF_DATA register. Need to make sure these
52 * transactions are atomic.
54 static DEFINE_SPINLOCK(kirkwood_pcie_lock
);
56 static int pcie_rd_conf(struct pci_bus
*bus
, u32 devfn
, int where
,
62 if (pcie_valid_config(bus
->number
, PCI_SLOT(devfn
)) == 0) {
64 return PCIBIOS_DEVICE_NOT_FOUND
;
67 spin_lock_irqsave(&kirkwood_pcie_lock
, flags
);
68 ret
= orion_pcie_rd_conf(PCIE_BASE
, bus
, devfn
, where
, size
, val
);
69 spin_unlock_irqrestore(&kirkwood_pcie_lock
, flags
);
74 static int pcie_wr_conf(struct pci_bus
*bus
, u32 devfn
,
75 int where
, int size
, u32 val
)
80 if (pcie_valid_config(bus
->number
, PCI_SLOT(devfn
)) == 0)
81 return PCIBIOS_DEVICE_NOT_FOUND
;
83 spin_lock_irqsave(&kirkwood_pcie_lock
, flags
);
84 ret
= orion_pcie_wr_conf(PCIE_BASE
, bus
, devfn
, where
, size
, val
);
85 spin_unlock_irqrestore(&kirkwood_pcie_lock
, flags
);
90 static struct pci_ops pcie_ops
= {
92 .write
= pcie_wr_conf
,
96 static int __init
kirkwood_pcie_setup(int nr
, struct pci_sys_data
*sys
)
99 extern unsigned int kirkwood_clk_ctrl
;
102 * Generic PCIe unit setup.
104 orion_pcie_setup(PCIE_BASE
, &kirkwood_mbus_dram_info
);
109 res
= kzalloc(sizeof(struct resource
) * 2, GFP_KERNEL
);
111 panic("pcie_setup unable to alloc resources");
116 res
[0].name
= "PCIe I/O Space";
117 res
[0].flags
= IORESOURCE_IO
;
118 res
[0].start
= KIRKWOOD_PCIE_IO_PHYS_BASE
;
119 res
[0].end
= res
[0].start
+ KIRKWOOD_PCIE_IO_SIZE
- 1;
120 if (request_resource(&ioport_resource
, &res
[0]))
121 panic("Request PCIe IO resource failed\n");
122 sys
->resource
[0] = &res
[0];
127 res
[1].name
= "PCIe Memory Space";
128 res
[1].flags
= IORESOURCE_MEM
;
129 res
[1].start
= KIRKWOOD_PCIE_MEM_PHYS_BASE
;
130 res
[1].end
= res
[1].start
+ KIRKWOOD_PCIE_MEM_SIZE
- 1;
131 if (request_resource(&iomem_resource
, &res
[1]))
132 panic("Request PCIe Memory resource failed\n");
133 sys
->resource
[1] = &res
[1];
135 sys
->resource
[2] = NULL
;
138 kirkwood_clk_ctrl
|= CGC_PEX0
;
143 static void __devinit
rc_pci_fixup(struct pci_dev
*dev
)
146 * Prevent enumeration of root complex.
148 if (dev
->bus
->parent
== NULL
&& dev
->devfn
== 0) {
151 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
152 dev
->resource
[i
].start
= 0;
153 dev
->resource
[i
].end
= 0;
154 dev
->resource
[i
].flags
= 0;
158 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL
, PCI_ANY_ID
, rc_pci_fixup
);
160 static struct pci_bus __init
*
161 kirkwood_pcie_scan_bus(int nr
, struct pci_sys_data
*sys
)
166 bus
= pci_scan_bus(sys
->busnr
, &pcie_ops
, sys
);
175 static int __init
kirkwood_pcie_map_irq(struct pci_dev
*dev
, u8 slot
, u8 pin
)
177 return IRQ_KIRKWOOD_PCIE
;
180 static struct hw_pci kirkwood_pci __initdata
= {
182 .swizzle
= pci_std_swizzle
,
183 .setup
= kirkwood_pcie_setup
,
184 .scan
= kirkwood_pcie_scan_bus
,
185 .map_irq
= kirkwood_pcie_map_irq
,
188 void __init
kirkwood_pcie_init(void)
190 pci_common_init(&kirkwood_pci
);