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Merge branch 'parisc-for-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/delle...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-kirkwood / common.c
1 /*
2 * arch/arm/mach-kirkwood/common.c
3 *
4 * Core functions for Marvell Kirkwood SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/serial_8250.h>
15 #include <linux/ata_platform.h>
16 #include <linux/mtd/nand.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/clk-provider.h>
19 #include <linux/spinlock.h>
20 #include <linux/mv643xx_i2c.h>
21 #include <linux/timex.h>
22 #include <linux/kexec.h>
23 #include <net/dsa.h>
24 #include <asm/page.h>
25 #include <asm/mach/map.h>
26 #include <asm/mach/time.h>
27 #include <mach/kirkwood.h>
28 #include <mach/bridge-regs.h>
29 #include <linux/platform_data/asoc-kirkwood.h>
30 #include <plat/cache-feroceon-l2.h>
31 #include <linux/platform_data/mmc-mvsdio.h>
32 #include <linux/platform_data/mtd-orion_nand.h>
33 #include <linux/platform_data/usb-ehci-orion.h>
34 #include <plat/common.h>
35 #include <plat/time.h>
36 #include <linux/platform_data/dma-mv_xor.h>
37 #include "common.h"
38
39 /*****************************************************************************
40 * I/O Address Mapping
41 ****************************************************************************/
42 static struct map_desc kirkwood_io_desc[] __initdata = {
43 {
44 .virtual = (unsigned long) KIRKWOOD_REGS_VIRT_BASE,
45 .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
46 .length = KIRKWOOD_REGS_SIZE,
47 .type = MT_DEVICE,
48 },
49 };
50
51 void __init kirkwood_map_io(void)
52 {
53 iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
54 }
55
56 /*****************************************************************************
57 * CLK tree
58 ****************************************************************************/
59
60 static void enable_sata0(void)
61 {
62 /* Enable PLL and IVREF */
63 writel(readl(SATA0_PHY_MODE_2) | 0xf, SATA0_PHY_MODE_2);
64 /* Enable PHY */
65 writel(readl(SATA0_IF_CTRL) & ~0x200, SATA0_IF_CTRL);
66 }
67
68 static void disable_sata0(void)
69 {
70 /* Disable PLL and IVREF */
71 writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
72 /* Disable PHY */
73 writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
74 }
75
76 static void enable_sata1(void)
77 {
78 /* Enable PLL and IVREF */
79 writel(readl(SATA1_PHY_MODE_2) | 0xf, SATA1_PHY_MODE_2);
80 /* Enable PHY */
81 writel(readl(SATA1_IF_CTRL) & ~0x200, SATA1_IF_CTRL);
82 }
83
84 static void disable_sata1(void)
85 {
86 /* Disable PLL and IVREF */
87 writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
88 /* Disable PHY */
89 writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
90 }
91
92 static void disable_pcie0(void)
93 {
94 writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
95 while (1)
96 if (readl(PCIE_STATUS) & 0x1)
97 break;
98 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
99 }
100
101 static void disable_pcie1(void)
102 {
103 u32 dev, rev;
104
105 kirkwood_pcie_id(&dev, &rev);
106
107 if (dev == MV88F6282_DEV_ID) {
108 writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
109 while (1)
110 if (readl(PCIE1_STATUS) & 0x1)
111 break;
112 writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
113 }
114 }
115
116 /* An extended version of the gated clk. This calls fn_en()/fn_dis
117 * before enabling/disabling the clock. We use this to turn on/off
118 * PHYs etc. */
119 struct clk_gate_fn {
120 struct clk_gate gate;
121 void (*fn_en)(void);
122 void (*fn_dis)(void);
123 };
124
125 #define to_clk_gate_fn(_gate) container_of(_gate, struct clk_gate_fn, gate)
126 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
127
128 static int clk_gate_fn_enable(struct clk_hw *hw)
129 {
130 struct clk_gate *gate = to_clk_gate(hw);
131 struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate);
132 int ret;
133
134 ret = clk_gate_ops.enable(hw);
135 if (!ret && gate_fn->fn_en)
136 gate_fn->fn_en();
137
138 return ret;
139 }
140
141 static void clk_gate_fn_disable(struct clk_hw *hw)
142 {
143 struct clk_gate *gate = to_clk_gate(hw);
144 struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate);
145
146 if (gate_fn->fn_dis)
147 gate_fn->fn_dis();
148
149 clk_gate_ops.disable(hw);
150 }
151
152 static struct clk_ops clk_gate_fn_ops;
153
154 static struct clk __init *clk_register_gate_fn(struct device *dev,
155 const char *name,
156 const char *parent_name, unsigned long flags,
157 void __iomem *reg, u8 bit_idx,
158 u8 clk_gate_flags, spinlock_t *lock,
159 void (*fn_en)(void), void (*fn_dis)(void))
160 {
161 struct clk_gate_fn *gate_fn;
162 struct clk *clk;
163 struct clk_init_data init;
164
165 gate_fn = kzalloc(sizeof(struct clk_gate_fn), GFP_KERNEL);
166 if (!gate_fn) {
167 pr_err("%s: could not allocate gated clk\n", __func__);
168 return ERR_PTR(-ENOMEM);
169 }
170
171 init.name = name;
172 init.ops = &clk_gate_fn_ops;
173 init.flags = flags;
174 init.parent_names = (parent_name ? &parent_name : NULL);
175 init.num_parents = (parent_name ? 1 : 0);
176
177 /* struct clk_gate assignments */
178 gate_fn->gate.reg = reg;
179 gate_fn->gate.bit_idx = bit_idx;
180 gate_fn->gate.flags = clk_gate_flags;
181 gate_fn->gate.lock = lock;
182 gate_fn->gate.hw.init = &init;
183 gate_fn->fn_en = fn_en;
184 gate_fn->fn_dis = fn_dis;
185
186 /* ops is the gate ops, but with our enable/disable functions */
187 if (clk_gate_fn_ops.enable != clk_gate_fn_enable ||
188 clk_gate_fn_ops.disable != clk_gate_fn_disable) {
189 clk_gate_fn_ops = clk_gate_ops;
190 clk_gate_fn_ops.enable = clk_gate_fn_enable;
191 clk_gate_fn_ops.disable = clk_gate_fn_disable;
192 }
193
194 clk = clk_register(dev, &gate_fn->gate.hw);
195
196 if (IS_ERR(clk))
197 kfree(gate_fn);
198
199 return clk;
200 }
201
202 static DEFINE_SPINLOCK(gating_lock);
203 static struct clk *tclk;
204
205 static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
206 {
207 return clk_register_gate(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
208 bit_idx, 0, &gating_lock);
209 }
210
211 static struct clk __init *kirkwood_register_gate_fn(const char *name,
212 u8 bit_idx,
213 void (*fn_en)(void),
214 void (*fn_dis)(void))
215 {
216 return clk_register_gate_fn(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
217 bit_idx, 0, &gating_lock, fn_en, fn_dis);
218 }
219
220 static struct clk *ge0, *ge1;
221
222 void __init kirkwood_clk_init(void)
223 {
224 struct clk *runit, *sata0, *sata1, *usb0, *sdio;
225 struct clk *crypto, *xor0, *xor1, *pex0, *pex1, *audio;
226
227 tclk = clk_register_fixed_rate(NULL, "tclk", NULL,
228 CLK_IS_ROOT, kirkwood_tclk);
229
230 runit = kirkwood_register_gate("runit", CGC_BIT_RUNIT);
231 ge0 = kirkwood_register_gate("ge0", CGC_BIT_GE0);
232 ge1 = kirkwood_register_gate("ge1", CGC_BIT_GE1);
233 sata0 = kirkwood_register_gate_fn("sata0", CGC_BIT_SATA0,
234 enable_sata0, disable_sata0);
235 sata1 = kirkwood_register_gate_fn("sata1", CGC_BIT_SATA1,
236 enable_sata1, disable_sata1);
237 usb0 = kirkwood_register_gate("usb0", CGC_BIT_USB0);
238 sdio = kirkwood_register_gate("sdio", CGC_BIT_SDIO);
239 crypto = kirkwood_register_gate("crypto", CGC_BIT_CRYPTO);
240 xor0 = kirkwood_register_gate("xor0", CGC_BIT_XOR0);
241 xor1 = kirkwood_register_gate("xor1", CGC_BIT_XOR1);
242 pex0 = kirkwood_register_gate_fn("pex0", CGC_BIT_PEX0,
243 NULL, disable_pcie0);
244 pex1 = kirkwood_register_gate_fn("pex1", CGC_BIT_PEX1,
245 NULL, disable_pcie1);
246 audio = kirkwood_register_gate("audio", CGC_BIT_AUDIO);
247 kirkwood_register_gate("tdm", CGC_BIT_TDM);
248 kirkwood_register_gate("tsu", CGC_BIT_TSU);
249
250 /* clkdev entries, mapping clks to devices */
251 orion_clkdev_add(NULL, "orion_spi.0", runit);
252 orion_clkdev_add(NULL, "orion_spi.1", runit);
253 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", ge0);
254 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", ge1);
255 orion_clkdev_add(NULL, "orion_wdt", tclk);
256 orion_clkdev_add("0", "sata_mv.0", sata0);
257 orion_clkdev_add("1", "sata_mv.0", sata1);
258 orion_clkdev_add(NULL, "orion-ehci.0", usb0);
259 orion_clkdev_add(NULL, "orion_nand", runit);
260 orion_clkdev_add(NULL, "mvsdio", sdio);
261 orion_clkdev_add(NULL, "mv_crypto", crypto);
262 orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
263 orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
264 orion_clkdev_add("0", "pcie", pex0);
265 orion_clkdev_add("1", "pcie", pex1);
266 orion_clkdev_add(NULL, "kirkwood-i2s", audio);
267 orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", runit);
268 orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".1", runit);
269
270 /* Marvell says runit is used by SPI, UART, NAND, TWSI, ...,
271 * so should never be gated.
272 */
273 clk_prepare_enable(runit);
274 }
275
276 /*****************************************************************************
277 * EHCI0
278 ****************************************************************************/
279 void __init kirkwood_ehci_init(void)
280 {
281 orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
282 }
283
284
285 /*****************************************************************************
286 * GE00
287 ****************************************************************************/
288 void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
289 {
290 orion_ge00_init(eth_data,
291 GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
292 IRQ_KIRKWOOD_GE00_ERR, 1600);
293 /* The interface forgets the MAC address assigned by u-boot if
294 the clock is turned off, so claim the clk now. */
295 clk_prepare_enable(ge0);
296 }
297
298
299 /*****************************************************************************
300 * GE01
301 ****************************************************************************/
302 void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
303 {
304 orion_ge01_init(eth_data,
305 GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
306 IRQ_KIRKWOOD_GE01_ERR, 1600);
307 clk_prepare_enable(ge1);
308 }
309
310
311 /*****************************************************************************
312 * Ethernet switch
313 ****************************************************************************/
314 void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
315 {
316 orion_ge00_switch_init(d, irq);
317 }
318
319
320 /*****************************************************************************
321 * NAND flash
322 ****************************************************************************/
323 static struct resource kirkwood_nand_resource = {
324 .flags = IORESOURCE_MEM,
325 .start = KIRKWOOD_NAND_MEM_PHYS_BASE,
326 .end = KIRKWOOD_NAND_MEM_PHYS_BASE +
327 KIRKWOOD_NAND_MEM_SIZE - 1,
328 };
329
330 static struct orion_nand_data kirkwood_nand_data = {
331 .cle = 0,
332 .ale = 1,
333 .width = 8,
334 };
335
336 static struct platform_device kirkwood_nand_flash = {
337 .name = "orion_nand",
338 .id = -1,
339 .dev = {
340 .platform_data = &kirkwood_nand_data,
341 },
342 .resource = &kirkwood_nand_resource,
343 .num_resources = 1,
344 };
345
346 void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
347 int chip_delay)
348 {
349 kirkwood_nand_data.parts = parts;
350 kirkwood_nand_data.nr_parts = nr_parts;
351 kirkwood_nand_data.chip_delay = chip_delay;
352 platform_device_register(&kirkwood_nand_flash);
353 }
354
355 void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
356 int (*dev_ready)(struct mtd_info *))
357 {
358 kirkwood_nand_data.parts = parts;
359 kirkwood_nand_data.nr_parts = nr_parts;
360 kirkwood_nand_data.dev_ready = dev_ready;
361 platform_device_register(&kirkwood_nand_flash);
362 }
363
364 /*****************************************************************************
365 * SoC RTC
366 ****************************************************************************/
367 static void __init kirkwood_rtc_init(void)
368 {
369 orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
370 }
371
372
373 /*****************************************************************************
374 * SATA
375 ****************************************************************************/
376 void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
377 {
378 orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
379 }
380
381
382 /*****************************************************************************
383 * SD/SDIO/MMC
384 ****************************************************************************/
385 static struct resource mvsdio_resources[] = {
386 [0] = {
387 .start = SDIO_PHYS_BASE,
388 .end = SDIO_PHYS_BASE + SZ_1K - 1,
389 .flags = IORESOURCE_MEM,
390 },
391 [1] = {
392 .start = IRQ_KIRKWOOD_SDIO,
393 .end = IRQ_KIRKWOOD_SDIO,
394 .flags = IORESOURCE_IRQ,
395 },
396 };
397
398 static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
399
400 static struct platform_device kirkwood_sdio = {
401 .name = "mvsdio",
402 .id = -1,
403 .dev = {
404 .dma_mask = &mvsdio_dmamask,
405 .coherent_dma_mask = DMA_BIT_MASK(32),
406 },
407 .num_resources = ARRAY_SIZE(mvsdio_resources),
408 .resource = mvsdio_resources,
409 };
410
411 void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
412 {
413 u32 dev, rev;
414
415 kirkwood_pcie_id(&dev, &rev);
416 if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
417 mvsdio_data->clock = 100000000;
418 else
419 mvsdio_data->clock = 200000000;
420 kirkwood_sdio.dev.platform_data = mvsdio_data;
421 platform_device_register(&kirkwood_sdio);
422 }
423
424
425 /*****************************************************************************
426 * SPI
427 ****************************************************************************/
428 void __init kirkwood_spi_init(void)
429 {
430 orion_spi_init(SPI_PHYS_BASE);
431 }
432
433
434 /*****************************************************************************
435 * I2C
436 ****************************************************************************/
437 void __init kirkwood_i2c_init(void)
438 {
439 orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
440 }
441
442
443 /*****************************************************************************
444 * UART0
445 ****************************************************************************/
446
447 void __init kirkwood_uart0_init(void)
448 {
449 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
450 IRQ_KIRKWOOD_UART_0, tclk);
451 }
452
453
454 /*****************************************************************************
455 * UART1
456 ****************************************************************************/
457 void __init kirkwood_uart1_init(void)
458 {
459 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
460 IRQ_KIRKWOOD_UART_1, tclk);
461 }
462
463 /*****************************************************************************
464 * Cryptographic Engines and Security Accelerator (CESA)
465 ****************************************************************************/
466 void __init kirkwood_crypto_init(void)
467 {
468 orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
469 KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
470 }
471
472
473 /*****************************************************************************
474 * XOR0
475 ****************************************************************************/
476 void __init kirkwood_xor0_init(void)
477 {
478 orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
479 IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
480 }
481
482
483 /*****************************************************************************
484 * XOR1
485 ****************************************************************************/
486 void __init kirkwood_xor1_init(void)
487 {
488 orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
489 IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
490 }
491
492
493 /*****************************************************************************
494 * Watchdog
495 ****************************************************************************/
496 void __init kirkwood_wdt_init(void)
497 {
498 orion_wdt_init();
499 }
500
501 /*****************************************************************************
502 * CPU idle
503 ****************************************************************************/
504 static struct resource kirkwood_cpuidle_resource[] = {
505 {
506 .flags = IORESOURCE_MEM,
507 .start = DDR_OPERATION_BASE,
508 .end = DDR_OPERATION_BASE + 3,
509 },
510 };
511
512 static struct platform_device kirkwood_cpuidle = {
513 .name = "kirkwood_cpuidle",
514 .id = -1,
515 .resource = kirkwood_cpuidle_resource,
516 .num_resources = 1,
517 };
518
519 void __init kirkwood_cpuidle_init(void)
520 {
521 platform_device_register(&kirkwood_cpuidle);
522 }
523
524 /*****************************************************************************
525 * Time handling
526 ****************************************************************************/
527 void __init kirkwood_init_early(void)
528 {
529 orion_time_set_base(TIMER_VIRT_BASE);
530
531 /*
532 * Some Kirkwood devices allocate their coherent buffers from atomic
533 * context. Increase size of atomic coherent pool to make sure such
534 * the allocations won't fail.
535 */
536 init_dma_coherent_pool_size(SZ_1M);
537 mvebu_mbus_init("marvell,kirkwood-mbus",
538 BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
539 DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ);
540 }
541
542 int kirkwood_tclk;
543
544 static int __init kirkwood_find_tclk(void)
545 {
546 u32 dev, rev;
547
548 kirkwood_pcie_id(&dev, &rev);
549
550 if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
551 if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
552 return 200000000;
553
554 return 166666667;
555 }
556
557 void __init kirkwood_timer_init(void)
558 {
559 kirkwood_tclk = kirkwood_find_tclk();
560
561 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
562 IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
563 }
564
565 /*****************************************************************************
566 * Audio
567 ****************************************************************************/
568 static struct resource kirkwood_i2s_resources[] = {
569 [0] = {
570 .start = AUDIO_PHYS_BASE,
571 .end = AUDIO_PHYS_BASE + SZ_16K - 1,
572 .flags = IORESOURCE_MEM,
573 },
574 [1] = {
575 .start = IRQ_KIRKWOOD_I2S,
576 .end = IRQ_KIRKWOOD_I2S,
577 .flags = IORESOURCE_IRQ,
578 },
579 };
580
581 static struct kirkwood_asoc_platform_data kirkwood_i2s_data = {
582 .burst = 128,
583 };
584
585 static struct platform_device kirkwood_i2s_device = {
586 .name = "kirkwood-i2s",
587 .id = -1,
588 .num_resources = ARRAY_SIZE(kirkwood_i2s_resources),
589 .resource = kirkwood_i2s_resources,
590 .dev = {
591 .platform_data = &kirkwood_i2s_data,
592 },
593 };
594
595 static struct platform_device kirkwood_pcm_device = {
596 .name = "kirkwood-pcm-audio",
597 .id = -1,
598 };
599
600 void __init kirkwood_audio_init(void)
601 {
602 platform_device_register(&kirkwood_i2s_device);
603 platform_device_register(&kirkwood_pcm_device);
604 }
605
606 /*****************************************************************************
607 * General
608 ****************************************************************************/
609 /*
610 * Identify device ID and revision.
611 */
612 char * __init kirkwood_id(void)
613 {
614 u32 dev, rev;
615
616 kirkwood_pcie_id(&dev, &rev);
617
618 if (dev == MV88F6281_DEV_ID) {
619 if (rev == MV88F6281_REV_Z0)
620 return "MV88F6281-Z0";
621 else if (rev == MV88F6281_REV_A0)
622 return "MV88F6281-A0";
623 else if (rev == MV88F6281_REV_A1)
624 return "MV88F6281-A1";
625 else
626 return "MV88F6281-Rev-Unsupported";
627 } else if (dev == MV88F6192_DEV_ID) {
628 if (rev == MV88F6192_REV_Z0)
629 return "MV88F6192-Z0";
630 else if (rev == MV88F6192_REV_A0)
631 return "MV88F6192-A0";
632 else if (rev == MV88F6192_REV_A1)
633 return "MV88F6192-A1";
634 else
635 return "MV88F6192-Rev-Unsupported";
636 } else if (dev == MV88F6180_DEV_ID) {
637 if (rev == MV88F6180_REV_A0)
638 return "MV88F6180-Rev-A0";
639 else if (rev == MV88F6180_REV_A1)
640 return "MV88F6180-Rev-A1";
641 else
642 return "MV88F6180-Rev-Unsupported";
643 } else if (dev == MV88F6282_DEV_ID) {
644 if (rev == MV88F6282_REV_A0)
645 return "MV88F6282-Rev-A0";
646 else if (rev == MV88F6282_REV_A1)
647 return "MV88F6282-Rev-A1";
648 else
649 return "MV88F6282-Rev-Unsupported";
650 } else {
651 return "Device-Unknown";
652 }
653 }
654
655 void __init kirkwood_setup_wins(void)
656 {
657 /*
658 * The PCIe windows will no longer be statically allocated
659 * here once Kirkwood is migrated to the pci-mvebu driver.
660 */
661 mvebu_mbus_add_window_remap_flags("pcie0.0",
662 KIRKWOOD_PCIE_IO_PHYS_BASE,
663 KIRKWOOD_PCIE_IO_SIZE,
664 KIRKWOOD_PCIE_IO_BUS_BASE,
665 MVEBU_MBUS_PCI_IO);
666 mvebu_mbus_add_window_remap_flags("pcie0.0",
667 KIRKWOOD_PCIE_MEM_PHYS_BASE,
668 KIRKWOOD_PCIE_MEM_SIZE,
669 MVEBU_MBUS_NO_REMAP,
670 MVEBU_MBUS_PCI_MEM);
671 mvebu_mbus_add_window_remap_flags("pcie1.0",
672 KIRKWOOD_PCIE1_IO_PHYS_BASE,
673 KIRKWOOD_PCIE1_IO_SIZE,
674 KIRKWOOD_PCIE1_IO_BUS_BASE,
675 MVEBU_MBUS_PCI_IO);
676 mvebu_mbus_add_window_remap_flags("pcie1.0",
677 KIRKWOOD_PCIE1_MEM_PHYS_BASE,
678 KIRKWOOD_PCIE1_MEM_SIZE,
679 MVEBU_MBUS_NO_REMAP,
680 MVEBU_MBUS_PCI_MEM);
681 mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE,
682 KIRKWOOD_NAND_MEM_SIZE);
683 mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE,
684 KIRKWOOD_SRAM_SIZE);
685 }
686
687 void __init kirkwood_l2_init(void)
688 {
689 #ifdef CONFIG_CACHE_FEROCEON_L2
690 #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
691 writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
692 feroceon_l2_init(1);
693 #else
694 writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
695 feroceon_l2_init(0);
696 #endif
697 #endif
698 }
699
700 void __init kirkwood_init(void)
701 {
702 pr_info("Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk);
703
704 /*
705 * Disable propagation of mbus errors to the CPU local bus,
706 * as this causes mbus errors (which can occur for example
707 * for PCI aborts) to throw CPU aborts, which we're not set
708 * up to deal with.
709 */
710 writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
711
712 kirkwood_setup_wins();
713
714 kirkwood_l2_init();
715
716 /* Setup root of clk tree */
717 kirkwood_clk_init();
718
719 /* internal devices that every board has */
720 kirkwood_rtc_init();
721 kirkwood_wdt_init();
722 kirkwood_xor0_init();
723 kirkwood_xor1_init();
724 kirkwood_crypto_init();
725
726 kirkwood_cpuidle_init();
727 #ifdef CONFIG_KEXEC
728 kexec_reinit = kirkwood_enable_pcie;
729 #endif
730 }
731
732 void kirkwood_restart(char mode, const char *cmd)
733 {
734 /*
735 * Enable soft reset to assert RSTOUTn.
736 */
737 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
738
739 /*
740 * Assert soft reset.
741 */
742 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
743
744 while (1)
745 ;
746 }
kernel source for telekom puls (alcatel/mediatek)