arch/arm/mach-ixp4xx/common.c

   1 /*
   2  * arch/arm/mach-ixp4xx/common.c
   3  *
   4  * Generic code shared across all IXP4XX platforms
   5  *
   6  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright 2002 (c) Intel Corporation
   9  * Copyright 2003-2004 (c) MontaVista, Software, Inc.
  10  *
  11  * This file is licensed under  the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/mm.h>
  18 #include <linux/init.h>
  19 #include <linux/serial.h>
  20 #include <linux/tty.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/bitops.h>
  25 #include <linux/time.h>
  26 #include <linux/timex.h>
  27 #include <linux/clocksource.h>
  28 #include <linux/clockchips.h>
  29 #include <linux/io.h>
  30 #include <linux/export.h>
  31 #include <linux/gpio.h>
  32
  33 #include <mach/udc.h>
  34 #include <mach/hardware.h>
  35 #include <mach/io.h>
  36 #include <asm/uaccess.h>
  37 #include <asm/pgtable.h>
  38 #include <asm/page.h>
  39 #include <asm/irq.h>
  40 #include <asm/sched_clock.h>
  41 #include <asm/system_misc.h>
  42
  43 #include <asm/mach/map.h>
  44 #include <asm/mach/irq.h>
  45 #include <asm/mach/time.h>
  46
  47 static void __init ixp4xx_clocksource_init(void);
  48 static void __init ixp4xx_clockevent_init(void);
  49 static struct clock_event_device clockevent_ixp4xx;
  50
  51 /*************************************************************************
  52  * IXP4xx chipset I/O mapping
  53  *************************************************************************/
  54 static struct map_desc ixp4xx_io_desc[] __initdata = {
  55         {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
  56                 .virtual        = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
  57                 .pfn            = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
  58                 .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
  59                 .type           = MT_DEVICE
  60         }, {    /* Expansion Bus Config Registers */
  61                 .virtual        = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
  62                 .pfn            = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
  63                 .length         = IXP4XX_EXP_CFG_REGION_SIZE,
  64                 .type           = MT_DEVICE
  65         }, {    /* PCI Registers */
  66                 .virtual        = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
  67                 .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
  68                 .length         = IXP4XX_PCI_CFG_REGION_SIZE,
  69                 .type           = MT_DEVICE
  70         }, {    /* Queue Manager */
  71                 .virtual        = (unsigned long)IXP4XX_QMGR_BASE_VIRT,
  72                 .pfn            = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS),
  73                 .length         = IXP4XX_QMGR_REGION_SIZE,
  74                 .type           = MT_DEVICE
  75         },
  76 };
  77
  78 void __init ixp4xx_map_io(void)
  79 {
  80         iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
  81 }
  82
  83
  84 /*************************************************************************
  85  * IXP4xx chipset IRQ handling
  86  *
  87  * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
  88  *       (be it PCI or something else) configures that GPIO line
  89  *       as an IRQ.
  90  **************************************************************************/
  91 enum ixp4xx_irq_type {
  92         IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
  93 };
  94
  95 /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
  96 static unsigned long long ixp4xx_irq_edge = 0;
  97
  98 /*
  99  * IRQ -> GPIO mapping table
 100  */
 101 static signed char irq2gpio[32] = {
 102         -1, -1, -1, -1, -1, -1,  0,  1,
 103         -1, -1, -1, -1, -1, -1, -1, -1,
 104         -1, -1, -1,  2,  3,  4,  5,  6,
 105          7,  8,  9, 10, 11, 12, -1, -1,
 106 };
 107
 108 static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
 109 {
 110         int irq;
 111
 112         for (irq = 0; irq < 32; irq++) {
 113                 if (irq2gpio[irq] == gpio)
 114                         return irq;
 115         }
 116         return -EINVAL;
 117 }
 118
 119 int irq_to_gpio(unsigned int irq)
 120 {
 121         int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL;
 122
 123         if (gpio == -1)
 124                 return -EINVAL;
 125
 126         return gpio;
 127 }
 128 EXPORT_SYMBOL(irq_to_gpio);
 129
 130 static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
 131 {
 132         int line = irq2gpio[d->irq];
 133         u32 int_style;
 134         enum ixp4xx_irq_type irq_type;
 135         volatile u32 *int_reg;
 136
 137         /*
 138          * Only for GPIO IRQs
 139          */
 140         if (line < 0)
 141                 return -EINVAL;
 142
 143         switch (type){
 144         case IRQ_TYPE_EDGE_BOTH:
 145                 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
 146                 irq_type = IXP4XX_IRQ_EDGE;
 147                 break;
 148         case IRQ_TYPE_EDGE_RISING:
 149                 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
 150                 irq_type = IXP4XX_IRQ_EDGE;
 151                 break;
 152         case IRQ_TYPE_EDGE_FALLING:
 153                 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
 154                 irq_type = IXP4XX_IRQ_EDGE;
 155                 break;
 156         case IRQ_TYPE_LEVEL_HIGH:
 157                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
 158                 irq_type = IXP4XX_IRQ_LEVEL;
 159                 break;
 160         case IRQ_TYPE_LEVEL_LOW:
 161                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
 162                 irq_type = IXP4XX_IRQ_LEVEL;
 163                 break;
 164         default:
 165                 return -EINVAL;
 166         }
 167
 168         if (irq_type == IXP4XX_IRQ_EDGE)
 169                 ixp4xx_irq_edge |= (1 << d->irq);
 170         else
 171                 ixp4xx_irq_edge &= ~(1 << d->irq);
 172
 173         if (line >= 8) {        /* pins 8-15 */
 174                 line -= 8;
 175                 int_reg = IXP4XX_GPIO_GPIT2R;
 176         } else {                /* pins 0-7 */
 177                 int_reg = IXP4XX_GPIO_GPIT1R;
 178         }
 179
 180         /* Clear the style for the appropriate pin */
 181         *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
 182                         (line * IXP4XX_GPIO_STYLE_SIZE));
 183
 184         *IXP4XX_GPIO_GPISR = (1 << line);
 185
 186         /* Set the new style */
 187         *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
 188
 189         /* Configure the line as an input */
 190         gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN);
 191
 192         return 0;
 193 }
 194
 195 static void ixp4xx_irq_mask(struct irq_data *d)
 196 {
 197         if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
 198                 *IXP4XX_ICMR2 &= ~(1 << (d->irq - 32));
 199         else
 200                 *IXP4XX_ICMR &= ~(1 << d->irq);
 201 }
 202
 203 static void ixp4xx_irq_ack(struct irq_data *d)
 204 {
 205         int line = (d->irq < 32) ? irq2gpio[d->irq] : -1;
 206
 207         if (line >= 0)
 208                 *IXP4XX_GPIO_GPISR = (1 << line);
 209 }
 210
 211 /*
 212  * Level triggered interrupts on GPIO lines can only be cleared when the
 213  * interrupt condition disappears.
 214  */
 215 static void ixp4xx_irq_unmask(struct irq_data *d)
 216 {
 217         if (!(ixp4xx_irq_edge & (1 << d->irq)))
 218                 ixp4xx_irq_ack(d);
 219
 220         if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
 221                 *IXP4XX_ICMR2 |= (1 << (d->irq - 32));
 222         else
 223                 *IXP4XX_ICMR |= (1 << d->irq);
 224 }
 225
 226 static struct irq_chip ixp4xx_irq_chip = {
 227         .name           = "IXP4xx",
 228         .irq_ack        = ixp4xx_irq_ack,
 229         .irq_mask       = ixp4xx_irq_mask,
 230         .irq_unmask     = ixp4xx_irq_unmask,
 231         .irq_set_type   = ixp4xx_set_irq_type,
 232 };
 233
 234 void __init ixp4xx_init_irq(void)
 235 {
 236         int i = 0;
 237
 238         /*
 239          * ixp4xx does not implement the XScale PWRMODE register
 240          * so it must not call cpu_do_idle().
 241          */
 242         disable_hlt();
 243
 244         /* Route all sources to IRQ instead of FIQ */
 245         *IXP4XX_ICLR = 0x0;
 246
 247         /* Disable all interrupt */
 248         *IXP4XX_ICMR = 0x0;
 249
 250         if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
 251                 /* Route upper 32 sources to IRQ instead of FIQ */
 252                 *IXP4XX_ICLR2 = 0x00;
 253
 254                 /* Disable upper 32 interrupts */
 255                 *IXP4XX_ICMR2 = 0x00;
 256         }
 257
 258         /* Default to all level triggered */
 259         for(i = 0; i < NR_IRQS; i++) {
 260                 irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
 261                                          handle_level_irq);
 262                 set_irq_flags(i, IRQF_VALID);
 263         }
 264 }
 265
 266
 267 /*************************************************************************
 268  * IXP4xx timer tick
 269  * We use OS timer1 on the CPU for the timer tick and the timestamp
 270  * counter as a source of real clock ticks to account for missed jiffies.
 271  *************************************************************************/
 272
 273 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
 274 {
 275         struct clock_event_device *evt = dev_id;
 276
 277         /* Clear Pending Interrupt by writing '1' to it */
 278         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 279
 280         evt->event_handler(evt);
 281
 282         return IRQ_HANDLED;
 283 }
 284
 285 static struct irqaction ixp4xx_timer_irq = {
 286         .name           = "timer1",
 287         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 288         .handler        = ixp4xx_timer_interrupt,
 289         .dev_id         = &clockevent_ixp4xx,
 290 };
 291
 292 void __init ixp4xx_timer_init(void)
 293 {
 294         /* Reset/disable counter */
 295         *IXP4XX_OSRT1 = 0;
 296
 297         /* Clear Pending Interrupt by writing '1' to it */
 298         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 299
 300         /* Reset time-stamp counter */
 301         *IXP4XX_OSTS = 0;
 302
 303         /* Connect the interrupt handler and enable the interrupt */
 304         setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
 305
 306         ixp4xx_clocksource_init();
 307         ixp4xx_clockevent_init();
 308 }
 309
 310 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
 311
 312 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
 313 {
 314         memcpy(&ixp4xx_udc_info, info, sizeof *info);
 315 }
 316
 317 static struct resource ixp4xx_udc_resources[] = {
 318         [0] = {
 319                 .start  = 0xc800b000,
 320                 .end    = 0xc800bfff,
 321                 .flags  = IORESOURCE_MEM,
 322         },
 323         [1] = {
 324                 .start  = IRQ_IXP4XX_USB,
 325                 .end    = IRQ_IXP4XX_USB,
 326                 .flags  = IORESOURCE_IRQ,
 327         },
 328 };
 329
 330 /*
 331  * USB device controller. The IXP4xx uses the same controller as PXA25X,
 332  * so we just use the same device.
 333  */
 334 static struct platform_device ixp4xx_udc_device = {
 335         .name           = "pxa25x-udc",
 336         .id             = -1,
 337         .num_resources  = 2,
 338         .resource       = ixp4xx_udc_resources,
 339         .dev            = {
 340                 .platform_data = &ixp4xx_udc_info,
 341         },
 342 };
 343
 344 static struct platform_device *ixp4xx_devices[] __initdata = {
 345         &ixp4xx_udc_device,
 346 };
 347
 348 static struct resource ixp46x_i2c_resources[] = {
 349         [0] = {
 350                 .start  = 0xc8011000,
 351                 .end    = 0xc801101c,
 352                 .flags  = IORESOURCE_MEM,
 353         },
 354         [1] = {
 355                 .start  = IRQ_IXP4XX_I2C,
 356                 .end    = IRQ_IXP4XX_I2C,
 357                 .flags  = IORESOURCE_IRQ
 358         }
 359 };
 360
 361 /*
 362  * I2C controller. The IXP46x uses the same block as the IOP3xx, so
 363  * we just use the same device name.
 364  */
 365 static struct platform_device ixp46x_i2c_controller = {
 366         .name           = "IOP3xx-I2C",
 367         .id             = 0,
 368         .num_resources  = 2,
 369         .resource       = ixp46x_i2c_resources
 370 };
 371
 372 static struct platform_device *ixp46x_devices[] __initdata = {
 373         &ixp46x_i2c_controller
 374 };
 375
 376 unsigned long ixp4xx_exp_bus_size;
 377 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
 378
 379 static int ixp4xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
 380 {
 381         gpio_line_config(gpio, IXP4XX_GPIO_IN);
 382
 383         return 0;
 384 }
 385
 386 static int ixp4xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
 387                                         int level)
 388 {
 389         gpio_line_set(gpio, level);
 390         gpio_line_config(gpio, IXP4XX_GPIO_OUT);
 391
 392         return 0;
 393 }
 394
 395 static int ixp4xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
 396 {
 397         int value;
 398
 399         gpio_line_get(gpio, &value);
 400
 401         return value;
 402 }
 403
 404 static void ixp4xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
 405                                   int value)
 406 {
 407         gpio_line_set(gpio, value);
 408 }
 409
 410 static struct gpio_chip ixp4xx_gpio_chip = {
 411         .label                  = "IXP4XX_GPIO_CHIP",
 412         .direction_input        = ixp4xx_gpio_direction_input,
 413         .direction_output       = ixp4xx_gpio_direction_output,
 414         .get                    = ixp4xx_gpio_get_value,
 415         .set                    = ixp4xx_gpio_set_value,
 416         .to_irq                 = ixp4xx_gpio_to_irq,
 417         .base                   = 0,
 418         .ngpio                  = 16,
 419 };
 420
 421 void __init ixp4xx_sys_init(void)
 422 {
 423         ixp4xx_exp_bus_size = SZ_16M;
 424
 425         platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
 426
 427         gpiochip_add(&ixp4xx_gpio_chip);
 428
 429         if (cpu_is_ixp46x()) {
 430                 int region;
 431
 432                 platform_add_devices(ixp46x_devices,
 433                                 ARRAY_SIZE(ixp46x_devices));
 434
 435                 for (region = 0; region < 7; region++) {
 436                         if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
 437                                 ixp4xx_exp_bus_size = SZ_32M;
 438                                 break;
 439                         }
 440                 }
 441         }
 442
 443         printk("IXP4xx: Using %luMiB expansion bus window size\n",
 444                         ixp4xx_exp_bus_size >> 20);
 445 }
 446
 447 /*
 448  * sched_clock()
 449  */
 450 static u32 notrace ixp4xx_read_sched_clock(void)
 451 {
 452         return *IXP4XX_OSTS;
 453 }
 454
 455 /*
 456  * clocksource
 457  */
 458
 459 static cycle_t ixp4xx_clocksource_read(struct clocksource *c)
 460 {
 461         return *IXP4XX_OSTS;
 462 }
 463
 464 unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
 465 EXPORT_SYMBOL(ixp4xx_timer_freq);
 466 static void __init ixp4xx_clocksource_init(void)
 467 {
 468         setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
 469
 470         clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
 471                         ixp4xx_clocksource_read);
 472 }
 473
 474 /*
 475  * clockevents
 476  */
 477 static int ixp4xx_set_next_event(unsigned long evt,
 478                                  struct clock_event_device *unused)
 479 {
 480         unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
 481
 482         *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
 483
 484         return 0;
 485 }
 486
 487 static void ixp4xx_set_mode(enum clock_event_mode mode,
 488                             struct clock_event_device *evt)
 489 {
 490         unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
 491         unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
 492
 493         switch (mode) {
 494         case CLOCK_EVT_MODE_PERIODIC:
 495                 osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK;
 496                 opts = IXP4XX_OST_ENABLE;
 497                 break;
 498         case CLOCK_EVT_MODE_ONESHOT:
 499                 /* period set by 'set next_event' */
 500                 osrt = 0;
 501                 opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
 502                 break;
 503         case CLOCK_EVT_MODE_SHUTDOWN:
 504                 opts &= ~IXP4XX_OST_ENABLE;
 505                 break;
 506         case CLOCK_EVT_MODE_RESUME:
 507                 opts |= IXP4XX_OST_ENABLE;
 508                 break;
 509         case CLOCK_EVT_MODE_UNUSED:
 510         default:
 511                 osrt = opts = 0;
 512                 break;
 513         }
 514
 515         *IXP4XX_OSRT1 = osrt | opts;
 516 }
 517
 518 static struct clock_event_device clockevent_ixp4xx = {
 519         .name           = "ixp4xx timer1",
 520         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 521         .rating         = 200,
 522         .set_mode       = ixp4xx_set_mode,
 523         .set_next_event = ixp4xx_set_next_event,
 524 };
 525
 526 static void __init ixp4xx_clockevent_init(void)
 527 {
 528         clockevent_ixp4xx.cpumask = cpumask_of(0);
 529         clockevents_config_and_register(&clockevent_ixp4xx, IXP4XX_TIMER_FREQ,
 530                                         0xf, 0xfffffffe);
 531 }
 532
 533 void ixp4xx_restart(char mode, const char *cmd)
 534 {
 535         if ( 1 && mode == 's') {
 536                 /* Jump into ROM at address 0 */
 537                 soft_restart(0);
 538         } else {
 539                 /* Use on-chip reset capability */
 540
 541                 /* set the "key" register to enable access to
 542                  * "timer" and "enable" registers
 543                  */
 544                 *IXP4XX_OSWK = IXP4XX_WDT_KEY;
 545
 546                 /* write 0 to the timer register for an immediate reset */
 547                 *IXP4XX_OSWT = 0;
 548
 549                 *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
 550         }
 551 }
 552
 553 #ifdef CONFIG_IXP4XX_INDIRECT_PCI
 554 /*
 555  * In the case of using indirect PCI, we simply return the actual PCI
 556  * address and our read/write implementation use that to drive the
 557  * access registers. If something outside of PCI is ioremap'd, we
 558  * fallback to the default.
 559  */
 560
 561 static void __iomem *ixp4xx_ioremap_caller(unsigned long addr, size_t size,
 562                                            unsigned int mtype, void *caller)
 563 {
 564         if (!is_pci_memory(addr))
 565                 return __arm_ioremap_caller(addr, size, mtype, caller);
 566
 567         return (void __iomem *)addr;
 568 }
 569
 570 static void ixp4xx_iounmap(void __iomem *addr)
 571 {
 572         if (!is_pci_memory((__force u32)addr))
 573                 __iounmap(addr);
 574 }
 575
 576 void __init ixp4xx_init_early(void)
 577 {
 578         arch_ioremap_caller = ixp4xx_ioremap_caller;
 579         arch_iounmap = ixp4xx_iounmap;
 580 }
 581 #else
 582 void __init ixp4xx_init_early(void) {}
 583 #endif