arch/arm/mach-integrator/pci_v3.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/pci_v3.c
   3  *
   4  *  PCI functions for V3 host PCI bridge
   5  *
   6  *  Copyright (C) 1999 ARM Limited
   7  *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22  */
  23 #include <linux/config.h>
  24 #include <linux/kernel.h>
  25 #include <linux/pci.h>
  26 #include <linux/ptrace.h>
  27 #include <linux/slab.h>
  28 #include <linux/ioport.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/init.h>
  32
  33 #include <asm/hardware.h>
  34 #include <asm/io.h>
  35 #include <asm/irq.h>
  36 #include <asm/system.h>
  37 #include <asm/mach/pci.h>
  38
  39 #include <asm/hardware/pci_v3.h>
  40
  41 /*
  42  * The V3 PCI interface chip in Integrator provides several windows from
  43  * local bus memory into the PCI memory areas.   Unfortunately, there
  44  * are not really enough windows for our usage, therefore we reuse
  45  * one of the windows for access to PCI configuration space.  The
  46  * memory map is as follows:
  47  *
  48  * Local Bus Memory         Usage
  49  *
  50  * 40000000 - 4FFFFFFF      PCI memory.  256M non-prefetchable
  51  * 50000000 - 5FFFFFFF      PCI memory.  256M prefetchable
  52  * 60000000 - 60FFFFFF      PCI IO.  16M
  53  * 61000000 - 61FFFFFF      PCI Configuration. 16M
  54  *
  55  * There are three V3 windows, each described by a pair of V3 registers.
  56  * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
  57  * Base0 and Base1 can be used for any type of PCI memory access.   Base2
  58  * can be used either for PCI I/O or for I20 accesses.  By default, uHAL
  59  * uses this only for PCI IO space.
  60  *
  61  * Normally these spaces are mapped using the following base registers:
  62  *
  63  * Usage Local Bus Memory         Base/Map registers used
  64  *
  65  * Mem   40000000 - 4FFFFFFF      LB_BASE0/LB_MAP0
  66  * Mem   50000000 - 5FFFFFFF      LB_BASE1/LB_MAP1
  67  * IO    60000000 - 60FFFFFF      LB_BASE2/LB_MAP2
  68  * Cfg   61000000 - 61FFFFFF
  69  *
  70  * This means that I20 and PCI configuration space accesses will fail.
  71  * When PCI configuration accesses are needed (via the uHAL PCI
  72  * configuration space primitives) we must remap the spaces as follows:
  73  *
  74  * Usage Local Bus Memory         Base/Map registers used
  75  *
  76  * Mem   40000000 - 4FFFFFFF      LB_BASE0/LB_MAP0
  77  * Mem   50000000 - 5FFFFFFF      LB_BASE0/LB_MAP0
  78  * IO    60000000 - 60FFFFFF      LB_BASE2/LB_MAP2
  79  * Cfg   61000000 - 61FFFFFF      LB_BASE1/LB_MAP1
  80  *
  81  * To make this work, the code depends on overlapping windows working.
  82  * The V3 chip translates an address by checking its range within
  83  * each of the BASE/MAP pairs in turn (in ascending register number
  84  * order).  It will use the first matching pair.   So, for example,
  85  * if the same address is mapped by both LB_BASE0/LB_MAP0 and
  86  * LB_BASE1/LB_MAP1, the V3 will use the translation from
  87  * LB_BASE0/LB_MAP0.
  88  *
  89  * To allow PCI Configuration space access, the code enlarges the
  90  * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M.  This occludes
  91  * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
  92  * be remapped for use by configuration cycles.
  93  *
  94  * At the end of the PCI Configuration space accesses,
  95  * LB_BASE1/LB_MAP1 is reset to map PCI Memory.  Finally the window
  96  * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
  97  * reveal the now restored LB_BASE1/LB_MAP1 window.
  98  *
  99  * NOTE: We do not set up I2O mapping.  I suspect that this is only
 100  * for an intelligent (target) device.  Using I2O disables most of
 101  * the mappings into PCI memory.
 102  */
 103
 104 // V3 access routines
 105 #define v3_writeb(o,v) __raw_writeb(v, PCI_V3_VADDR + (unsigned int)(o))
 106 #define v3_readb(o)    (__raw_readb(PCI_V3_VADDR + (unsigned int)(o)))
 107
 108 #define v3_writew(o,v) __raw_writew(v, PCI_V3_VADDR + (unsigned int)(o))
 109 #define v3_readw(o)    (__raw_readw(PCI_V3_VADDR + (unsigned int)(o)))
 110
 111 #define v3_writel(o,v) __raw_writel(v, PCI_V3_VADDR + (unsigned int)(o))
 112 #define v3_readl(o)    (__raw_readl(PCI_V3_VADDR + (unsigned int)(o)))
 113
 114 /*============================================================================
 115  *
 116  * routine:     uHALir_PCIMakeConfigAddress()
 117  *
 118  * parameters:  bus = which bus
 119  *              device = which device
 120  *              function = which function
 121  *              offset = configuration space register we are interested in
 122  *
 123  * description: this routine will generate a platform dependent config
 124  *              address.
 125  *
 126  * calls:       none
 127  *
 128  * returns:     configuration address to play on the PCI bus
 129  *
 130  * To generate the appropriate PCI configuration cycles in the PCI
 131  * configuration address space, you present the V3 with the following pattern
 132  * (which is very nearly a type 1 (except that the lower two bits are 00 and
 133  * not 01).   In order for this mapping to work you need to set up one of
 134  * the local to PCI aperatures to 16Mbytes in length translating to
 135  * PCI configuration space starting at 0x0000.0000.
 136  *
 137  * PCI configuration cycles look like this:
 138  *
 139  * Type 0:
 140  *
 141  *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
 142  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
 143  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 144  * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
 145  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 146  *
 147  *      31:11   Device select bit.
 148  *      10:8    Function number
 149  *       7:2    Register number
 150  *
 151  * Type 1:
 152  *
 153  *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
 154  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
 155  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 156  * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
 157  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 158  *
 159  *      31:24   reserved
 160  *      23:16   bus number (8 bits = 128 possible buses)
 161  *      15:11   Device number (5 bits)
 162  *      10:8    function number
 163  *       7:2    register number
 164  *
 165  */
 166 static DEFINE_SPINLOCK(v3_lock);
 167
 168 #define PCI_BUS_NONMEM_START    0x00000000
 169 #define PCI_BUS_NONMEM_SIZE     SZ_256M
 170
 171 #define PCI_BUS_PREMEM_START    PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE
 172 #define PCI_BUS_PREMEM_SIZE     SZ_256M
 173
 174 #if PCI_BUS_NONMEM_START & 0x000fffff
 175 #error PCI_BUS_NONMEM_START must be megabyte aligned
 176 #endif
 177 #if PCI_BUS_PREMEM_START & 0x000fffff
 178 #error PCI_BUS_PREMEM_START must be megabyte aligned
 179 #endif
 180
 181 #undef V3_LB_BASE_PREFETCH
 182 #define V3_LB_BASE_PREFETCH 0
 183
 184 static unsigned long v3_open_config_window(struct pci_bus *bus,
 185                                            unsigned int devfn, int offset)
 186 {
 187         unsigned int address, mapaddress, busnr;
 188
 189         busnr = bus->number;
 190
 191         /*
 192          * Trap out illegal values
 193          */
 194         if (offset > 255)
 195                 BUG();
 196         if (busnr > 255)
 197                 BUG();
 198         if (devfn > 255)
 199                 BUG();
 200
 201         if (busnr == 0) {
 202                 int slot = PCI_SLOT(devfn);
 203
 204                 /*
 205                  * local bus segment so need a type 0 config cycle
 206                  *
 207                  * build the PCI configuration "address" with one-hot in
 208                  * A31-A11
 209                  *
 210                  * mapaddress:
 211                  *  3:1 = config cycle (101)
 212                  *  0   = PCI A1 & A0 are 0 (0)
 213                  */
 214                 address = PCI_FUNC(devfn) << 8;
 215                 mapaddress = V3_LB_MAP_TYPE_CONFIG;
 216
 217                 if (slot > 12)
 218                         /*
 219                          * high order bits are handled by the MAP register
 220                          */
 221                         mapaddress |= 1 << (slot - 5);
 222                 else
 223                         /*
 224                          * low order bits handled directly in the address
 225                          */
 226                         address |= 1 << (slot + 11);
 227         } else {
 228                 /*
 229                  * not the local bus segment so need a type 1 config cycle
 230                  *
 231                  * address:
 232                  *  23:16 = bus number
 233                  *  15:11 = slot number (7:3 of devfn)
 234                  *  10:8  = func number (2:0 of devfn)
 235                  *
 236                  * mapaddress:
 237                  *  3:1 = config cycle (101)
 238                  *  0   = PCI A1 & A0 from host bus (1)
 239                  */
 240                 mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
 241                 address = (busnr << 16) | (devfn << 8);
 242         }
 243
 244         /*
 245          * Set up base0 to see all 512Mbytes of memory space (not
 246          * prefetchable), this frees up base1 for re-use by
 247          * configuration memory
 248          */
 249         v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
 250                         V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
 251
 252         /*
 253          * Set up base1/map1 to point into configuration space.
 254          */
 255         v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
 256                         V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
 257         v3_writew(V3_LB_MAP1, mapaddress);
 258
 259         return PCI_CONFIG_VADDR + address + offset;
 260 }
 261
 262 static void v3_close_config_window(void)
 263 {
 264         /*
 265          * Reassign base1 for use by prefetchable PCI memory
 266          */
 267         v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
 268                         V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
 269                         V3_LB_BASE_ENABLE);
 270         v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
 271                         V3_LB_MAP_TYPE_MEM_MULTIPLE);
 272
 273         /*
 274          * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
 275          */
 276         v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
 277                         V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
 278 }
 279
 280 static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
 281                           int size, u32 *val)
 282 {
 283         unsigned long addr;
 284         unsigned long flags;
 285         u32 v;
 286
 287         spin_lock_irqsave(&v3_lock, flags);
 288         addr = v3_open_config_window(bus, devfn, where);
 289
 290         switch (size) {
 291         case 1:
 292                 v = __raw_readb(addr);
 293                 break;
 294
 295         case 2:
 296                 v = __raw_readw(addr);
 297                 break;
 298
 299         default:
 300                 v = __raw_readl(addr);
 301                 break;
 302         }
 303
 304         v3_close_config_window();
 305         spin_unlock_irqrestore(&v3_lock, flags);
 306
 307         *val = v;
 308         return PCIBIOS_SUCCESSFUL;
 309 }
 310
 311 static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
 312                            int size, u32 val)
 313 {
 314         unsigned long addr;
 315         unsigned long flags;
 316
 317         spin_lock_irqsave(&v3_lock, flags);
 318         addr = v3_open_config_window(bus, devfn, where);
 319
 320         switch (size) {
 321         case 1:
 322                 __raw_writeb((u8)val, addr);
 323                 __raw_readb(addr);
 324                 break;
 325
 326         case 2:
 327                 __raw_writew((u16)val, addr);
 328                 __raw_readw(addr);
 329                 break;
 330
 331         case 4:
 332                 __raw_writel(val, addr);
 333                 __raw_readl(addr);
 334                 break;
 335         }
 336
 337         v3_close_config_window();
 338         spin_unlock_irqrestore(&v3_lock, flags);
 339
 340         return PCIBIOS_SUCCESSFUL;
 341 }
 342
 343 static struct pci_ops pci_v3_ops = {
 344         .read   = v3_read_config,
 345         .write  = v3_write_config,
 346 };
 347
 348 static struct resource non_mem = {
 349         .name   = "PCI non-prefetchable",
 350         .start  = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START,
 351         .end    = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE - 1,
 352         .flags  = IORESOURCE_MEM,
 353 };
 354
 355 static struct resource pre_mem = {
 356         .name   = "PCI prefetchable",
 357         .start  = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START,
 358         .end    = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START + PCI_BUS_PREMEM_SIZE - 1,
 359         .flags  = IORESOURCE_MEM | IORESOURCE_PREFETCH,
 360 };
 361
 362 static int __init pci_v3_setup_resources(struct resource **resource)
 363 {
 364         if (request_resource(&iomem_resource, &non_mem)) {
 365                 printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
 366                        "memory region\n");
 367                 return -EBUSY;
 368         }
 369         if (request_resource(&iomem_resource, &pre_mem)) {
 370                 release_resource(&non_mem);
 371                 printk(KERN_ERR "PCI: unable to allocate prefetchable "
 372                        "memory region\n");
 373                 return -EBUSY;
 374         }
 375
 376         /*
 377          * bus->resource[0] is the IO resource for this bus
 378          * bus->resource[1] is the mem resource for this bus
 379          * bus->resource[2] is the prefetch mem resource for this bus
 380          */
 381         resource[0] = &ioport_resource;
 382         resource[1] = &non_mem;
 383         resource[2] = &pre_mem;
 384
 385         return 1;
 386 }
 387
 388 /*
 389  * These don't seem to be implemented on the Integrator I have, which
 390  * means I can't get additional information on the reason for the pm2fb
 391  * problems.  I suppose I'll just have to mind-meld with the machine. ;)
 392  */
 393 #define SC_PCI     (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_PCIENABLE_OFFSET)
 394 #define SC_LBFADDR (IO_ADDRESS(INTEGRATOR_SC_BASE) + 0x20)
 395 #define SC_LBFCODE (IO_ADDRESS(INTEGRATOR_SC_BASE) + 0x24)
 396
 397 static int
 398 v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 399 {
 400         unsigned long pc = instruction_pointer(regs);
 401         unsigned long instr = *(unsigned long *)pc;
 402 #if 0
 403         char buf[128];
 404
 405         sprintf(buf, "V3 fault: addr 0x%08lx, FSR 0x%03x, PC 0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
 406                 addr, fsr, pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255,
 407                 v3_readb(V3_LB_ISTAT));
 408         printk(KERN_DEBUG "%s", buf);
 409         printascii(buf);
 410 #endif
 411
 412         v3_writeb(V3_LB_ISTAT, 0);
 413         __raw_writel(3, SC_PCI);
 414
 415         /*
 416          * If the instruction being executed was a read,
 417          * make it look like it read all-ones.
 418          */
 419         if ((instr & 0x0c100000) == 0x04100000) {
 420                 int reg = (instr >> 12) & 15;
 421                 unsigned long val;
 422
 423                 if (instr & 0x00400000)
 424                         val = 255;
 425                 else
 426                         val = -1;
 427
 428                 regs->uregs[reg] = val;
 429                 regs->ARM_pc += 4;
 430                 return 0;
 431         }
 432
 433         if ((instr & 0x0e100090) == 0x00100090) {
 434                 int reg = (instr >> 12) & 15;
 435
 436                 regs->uregs[reg] = -1;
 437                 regs->ARM_pc += 4;
 438                 return 0;
 439         }
 440
 441         return 1;
 442 }
 443
 444 static irqreturn_t v3_irq(int irq, void *devid, struct pt_regs *regs)
 445 {
 446 #ifdef CONFIG_DEBUG_LL
 447         unsigned long pc = instruction_pointer(regs);
 448         unsigned long instr = *(unsigned long *)pc;
 449         char buf[128];
 450
 451         sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n", irq,
 452                 pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255,
 453                 v3_readb(V3_LB_ISTAT));
 454         printascii(buf);
 455 #endif
 456
 457         v3_writew(V3_PCI_STAT, 0xf000);
 458         v3_writeb(V3_LB_ISTAT, 0);
 459         __raw_writel(3, SC_PCI);
 460
 461 #ifdef CONFIG_DEBUG_LL
 462         /*
 463          * If the instruction being executed was a read,
 464          * make it look like it read all-ones.
 465          */
 466         if ((instr & 0x0c100000) == 0x04100000) {
 467                 int reg = (instr >> 16) & 15;
 468                 sprintf(buf, "   reg%d = %08lx\n", reg, regs->uregs[reg]);
 469                 printascii(buf);
 470         }
 471 #endif
 472         return IRQ_HANDLED;
 473 }
 474
 475 int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
 476 {
 477         int ret = 0;
 478
 479         if (nr == 0) {
 480                 sys->mem_offset = PHYS_PCI_MEM_BASE;
 481                 ret = pci_v3_setup_resources(sys->resource);
 482         }
 483
 484         return ret;
 485 }
 486
 487 struct pci_bus *pci_v3_scan_bus(int nr, struct pci_sys_data *sys)
 488 {
 489         return pci_scan_bus(sys->busnr, &pci_v3_ops, sys);
 490 }
 491
 492 /*
 493  * V3_LB_BASE? - local bus address
 494  * V3_LB_MAP?  - pci bus address
 495  */
 496 void __init pci_v3_preinit(void)
 497 {
 498         unsigned long flags;
 499         unsigned int temp;
 500         int ret;
 501
 502         /*
 503          * Hook in our fault handler for PCI errors
 504          */
 505         hook_fault_code(4, v3_pci_fault, SIGBUS, "external abort on linefetch");
 506         hook_fault_code(6, v3_pci_fault, SIGBUS, "external abort on linefetch");
 507         hook_fault_code(8, v3_pci_fault, SIGBUS, "external abort on non-linefetch");
 508         hook_fault_code(10, v3_pci_fault, SIGBUS, "external abort on non-linefetch");
 509
 510         spin_lock_irqsave(&v3_lock, flags);
 511
 512         /*
 513          * Unlock V3 registers, but only if they were previously locked.
 514          */
 515         if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
 516                 v3_writew(V3_SYSTEM, 0xa05f);
 517
 518         /*
 519          * Setup window 0 - PCI non-prefetchable memory
 520          *  Local: 0x40000000 Bus: 0x00000000 Size: 256MB
 521          */
 522         v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
 523                         V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
 524         v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) |
 525                         V3_LB_MAP_TYPE_MEM);
 526
 527         /*
 528          * Setup window 1 - PCI prefetchable memory
 529          *  Local: 0x50000000 Bus: 0x10000000 Size: 256MB
 530          */
 531         v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
 532                         V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
 533                         V3_LB_BASE_ENABLE);
 534         v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
 535                         V3_LB_MAP_TYPE_MEM_MULTIPLE);
 536
 537         /*
 538          * Setup window 2 - PCI IO
 539          */
 540         v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(PHYS_PCI_IO_BASE) |
 541                         V3_LB_BASE_ENABLE);
 542         v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
 543
 544         /*
 545          * Disable PCI to host IO cycles
 546          */
 547         temp = v3_readw(V3_PCI_CFG) & ~V3_PCI_CFG_M_I2O_EN;
 548         temp |= V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS;
 549         v3_writew(V3_PCI_CFG, temp);
 550
 551         printk(KERN_DEBUG "FIFO_CFG: %04x  FIFO_PRIO: %04x\n",
 552                 v3_readw(V3_FIFO_CFG), v3_readw(V3_FIFO_PRIORITY));
 553
 554         /*
 555          * Set the V3 FIFO such that writes have higher priority than
 556          * reads, and local bus write causes local bus read fifo flush.
 557          * Same for PCI.
 558          */
 559         v3_writew(V3_FIFO_PRIORITY, 0x0a0a);
 560
 561         /*
 562          * Re-lock the system register.
 563          */
 564         temp = v3_readw(V3_SYSTEM) | V3_SYSTEM_M_LOCK;
 565         v3_writew(V3_SYSTEM, temp);
 566
 567         /*
 568          * Clear any error conditions, and enable write errors.
 569          */
 570         v3_writeb(V3_LB_ISTAT, 0);
 571         v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
 572         v3_writeb(V3_LB_IMASK, 0x28);
 573         __raw_writel(3, SC_PCI);
 574
 575         /*
 576          * Grab the PCI error interrupt.
 577          */
 578         ret = request_irq(IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
 579         if (ret)
 580                 printk(KERN_ERR "PCI: unable to grab PCI error "
 581                        "interrupt: %d\n", ret);
 582
 583         spin_unlock_irqrestore(&v3_lock, flags);
 584 }
 585
 586 void __init pci_v3_postinit(void)
 587 {
 588         unsigned int pci_cmd;
 589
 590         pci_cmd = PCI_COMMAND_MEMORY |
 591                   PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
 592
 593         v3_writew(V3_PCI_CMD, pci_cmd);
 594
 595         v3_writeb(V3_LB_ISTAT, ~0x40);
 596         v3_writeb(V3_LB_IMASK, 0x68);
 597
 598 #if 0
 599         ret = request_irq(IRQ_AP_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL);
 600         if (ret)
 601                 printk(KERN_ERR "PCI: unable to grab local bus timeout "
 602                        "interrupt: %d\n", ret);
 603 #endif
 604 }