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ARM: Indirect round/set_rate operations through clk structure
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-integrator / integrator_cp.c
1 /*
2 * linux/arch/arm/mach-integrator/integrator_cp.c
3 *
4 * Copyright (C) 2003 Deep Blue Solutions Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
9 */
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/list.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/slab.h>
17 #include <linux/string.h>
18 #include <linux/sysdev.h>
19 #include <linux/amba/bus.h>
20 #include <linux/amba/kmi.h>
21 #include <linux/amba/clcd.h>
22 #include <linux/amba/mmci.h>
23 #include <linux/io.h>
24
25 #include <asm/clkdev.h>
26 #include <mach/clkdev.h>
27 #include <mach/hardware.h>
28 #include <mach/platform.h>
29 #include <asm/irq.h>
30 #include <asm/setup.h>
31 #include <asm/mach-types.h>
32 #include <asm/hardware/arm_timer.h>
33 #include <asm/hardware/icst.h>
34
35 #include <mach/cm.h>
36 #include <mach/lm.h>
37
38 #include <asm/mach/arch.h>
39 #include <asm/mach/flash.h>
40 #include <asm/mach/irq.h>
41 #include <asm/mach/map.h>
42 #include <asm/mach/time.h>
43
44 #include <plat/timer-sp.h>
45
46 #define INTCP_PA_FLASH_BASE 0x24000000
47 #define INTCP_FLASH_SIZE SZ_32M
48
49 #define INTCP_PA_CLCD_BASE 0xc0000000
50
51 #define INTCP_VA_CIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x40)
52 #define INTCP_VA_PIC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE)
53 #define INTCP_VA_SIC_BASE IO_ADDRESS(INTEGRATOR_CP_SIC_BASE)
54
55 #define INTCP_ETH_SIZE 0x10
56
57 #define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
58 #define INTCP_FLASHPROG 0x04
59 #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
60 #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
61
62 /*
63 * Logical Physical
64 * f1000000 10000000 Core module registers
65 * f1100000 11000000 System controller registers
66 * f1200000 12000000 EBI registers
67 * f1300000 13000000 Counter/Timer
68 * f1400000 14000000 Interrupt controller
69 * f1600000 16000000 UART 0
70 * f1700000 17000000 UART 1
71 * f1a00000 1a000000 Debug LEDs
72 * fc900000 c9000000 GPIO
73 * fca00000 ca000000 SIC
74 * fcb00000 cb000000 CP system control
75 */
76
77 static struct map_desc intcp_io_desc[] __initdata = {
78 {
79 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
80 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
81 .length = SZ_4K,
82 .type = MT_DEVICE
83 }, {
84 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
85 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
86 .length = SZ_4K,
87 .type = MT_DEVICE
88 }, {
89 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
90 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
91 .length = SZ_4K,
92 .type = MT_DEVICE
93 }, {
94 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
95 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
96 .length = SZ_4K,
97 .type = MT_DEVICE
98 }, {
99 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
100 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
101 .length = SZ_4K,
102 .type = MT_DEVICE
103 }, {
104 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
105 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
106 .length = SZ_4K,
107 .type = MT_DEVICE
108 }, {
109 .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
110 .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
111 .length = SZ_4K,
112 .type = MT_DEVICE
113 }, {
114 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
115 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
116 .length = SZ_4K,
117 .type = MT_DEVICE
118 }, {
119 .virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
120 .pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
121 .length = SZ_4K,
122 .type = MT_DEVICE
123 }, {
124 .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
125 .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
126 .length = SZ_4K,
127 .type = MT_DEVICE
128 }, {
129 .virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
130 .pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
131 .length = SZ_4K,
132 .type = MT_DEVICE
133 }
134 };
135
136 static void __init intcp_map_io(void)
137 {
138 iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
139 }
140
141 #define cic_writel __raw_writel
142 #define cic_readl __raw_readl
143 #define pic_writel __raw_writel
144 #define pic_readl __raw_readl
145 #define sic_writel __raw_writel
146 #define sic_readl __raw_readl
147
148 static void cic_mask_irq(unsigned int irq)
149 {
150 irq -= IRQ_CIC_START;
151 cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
152 }
153
154 static void cic_unmask_irq(unsigned int irq)
155 {
156 irq -= IRQ_CIC_START;
157 cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
158 }
159
160 static struct irq_chip cic_chip = {
161 .name = "CIC",
162 .ack = cic_mask_irq,
163 .mask = cic_mask_irq,
164 .unmask = cic_unmask_irq,
165 };
166
167 static void pic_mask_irq(unsigned int irq)
168 {
169 irq -= IRQ_PIC_START;
170 pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
171 }
172
173 static void pic_unmask_irq(unsigned int irq)
174 {
175 irq -= IRQ_PIC_START;
176 pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
177 }
178
179 static struct irq_chip pic_chip = {
180 .name = "PIC",
181 .ack = pic_mask_irq,
182 .mask = pic_mask_irq,
183 .unmask = pic_unmask_irq,
184 };
185
186 static void sic_mask_irq(unsigned int irq)
187 {
188 irq -= IRQ_SIC_START;
189 sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
190 }
191
192 static void sic_unmask_irq(unsigned int irq)
193 {
194 irq -= IRQ_SIC_START;
195 sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
196 }
197
198 static struct irq_chip sic_chip = {
199 .name = "SIC",
200 .ack = sic_mask_irq,
201 .mask = sic_mask_irq,
202 .unmask = sic_unmask_irq,
203 };
204
205 static void
206 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
207 {
208 unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
209
210 if (status == 0) {
211 do_bad_IRQ(irq, desc);
212 return;
213 }
214
215 do {
216 irq = ffs(status) - 1;
217 status &= ~(1 << irq);
218
219 irq += IRQ_SIC_START;
220
221 generic_handle_irq(irq);
222 } while (status);
223 }
224
225 static void __init intcp_init_irq(void)
226 {
227 unsigned int i;
228
229 /*
230 * Disable all interrupt sources
231 */
232 pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
233 pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
234
235 for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
236 if (i == 11)
237 i = 22;
238 if (i == 29)
239 break;
240 set_irq_chip(i, &pic_chip);
241 set_irq_handler(i, handle_level_irq);
242 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
243 }
244
245 cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
246 cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
247
248 for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
249 set_irq_chip(i, &cic_chip);
250 set_irq_handler(i, handle_level_irq);
251 set_irq_flags(i, IRQF_VALID);
252 }
253
254 sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
255 sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
256
257 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
258 set_irq_chip(i, &sic_chip);
259 set_irq_handler(i, handle_level_irq);
260 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
261 }
262
263 set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
264 }
265
266 /*
267 * Clock handling
268 */
269 #define CM_LOCK (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
270 #define CM_AUXOSC (__io_address(INTEGRATOR_HDR_BASE)+0x1c)
271
272 static const struct icst_params cp_auxvco_params = {
273 .ref = 24000000,
274 .vco_max = ICST525_VCO_MAX_5V,
275 .vco_min = ICST525_VCO_MIN,
276 .vd_min = 8,
277 .vd_max = 263,
278 .rd_min = 3,
279 .rd_max = 65,
280 .s2div = icst525_s2div,
281 .idx2s = icst525_idx2s,
282 };
283
284 static void cp_auxvco_set(struct clk *clk, struct icst_vco vco)
285 {
286 u32 val;
287
288 val = readl(clk->vcoreg) & ~0x7ffff;
289 val |= vco.v | (vco.r << 9) | (vco.s << 16);
290
291 writel(0xa05f, CM_LOCK);
292 writel(val, clk->vcoreg);
293 writel(0, CM_LOCK);
294 }
295
296 static const struct clk_ops cp_auxclk_ops = {
297 .round = icst_clk_round,
298 .set = icst_clk_set,
299 .setvco = cp_auxvco_set,
300 };
301
302 static struct clk cp_auxclk = {
303 .ops = &cp_auxclk_ops,
304 .params = &cp_auxvco_params,
305 .vcoreg = CM_AUXOSC,
306 };
307
308 static struct clk_lookup cp_lookups[] = {
309 { /* CLCD */
310 .dev_id = "mb:c0",
311 .clk = &cp_auxclk,
312 },
313 };
314
315 /*
316 * Flash handling.
317 */
318 static int intcp_flash_init(void)
319 {
320 u32 val;
321
322 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
323 val |= CINTEGRATOR_FLASHPROG_FLWREN;
324 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
325
326 return 0;
327 }
328
329 static void intcp_flash_exit(void)
330 {
331 u32 val;
332
333 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
334 val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
335 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
336 }
337
338 static void intcp_flash_set_vpp(int on)
339 {
340 u32 val;
341
342 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
343 if (on)
344 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
345 else
346 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
347 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
348 }
349
350 static struct flash_platform_data intcp_flash_data = {
351 .map_name = "cfi_probe",
352 .width = 4,
353 .init = intcp_flash_init,
354 .exit = intcp_flash_exit,
355 .set_vpp = intcp_flash_set_vpp,
356 };
357
358 static struct resource intcp_flash_resource = {
359 .start = INTCP_PA_FLASH_BASE,
360 .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
361 .flags = IORESOURCE_MEM,
362 };
363
364 static struct platform_device intcp_flash_device = {
365 .name = "armflash",
366 .id = 0,
367 .dev = {
368 .platform_data = &intcp_flash_data,
369 },
370 .num_resources = 1,
371 .resource = &intcp_flash_resource,
372 };
373
374 static struct resource smc91x_resources[] = {
375 [0] = {
376 .start = INTEGRATOR_CP_ETH_BASE,
377 .end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
378 .flags = IORESOURCE_MEM,
379 },
380 [1] = {
381 .start = IRQ_CP_ETHINT,
382 .end = IRQ_CP_ETHINT,
383 .flags = IORESOURCE_IRQ,
384 },
385 };
386
387 static struct platform_device smc91x_device = {
388 .name = "smc91x",
389 .id = 0,
390 .num_resources = ARRAY_SIZE(smc91x_resources),
391 .resource = smc91x_resources,
392 };
393
394 static struct platform_device *intcp_devs[] __initdata = {
395 &intcp_flash_device,
396 &smc91x_device,
397 };
398
399 /*
400 * It seems that the card insertion interrupt remains active after
401 * we've acknowledged it. We therefore ignore the interrupt, and
402 * rely on reading it from the SIC. This also means that we must
403 * clear the latched interrupt.
404 */
405 static unsigned int mmc_status(struct device *dev)
406 {
407 unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
408 writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
409
410 return status & 8;
411 }
412
413 static struct mmci_platform_data mmc_data = {
414 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
415 .status = mmc_status,
416 .gpio_wp = -1,
417 .gpio_cd = -1,
418 };
419
420 static struct amba_device mmc_device = {
421 .dev = {
422 .init_name = "mb:1c",
423 .platform_data = &mmc_data,
424 },
425 .res = {
426 .start = INTEGRATOR_CP_MMC_BASE,
427 .end = INTEGRATOR_CP_MMC_BASE + SZ_4K - 1,
428 .flags = IORESOURCE_MEM,
429 },
430 .irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
431 .periphid = 0,
432 };
433
434 static struct amba_device aaci_device = {
435 .dev = {
436 .init_name = "mb:1d",
437 },
438 .res = {
439 .start = INTEGRATOR_CP_AACI_BASE,
440 .end = INTEGRATOR_CP_AACI_BASE + SZ_4K - 1,
441 .flags = IORESOURCE_MEM,
442 },
443 .irq = { IRQ_CP_AACIINT, NO_IRQ },
444 .periphid = 0,
445 };
446
447
448 /*
449 * CLCD support
450 */
451 static struct clcd_panel vga = {
452 .mode = {
453 .name = "VGA",
454 .refresh = 60,
455 .xres = 640,
456 .yres = 480,
457 .pixclock = 39721,
458 .left_margin = 40,
459 .right_margin = 24,
460 .upper_margin = 32,
461 .lower_margin = 11,
462 .hsync_len = 96,
463 .vsync_len = 2,
464 .sync = 0,
465 .vmode = FB_VMODE_NONINTERLACED,
466 },
467 .width = -1,
468 .height = -1,
469 .tim2 = TIM2_BCD | TIM2_IPC,
470 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
471 .bpp = 16,
472 .grayscale = 0,
473 };
474
475 /*
476 * Ensure VGA is selected.
477 */
478 static void cp_clcd_enable(struct clcd_fb *fb)
479 {
480 u32 val;
481
482 if (fb->fb.var.bits_per_pixel <= 8)
483 val = CM_CTRL_LCDMUXSEL_VGA_8421BPP;
484 else if (fb->fb.var.bits_per_pixel <= 16)
485 val = CM_CTRL_LCDMUXSEL_VGA_16BPP
486 | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1
487 | CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
488 else
489 val = 0; /* no idea for this, don't trust the docs */
490
491 cm_control(CM_CTRL_LCDMUXSEL_MASK|
492 CM_CTRL_LCDEN0|
493 CM_CTRL_LCDEN1|
494 CM_CTRL_STATIC1|
495 CM_CTRL_STATIC2|
496 CM_CTRL_STATIC|
497 CM_CTRL_n24BITEN, val);
498 }
499
500 static unsigned long framesize = SZ_1M;
501
502 static int cp_clcd_setup(struct clcd_fb *fb)
503 {
504 dma_addr_t dma;
505
506 fb->panel = &vga;
507
508 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
509 &dma, GFP_KERNEL);
510 if (!fb->fb.screen_base) {
511 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
512 return -ENOMEM;
513 }
514
515 fb->fb.fix.smem_start = dma;
516 fb->fb.fix.smem_len = framesize;
517
518 return 0;
519 }
520
521 static int cp_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
522 {
523 return dma_mmap_writecombine(&fb->dev->dev, vma,
524 fb->fb.screen_base,
525 fb->fb.fix.smem_start,
526 fb->fb.fix.smem_len);
527 }
528
529 static void cp_clcd_remove(struct clcd_fb *fb)
530 {
531 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
532 fb->fb.screen_base, fb->fb.fix.smem_start);
533 }
534
535 static struct clcd_board clcd_data = {
536 .name = "Integrator/CP",
537 .check = clcdfb_check,
538 .decode = clcdfb_decode,
539 .enable = cp_clcd_enable,
540 .setup = cp_clcd_setup,
541 .mmap = cp_clcd_mmap,
542 .remove = cp_clcd_remove,
543 };
544
545 static struct amba_device clcd_device = {
546 .dev = {
547 .init_name = "mb:c0",
548 .coherent_dma_mask = ~0,
549 .platform_data = &clcd_data,
550 },
551 .res = {
552 .start = INTCP_PA_CLCD_BASE,
553 .end = INTCP_PA_CLCD_BASE + SZ_4K - 1,
554 .flags = IORESOURCE_MEM,
555 },
556 .dma_mask = ~0,
557 .irq = { IRQ_CP_CLCDCINT, NO_IRQ },
558 .periphid = 0,
559 };
560
561 static struct amba_device *amba_devs[] __initdata = {
562 &mmc_device,
563 &aaci_device,
564 &clcd_device,
565 };
566
567 static void __init intcp_init(void)
568 {
569 int i;
570
571 clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
572 platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
573
574 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
575 struct amba_device *d = amba_devs[i];
576 amba_device_register(d, &iomem_resource);
577 }
578 }
579
580 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
581 #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
582 #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
583
584 static void __init intcp_timer_init(void)
585 {
586 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
587 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
588 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
589
590 sp804_clocksource_init(TIMER2_VA_BASE);
591 sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1);
592 }
593
594 static struct sys_timer cp_timer = {
595 .init = intcp_timer_init,
596 };
597
598 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
599 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
600 .phys_io = 0x16000000,
601 .io_pg_offst = ((0xf1600000) >> 18) & 0xfffc,
602 .boot_params = 0x00000100,
603 .map_io = intcp_map_io,
604 .init_irq = intcp_init_irq,
605 .timer = &cp_timer,
606 .init_machine = intcp_init,
607 MACHINE_END
kernel source for telekom puls (alcatel/mediatek)