arch/arm/mach-imx/mach-mx21ads.c

   1 /*
   2  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   3  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   4  *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/platform_device.h>
  18 #include <linux/mtd/mtd.h>
  19 #include <linux/mtd/physmap.h>
  20 #include <linux/gpio.h>
  21 #include <mach/common.h>
  22 #include <mach/hardware.h>
  23 #include <asm/mach-types.h>
  24 #include <asm/mach/arch.h>
  25 #include <asm/mach/time.h>
  26 #include <asm/mach/map.h>
  27 #include <mach/imx-uart.h>
  28 #include <mach/imxfb.h>
  29 #include <mach/iomux-mx21.h>
  30 #include <mach/mxc_nand.h>
  31 #include <mach/mmc.h>
  32
  33 #include "devices-imx21.h"
  34 #include "devices.h"
  35
  36 /*
  37  * Memory-mapped I/O on MX21ADS base board
  38  */
  39 #define MX21ADS_MMIO_BASE_ADDR   0xf5000000
  40 #define MX21ADS_MMIO_SIZE        SZ_16M
  41
  42 #define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
  43                 (MX21ADS_MMIO_BASE_ADDR + (offset))
  44
  45 #define MX21ADS_CS8900A_IRQ         IRQ_GPIOE(11)
  46 #define MX21ADS_CS8900A_IOBASE_REG  MX21ADS_REG_ADDR(0x000000)
  47 #define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
  48 #define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)
  49 #define MX21ADS_IO_REG              MX21ADS_REG_ADDR(0x800000)
  50
  51 /* MX21ADS_IO_REG bit definitions */
  52 #define MX21ADS_IO_SD_WP        0x0001 /* read */
  53 #define MX21ADS_IO_TP6          0x0001 /* write */
  54 #define MX21ADS_IO_SW_SEL       0x0002 /* read */
  55 #define MX21ADS_IO_TP7          0x0002 /* write */
  56 #define MX21ADS_IO_RESET_E_UART 0x0004
  57 #define MX21ADS_IO_RESET_BASE   0x0008
  58 #define MX21ADS_IO_CSI_CTL2     0x0010
  59 #define MX21ADS_IO_CSI_CTL1     0x0020
  60 #define MX21ADS_IO_CSI_CTL0     0x0040
  61 #define MX21ADS_IO_UART1_EN     0x0080
  62 #define MX21ADS_IO_UART4_EN     0x0100
  63 #define MX21ADS_IO_LCDON        0x0200
  64 #define MX21ADS_IO_IRDA_EN      0x0400
  65 #define MX21ADS_IO_IRDA_FIR_SEL 0x0800
  66 #define MX21ADS_IO_IRDA_MD0_B   0x1000
  67 #define MX21ADS_IO_IRDA_MD1     0x2000
  68 #define MX21ADS_IO_LED4_ON      0x4000
  69 #define MX21ADS_IO_LED3_ON      0x8000
  70
  71 static unsigned int mx21ads_pins[] = {
  72
  73         /* CS8900A */
  74         (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11),
  75
  76         /* UART1 */
  77         PE12_PF_UART1_TXD,
  78         PE13_PF_UART1_RXD,
  79         PE14_PF_UART1_CTS,
  80         PE15_PF_UART1_RTS,
  81
  82         /* UART3 (IrDA) - only TXD and RXD */
  83         PE8_PF_UART3_TXD,
  84         PE9_PF_UART3_RXD,
  85
  86         /* UART4 */
  87         PB26_AF_UART4_RTS,
  88         PB28_AF_UART4_TXD,
  89         PB29_AF_UART4_CTS,
  90         PB31_AF_UART4_RXD,
  91
  92         /* LCDC */
  93         PA5_PF_LSCLK,
  94         PA6_PF_LD0,
  95         PA7_PF_LD1,
  96         PA8_PF_LD2,
  97         PA9_PF_LD3,
  98         PA10_PF_LD4,
  99         PA11_PF_LD5,
 100         PA12_PF_LD6,
 101         PA13_PF_LD7,
 102         PA14_PF_LD8,
 103         PA15_PF_LD9,
 104         PA16_PF_LD10,
 105         PA17_PF_LD11,
 106         PA18_PF_LD12,
 107         PA19_PF_LD13,
 108         PA20_PF_LD14,
 109         PA21_PF_LD15,
 110         PA22_PF_LD16,
 111         PA24_PF_REV,     /* Sharp panel dedicated signal */
 112         PA25_PF_CLS,     /* Sharp panel dedicated signal */
 113         PA26_PF_PS,      /* Sharp panel dedicated signal */
 114         PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */
 115         PA28_PF_HSYNC,
 116         PA29_PF_VSYNC,
 117         PA30_PF_CONTRAST,
 118         PA31_PF_OE_ACD,
 119
 120         /* MMC/SDHC */
 121         PE18_PF_SD1_D0,
 122         PE19_PF_SD1_D1,
 123         PE20_PF_SD1_D2,
 124         PE21_PF_SD1_D3,
 125         PE22_PF_SD1_CMD,
 126         PE23_PF_SD1_CLK,
 127
 128         /* NFC */
 129         PF0_PF_NRFB,
 130         PF1_PF_NFCE,
 131         PF2_PF_NFWP,
 132         PF3_PF_NFCLE,
 133         PF4_PF_NFALE,
 134         PF5_PF_NFRE,
 135         PF6_PF_NFWE,
 136         PF7_PF_NFIO0,
 137         PF8_PF_NFIO1,
 138         PF9_PF_NFIO2,
 139         PF10_PF_NFIO3,
 140         PF11_PF_NFIO4,
 141         PF12_PF_NFIO5,
 142         PF13_PF_NFIO6,
 143         PF14_PF_NFIO7,
 144 };
 145
 146 /* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */
 147 static struct physmap_flash_data mx21ads_flash_data = {
 148         .width = 4,
 149 };
 150
 151 static struct resource mx21ads_flash_resource = {
 152         .start = MX21_CS0_BASE_ADDR,
 153         .end = MX21_CS0_BASE_ADDR + 0x02000000 - 1,
 154         .flags = IORESOURCE_MEM,
 155 };
 156
 157 static struct platform_device mx21ads_nor_mtd_device = {
 158         .name = "physmap-flash",
 159         .id = 0,
 160         .dev = {
 161                 .platform_data = &mx21ads_flash_data,
 162         },
 163         .num_resources = 1,
 164         .resource = &mx21ads_flash_resource,
 165 };
 166
 167 static struct imxuart_platform_data uart_pdata = {
 168         .flags = IMXUART_HAVE_RTSCTS,
 169 };
 170
 171 static struct imxuart_platform_data uart_norts_pdata = {
 172 };
 173
 174
 175 static int mx21ads_fb_init(struct platform_device *pdev)
 176 {
 177         u16 tmp;
 178
 179         tmp = __raw_readw(MX21ADS_IO_REG);
 180         tmp |= MX21ADS_IO_LCDON;
 181         __raw_writew(tmp, MX21ADS_IO_REG);
 182         return 0;
 183 }
 184
 185 static void mx21ads_fb_exit(struct platform_device *pdev)
 186 {
 187         u16 tmp;
 188
 189         tmp = __raw_readw(MX21ADS_IO_REG);
 190         tmp &= ~MX21ADS_IO_LCDON;
 191         __raw_writew(tmp, MX21ADS_IO_REG);
 192 }
 193
 194 /*
 195  * Connected is a portrait Sharp-QVGA display
 196  * of type: LQ035Q7DB02
 197  */
 198 static struct imx_fb_videomode mx21ads_modes[] = {
 199         {
 200                 .mode = {
 201                         .name           = "Sharp-LQ035Q7",
 202                         .refresh        = 60,
 203                         .xres           = 240,
 204                         .yres           = 320,
 205                         .pixclock       = 188679, /* in ps (5.3MHz) */
 206                         .hsync_len      = 2,
 207                         .left_margin    = 6,
 208                         .right_margin   = 16,
 209                         .vsync_len      = 1,
 210                         .upper_margin   = 8,
 211                         .lower_margin   = 10,
 212                 },
 213                 .pcr            = 0xfb108bc7,
 214                 .bpp            = 16,
 215         },
 216 };
 217
 218 static struct imx_fb_platform_data mx21ads_fb_data = {
 219         .mode = mx21ads_modes,
 220         .num_modes = ARRAY_SIZE(mx21ads_modes),
 221
 222         .pwmr           = 0x00a903ff,
 223         .lscr1          = 0x00120300,
 224         .dmacr          = 0x00020008,
 225
 226         .init = mx21ads_fb_init,
 227         .exit = mx21ads_fb_exit,
 228 };
 229
 230 static int mx21ads_sdhc_get_ro(struct device *dev)
 231 {
 232         return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0;
 233 }
 234
 235 static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
 236         void *data)
 237 {
 238         int ret;
 239
 240         ret = request_irq(IRQ_GPIOD(25), detect_irq,
 241                 IRQF_TRIGGER_FALLING, "mmc-detect", data);
 242         if (ret)
 243                 goto out;
 244         return 0;
 245 out:
 246         return ret;
 247 }
 248
 249 static void mx21ads_sdhc_exit(struct device *dev, void *data)
 250 {
 251         free_irq(IRQ_GPIOD(25), data);
 252 }
 253
 254 static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
 255         .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */
 256         .get_ro = mx21ads_sdhc_get_ro,
 257         .init = mx21ads_sdhc_init,
 258         .exit = mx21ads_sdhc_exit,
 259 };
 260
 261 static const struct mxc_nand_platform_data
 262 mx21ads_nand_board_info __initconst = {
 263         .width = 1,
 264         .hw_ecc = 1,
 265 };
 266
 267 static struct map_desc mx21ads_io_desc[] __initdata = {
 268         /*
 269          * Memory-mapped I/O on MX21ADS Base board:
 270          *   - CS8900A Ethernet controller
 271          *   - ST16C2552CJ UART
 272          *   - CPU and Base board version
 273          *   - Base board I/O register
 274          */
 275         {
 276                 .virtual = MX21ADS_MMIO_BASE_ADDR,
 277                 .pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR),
 278                 .length = MX21ADS_MMIO_SIZE,
 279                 .type = MT_DEVICE,
 280         },
 281 };
 282
 283 static void __init mx21ads_map_io(void)
 284 {
 285         mx21_map_io();
 286         iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc));
 287 }
 288
 289 static struct platform_device *platform_devices[] __initdata = {
 290         &mx21ads_nor_mtd_device,
 291 };
 292
 293 static void __init mx21ads_board_init(void)
 294 {
 295         mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
 296                         "mx21ads");
 297
 298         mxc_register_device(&imx2x_uart_device0, &uart_pdata);
 299         mxc_register_device(&imx2x_uart_device2, &uart_norts_pdata);
 300         mxc_register_device(&imx2x_uart_device3, &uart_pdata);
 301         mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
 302         mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
 303         imx21_add_mxc_nand(&mx21ads_nand_board_info);
 304
 305         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 306 }
 307
 308 static void __init mx21ads_timer_init(void)
 309 {
 310         mx21_clocks_init(32768, 26000000);
 311 }
 312
 313 static struct sys_timer mx21ads_timer = {
 314         .init   = mx21ads_timer_init,
 315 };
 316
 317 MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
 318         /* maintainer: Freescale Semiconductor, Inc. */
 319         .phys_io        = MX21_AIPI_BASE_ADDR,
 320         .io_pg_offst    = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
 321         .boot_params    = MX21_PHYS_OFFSET + 0x100,
 322         .map_io         = mx21ads_map_io,
 323         .init_irq       = mx21_init_irq,
 324         .init_machine   = mx21ads_board_init,
 325         .timer          = &mx21ads_timer,
 326 MACHINE_END