Linux-2.6.12-rc2
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-footbridge / common.c
1 /*
2 * linux/arch/arm/mach-footbridge/common.c
3 *
4 * Copyright (C) 1998-2000 Russell King, Dave Gilbert.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/config.h>
11 #include <linux/module.h>
12 #include <linux/types.h>
13 #include <linux/mm.h>
14 #include <linux/ioport.h>
15 #include <linux/list.h>
16 #include <linux/init.h>
17
18 #include <asm/pgtable.h>
19 #include <asm/page.h>
20 #include <asm/irq.h>
21 #include <asm/io.h>
22 #include <asm/mach-types.h>
23 #include <asm/setup.h>
24 #include <asm/hardware/dec21285.h>
25
26 #include <asm/mach/irq.h>
27 #include <asm/mach/map.h>
28
29 #include "common.h"
30
31 extern void __init isa_init_irq(unsigned int irq);
32
33 unsigned int mem_fclk_21285 = 50000000;
34
35 EXPORT_SYMBOL(mem_fclk_21285);
36
37 static int __init parse_tag_memclk(const struct tag *tag)
38 {
39 mem_fclk_21285 = tag->u.memclk.fmemclk;
40 return 0;
41 }
42
43 __tagtable(ATAG_MEMCLK, parse_tag_memclk);
44
45 /*
46 * Footbridge IRQ translation table
47 * Converts from our IRQ numbers into FootBridge masks
48 */
49 static const int fb_irq_mask[] = {
50 IRQ_MASK_UART_RX, /* 0 */
51 IRQ_MASK_UART_TX, /* 1 */
52 IRQ_MASK_TIMER1, /* 2 */
53 IRQ_MASK_TIMER2, /* 3 */
54 IRQ_MASK_TIMER3, /* 4 */
55 IRQ_MASK_IN0, /* 5 */
56 IRQ_MASK_IN1, /* 6 */
57 IRQ_MASK_IN2, /* 7 */
58 IRQ_MASK_IN3, /* 8 */
59 IRQ_MASK_DOORBELLHOST, /* 9 */
60 IRQ_MASK_DMA1, /* 10 */
61 IRQ_MASK_DMA2, /* 11 */
62 IRQ_MASK_PCI, /* 12 */
63 IRQ_MASK_SDRAMPARITY, /* 13 */
64 IRQ_MASK_I2OINPOST, /* 14 */
65 IRQ_MASK_PCI_ABORT, /* 15 */
66 IRQ_MASK_PCI_SERR, /* 16 */
67 IRQ_MASK_DISCARD_TIMER, /* 17 */
68 IRQ_MASK_PCI_DPERR, /* 18 */
69 IRQ_MASK_PCI_PERR, /* 19 */
70 };
71
72 static void fb_mask_irq(unsigned int irq)
73 {
74 *CSR_IRQ_DISABLE = fb_irq_mask[_DC21285_INR(irq)];
75 }
76
77 static void fb_unmask_irq(unsigned int irq)
78 {
79 *CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(irq)];
80 }
81
82 static struct irqchip fb_chip = {
83 .ack = fb_mask_irq,
84 .mask = fb_mask_irq,
85 .unmask = fb_unmask_irq,
86 };
87
88 static void __init __fb_init_irq(void)
89 {
90 unsigned int irq;
91
92 /*
93 * setup DC21285 IRQs
94 */
95 *CSR_IRQ_DISABLE = -1;
96 *CSR_FIQ_DISABLE = -1;
97
98 for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
99 set_irq_chip(irq, &fb_chip);
100 set_irq_handler(irq, do_level_IRQ);
101 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
102 }
103 }
104
105 void __init footbridge_init_irq(void)
106 {
107 __fb_init_irq();
108
109 if (!footbridge_cfn_mode())
110 return;
111
112 if (machine_is_ebsa285())
113 /* The following is dependent on which slot
114 * you plug the Southbridge card into. We
115 * currently assume that you plug it into
116 * the right-hand most slot.
117 */
118 isa_init_irq(IRQ_PCI);
119
120 if (machine_is_cats())
121 isa_init_irq(IRQ_IN2);
122
123 if (machine_is_netwinder())
124 isa_init_irq(IRQ_IN3);
125 }
126
127 /*
128 * Common mapping for all systems. Note that the outbound write flush is
129 * commented out since there is a "No Fix" problem with it. Not mapping
130 * it means that we have extra bullet protection on our feet.
131 */
132 static struct map_desc fb_common_io_desc[] __initdata = {
133 { ARMCSR_BASE, DC21285_ARMCSR_BASE, ARMCSR_SIZE, MT_DEVICE },
134 { XBUS_BASE, 0x40000000, XBUS_SIZE, MT_DEVICE }
135 };
136
137 /*
138 * The mapping when the footbridge is in host mode. We don't map any of
139 * this when we are in add-in mode.
140 */
141 static struct map_desc ebsa285_host_io_desc[] __initdata = {
142 #if defined(CONFIG_ARCH_FOOTBRIDGE) && defined(CONFIG_FOOTBRIDGE_HOST)
143 { PCIMEM_BASE, DC21285_PCI_MEM, PCIMEM_SIZE, MT_DEVICE },
144 { PCICFG0_BASE, DC21285_PCI_TYPE_0_CONFIG, PCICFG0_SIZE, MT_DEVICE },
145 { PCICFG1_BASE, DC21285_PCI_TYPE_1_CONFIG, PCICFG1_SIZE, MT_DEVICE },
146 { PCIIACK_BASE, DC21285_PCI_IACK, PCIIACK_SIZE, MT_DEVICE },
147 { PCIO_BASE, DC21285_PCI_IO, PCIO_SIZE, MT_DEVICE }
148 #endif
149 };
150
151 /*
152 * The CO-ebsa285 mapping.
153 */
154 static struct map_desc co285_io_desc[] __initdata = {
155 #ifdef CONFIG_ARCH_CO285
156 { PCIO_BASE, DC21285_PCI_IO, PCIO_SIZE, MT_DEVICE },
157 { PCIMEM_BASE, DC21285_PCI_MEM, PCIMEM_SIZE, MT_DEVICE }
158 #endif
159 };
160
161 void __init footbridge_map_io(void)
162 {
163 /*
164 * Set up the common mapping first; we need this to
165 * determine whether we're in host mode or not.
166 */
167 iotable_init(fb_common_io_desc, ARRAY_SIZE(fb_common_io_desc));
168
169 /*
170 * Now, work out what we've got to map in addition on this
171 * platform.
172 */
173 if (machine_is_co285())
174 iotable_init(co285_io_desc, ARRAY_SIZE(co285_io_desc));
175 if (footbridge_cfn_mode())
176 iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
177 }
178
179 #ifdef CONFIG_FOOTBRIDGE_ADDIN
180
181 /*
182 * These two functions convert virtual addresses to PCI addresses and PCI
183 * addresses to virtual addresses. Note that it is only legal to use these
184 * on memory obtained via get_zeroed_page or kmalloc.
185 */
186 unsigned long __virt_to_bus(unsigned long res)
187 {
188 WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
189
190 return (res - PAGE_OFFSET) + (*CSR_PCISDRAMBASE & 0xfffffff0);
191 }
192 EXPORT_SYMBOL(__virt_to_bus);
193
194 unsigned long __bus_to_virt(unsigned long res)
195 {
196 res -= (*CSR_PCISDRAMBASE & 0xfffffff0);
197 res += PAGE_OFFSET;
198
199 WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
200
201 return res;
202 }
203 EXPORT_SYMBOL(__bus_to_virt);
204
205 #endif