arch/arm/mach-exynos4/mach-smdkc210.c

   1 /* linux/arch/arm/mach-exynos4/mach-smdkc210.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/serial_core.h>
  12 #include <linux/delay.h>
  13 #include <linux/gpio.h>
  14 #include <linux/lcd.h>
  15 #include <linux/mmc/host.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/smsc911x.h>
  18 #include <linux/io.h>
  19 #include <linux/i2c.h>
  20
  21 #include <asm/mach/arch.h>
  22 #include <asm/mach-types.h>
  23
  24 #include <video/platform_lcd.h>
  25
  26 #include <plat/regs-serial.h>
  27 #include <plat/regs-srom.h>
  28 #include <plat/regs-fb-v4.h>
  29 #include <plat/exynos4.h>
  30 #include <plat/cpu.h>
  31 #include <plat/devs.h>
  32 #include <plat/fb.h>
  33 #include <plat/sdhci.h>
  34 #include <plat/iic.h>
  35 #include <plat/pd.h>
  36
  37 #include <mach/map.h>
  38
  39 /* Following are default values for UCON, ULCON and UFCON UART registers */
  40 #define SMDKC210_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
  41                                  S3C2410_UCON_RXILEVEL |        \
  42                                  S3C2410_UCON_TXIRQMODE |       \
  43                                  S3C2410_UCON_RXIRQMODE |       \
  44                                  S3C2410_UCON_RXFIFO_TOI |      \
  45                                  S3C2443_UCON_RXERR_IRQEN)
  46
  47 #define SMDKC210_ULCON_DEFAULT  S3C2410_LCON_CS8
  48
  49 #define SMDKC210_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
  50                                  S5PV210_UFCON_TXTRIG4 |        \
  51                                  S5PV210_UFCON_RXTRIG4)
  52
  53 static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
  54         [0] = {
  55                 .hwport         = 0,
  56                 .flags          = 0,
  57                 .ucon           = SMDKC210_UCON_DEFAULT,
  58                 .ulcon          = SMDKC210_ULCON_DEFAULT,
  59                 .ufcon          = SMDKC210_UFCON_DEFAULT,
  60         },
  61         [1] = {
  62                 .hwport         = 1,
  63                 .flags          = 0,
  64                 .ucon           = SMDKC210_UCON_DEFAULT,
  65                 .ulcon          = SMDKC210_ULCON_DEFAULT,
  66                 .ufcon          = SMDKC210_UFCON_DEFAULT,
  67         },
  68         [2] = {
  69                 .hwport         = 2,
  70                 .flags          = 0,
  71                 .ucon           = SMDKC210_UCON_DEFAULT,
  72                 .ulcon          = SMDKC210_ULCON_DEFAULT,
  73                 .ufcon          = SMDKC210_UFCON_DEFAULT,
  74         },
  75         [3] = {
  76                 .hwport         = 3,
  77                 .flags          = 0,
  78                 .ucon           = SMDKC210_UCON_DEFAULT,
  79                 .ulcon          = SMDKC210_ULCON_DEFAULT,
  80                 .ufcon          = SMDKC210_UFCON_DEFAULT,
  81         },
  82 };
  83
  84 static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
  85         .cd_type                = S3C_SDHCI_CD_GPIO,
  86         .ext_cd_gpio            = EXYNOS4_GPK0(2),
  87         .ext_cd_gpio_invert     = 1,
  88         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
  89 #ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
  90         .max_width              = 8,
  91         .host_caps              = MMC_CAP_8_BIT_DATA,
  92 #endif
  93 };
  94
  95 static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
  96         .cd_type                = S3C_SDHCI_CD_GPIO,
  97         .ext_cd_gpio            = EXYNOS4_GPK0(2),
  98         .ext_cd_gpio_invert     = 1,
  99         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 100 };
 101
 102 static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
 103         .cd_type                = S3C_SDHCI_CD_GPIO,
 104         .ext_cd_gpio            = EXYNOS4_GPK2(2),
 105         .ext_cd_gpio_invert     = 1,
 106         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 107 #ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
 108         .max_width              = 8,
 109         .host_caps              = MMC_CAP_8_BIT_DATA,
 110 #endif
 111 };
 112
 113 static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
 114         .cd_type                = S3C_SDHCI_CD_GPIO,
 115         .ext_cd_gpio            = EXYNOS4_GPK2(2),
 116         .ext_cd_gpio_invert     = 1,
 117         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 118 };
 119
 120 static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
 121                                    unsigned int power)
 122 {
 123         if (power) {
 124 #if !defined(CONFIG_BACKLIGHT_PWM)
 125                 gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
 126                 gpio_free(EXYNOS4_GPD0(1));
 127 #endif
 128                 /* fire nRESET on power up */
 129                 gpio_request(EXYNOS4_GPX0(6), "GPX0");
 130
 131                 gpio_direction_output(EXYNOS4_GPX0(6), 1);
 132                 mdelay(100);
 133
 134                 gpio_set_value(EXYNOS4_GPX0(6), 0);
 135                 mdelay(10);
 136
 137                 gpio_set_value(EXYNOS4_GPX0(6), 1);
 138                 mdelay(10);
 139
 140                 gpio_free(EXYNOS4_GPX0(6));
 141         } else {
 142 #if !defined(CONFIG_BACKLIGHT_PWM)
 143                 gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
 144                 gpio_free(EXYNOS4_GPD0(1));
 145 #endif
 146         }
 147 }
 148
 149 static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
 150         .set_power              = lcd_lte480wv_set_power,
 151 };
 152
 153 static struct platform_device smdkc210_lcd_lte480wv = {
 154         .name                   = "platform-lcd",
 155         .dev.parent             = &s5p_device_fimd0.dev,
 156         .dev.platform_data      = &smdkc210_lcd_lte480wv_data,
 157 };
 158
 159 static struct s3c_fb_pd_win smdkc210_fb_win0 = {
 160         .win_mode = {
 161                 .left_margin    = 13,
 162                 .right_margin   = 8,
 163                 .upper_margin   = 7,
 164                 .lower_margin   = 5,
 165                 .hsync_len      = 3,
 166                 .vsync_len      = 1,
 167                 .xres           = 800,
 168                 .yres           = 480,
 169         },
 170         .max_bpp                = 32,
 171         .default_bpp            = 24,
 172 };
 173
 174 static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
 175         .win[0]         = &smdkc210_fb_win0,
 176         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 177         .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 178         .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
 179 };
 180
 181 static struct resource smdkc210_smsc911x_resources[] = {
 182         [0] = {
 183                 .start  = EXYNOS4_PA_SROM_BANK(1),
 184                 .end    = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
 185                 .flags  = IORESOURCE_MEM,
 186         },
 187         [1] = {
 188                 .start  = IRQ_EINT(5),
 189                 .end    = IRQ_EINT(5),
 190                 .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
 191         },
 192 };
 193
 194 static struct smsc911x_platform_config smsc9215_config = {
 195         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
 196         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
 197         .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
 198         .phy_interface  = PHY_INTERFACE_MODE_MII,
 199         .mac            = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
 200 };
 201
 202 static struct platform_device smdkc210_smsc911x = {
 203         .name           = "smsc911x",
 204         .id             = -1,
 205         .num_resources  = ARRAY_SIZE(smdkc210_smsc911x_resources),
 206         .resource       = smdkc210_smsc911x_resources,
 207         .dev            = {
 208                 .platform_data  = &smsc9215_config,
 209         },
 210 };
 211
 212 static struct i2c_board_info i2c_devs1[] __initdata = {
 213         {I2C_BOARD_INFO("wm8994", 0x1a),},
 214 };
 215
 216 static struct platform_device *smdkc210_devices[] __initdata = {
 217         &s3c_device_hsmmc0,
 218         &s3c_device_hsmmc1,
 219         &s3c_device_hsmmc2,
 220         &s3c_device_hsmmc3,
 221         &s3c_device_i2c1,
 222         &s3c_device_rtc,
 223         &s3c_device_wdt,
 224         &exynos4_device_ac97,
 225         &exynos4_device_i2s0,
 226         &exynos4_device_pd[PD_MFC],
 227         &exynos4_device_pd[PD_G3D],
 228         &exynos4_device_pd[PD_LCD0],
 229         &exynos4_device_pd[PD_LCD1],
 230         &exynos4_device_pd[PD_CAM],
 231         &exynos4_device_pd[PD_TV],
 232         &exynos4_device_pd[PD_GPS],
 233         &exynos4_device_sysmmu,
 234         &samsung_asoc_dma,
 235         &s5p_device_fimd0,
 236         &smdkc210_lcd_lte480wv,
 237         &smdkc210_smsc911x,
 238 };
 239
 240 static void __init smdkc210_smsc911x_init(void)
 241 {
 242         u32 cs1;
 243
 244         /* configure nCS1 width to 16 bits */
 245         cs1 = __raw_readl(S5P_SROM_BW) &
 246                 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
 247         cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
 248                 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
 249                 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
 250                 S5P_SROM_BW__NCS1__SHIFT;
 251         __raw_writel(cs1, S5P_SROM_BW);
 252
 253         /* set timing for nCS1 suitable for ethernet chip */
 254         __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
 255                      (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
 256                      (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
 257                      (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
 258                      (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
 259                      (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
 260                      (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
 261 }
 262
 263 static void __init smdkc210_map_io(void)
 264 {
 265         s5p_init_io(NULL, 0, S5P_VA_CHIPID);
 266         s3c24xx_init_clocks(24000000);
 267         s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs));
 268 }
 269
 270 static void __init smdkc210_machine_init(void)
 271 {
 272         s3c_i2c1_set_platdata(NULL);
 273         i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
 274
 275         smdkc210_smsc911x_init();
 276
 277         s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
 278         s3c_sdhci1_set_platdata(&smdkc210_hsmmc1_pdata);
 279         s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
 280         s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
 281
 282         s5p_fimd0_set_platdata(&smdkc210_lcd0_pdata);
 283
 284         platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
 285 }
 286
 287 MACHINE_START(SMDKC210, "SMDKC210")
 288         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
 289         .boot_params    = S5P_PA_SDRAM + 0x100,
 290         .init_irq       = exynos4_init_irq,
 291         .map_io         = smdkc210_map_io,
 292         .init_machine   = smdkc210_machine_init,
 293         .timer          = &exynos4_timer,
 294 MACHINE_END