1 /* linux/arch/arm/mach-exynos4/mct.c
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * EXYNOS4 MCT(Multi-Core Timer) support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/sched.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/clockchips.h>
19 #include <linux/platform_device.h>
20 #include <linux/delay.h>
21 #include <linux/percpu.h>
24 #include <asm/localtimer.h>
29 #include <mach/irqs.h>
30 #include <mach/regs-mct.h>
31 #include <asm/mach/time.h>
33 #define TICK_BASE_CNT 1
40 static unsigned long clk_rate
;
41 static unsigned int mct_int_type
;
43 struct mct_clock_event_device
{
44 struct clock_event_device
*evt
;
49 static void exynos4_mct_write(unsigned int value
, void *addr
)
51 void __iomem
*stat_addr
;
55 __raw_writel(value
, addr
);
57 if (likely(addr
>= EXYNOS4_MCT_L_BASE(0))) {
58 u32 base
= (u32
) addr
& EXYNOS4_MCT_L_MASK
;
59 switch ((u32
) addr
& ~EXYNOS4_MCT_L_MASK
) {
60 case (u32
) MCT_L_TCON_OFFSET
:
61 stat_addr
= (void __iomem
*) base
+ MCT_L_WSTAT_OFFSET
;
62 mask
= 1 << 3; /* L_TCON write status */
64 case (u32
) MCT_L_ICNTB_OFFSET
:
65 stat_addr
= (void __iomem
*) base
+ MCT_L_WSTAT_OFFSET
;
66 mask
= 1 << 1; /* L_ICNTB write status */
68 case (u32
) MCT_L_TCNTB_OFFSET
:
69 stat_addr
= (void __iomem
*) base
+ MCT_L_WSTAT_OFFSET
;
70 mask
= 1 << 0; /* L_TCNTB write status */
77 case (u32
) EXYNOS4_MCT_G_TCON
:
78 stat_addr
= EXYNOS4_MCT_G_WSTAT
;
79 mask
= 1 << 16; /* G_TCON write status */
81 case (u32
) EXYNOS4_MCT_G_COMP0_L
:
82 stat_addr
= EXYNOS4_MCT_G_WSTAT
;
83 mask
= 1 << 0; /* G_COMP0_L write status */
85 case (u32
) EXYNOS4_MCT_G_COMP0_U
:
86 stat_addr
= EXYNOS4_MCT_G_WSTAT
;
87 mask
= 1 << 1; /* G_COMP0_U write status */
89 case (u32
) EXYNOS4_MCT_G_COMP0_ADD_INCR
:
90 stat_addr
= EXYNOS4_MCT_G_WSTAT
;
91 mask
= 1 << 2; /* G_COMP0_ADD_INCR w status */
93 case (u32
) EXYNOS4_MCT_G_CNT_L
:
94 stat_addr
= EXYNOS4_MCT_G_CNT_WSTAT
;
95 mask
= 1 << 0; /* G_CNT_L write status */
97 case (u32
) EXYNOS4_MCT_G_CNT_U
:
98 stat_addr
= EXYNOS4_MCT_G_CNT_WSTAT
;
99 mask
= 1 << 1; /* G_CNT_U write status */
106 /* Wait maximum 1 ms until written values are applied */
107 for (i
= 0; i
< loops_per_jiffy
/ 1000 * HZ
; i
++)
108 if (__raw_readl(stat_addr
) & mask
) {
109 __raw_writel(mask
, stat_addr
);
113 panic("MCT hangs after writing %d (addr:0x%08x)\n", value
, (u32
)addr
);
116 /* Clocksource handling */
117 static void exynos4_mct_frc_start(u32 hi
, u32 lo
)
121 exynos4_mct_write(lo
, EXYNOS4_MCT_G_CNT_L
);
122 exynos4_mct_write(hi
, EXYNOS4_MCT_G_CNT_U
);
124 reg
= __raw_readl(EXYNOS4_MCT_G_TCON
);
125 reg
|= MCT_G_TCON_START
;
126 exynos4_mct_write(reg
, EXYNOS4_MCT_G_TCON
);
129 static cycle_t
exynos4_frc_read(struct clocksource
*cs
)
132 u32 hi2
= __raw_readl(EXYNOS4_MCT_G_CNT_U
);
136 lo
= __raw_readl(EXYNOS4_MCT_G_CNT_L
);
137 hi2
= __raw_readl(EXYNOS4_MCT_G_CNT_U
);
140 return ((cycle_t
)hi
<< 32) | lo
;
143 static void exynos4_frc_resume(struct clocksource
*cs
)
145 exynos4_mct_frc_start(0, 0);
148 struct clocksource mct_frc
= {
151 .read
= exynos4_frc_read
,
152 .mask
= CLOCKSOURCE_MASK(64),
153 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
154 .resume
= exynos4_frc_resume
,
157 static void __init
exynos4_clocksource_init(void)
159 exynos4_mct_frc_start(0, 0);
161 if (clocksource_register_hz(&mct_frc
, clk_rate
))
162 panic("%s: can't register clocksource\n", mct_frc
.name
);
165 static void exynos4_mct_comp0_stop(void)
169 tcon
= __raw_readl(EXYNOS4_MCT_G_TCON
);
170 tcon
&= ~(MCT_G_TCON_COMP0_ENABLE
| MCT_G_TCON_COMP0_AUTO_INC
);
172 exynos4_mct_write(tcon
, EXYNOS4_MCT_G_TCON
);
173 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB
);
176 static void exynos4_mct_comp0_start(enum clock_event_mode mode
,
177 unsigned long cycles
)
182 tcon
= __raw_readl(EXYNOS4_MCT_G_TCON
);
184 if (mode
== CLOCK_EVT_MODE_PERIODIC
) {
185 tcon
|= MCT_G_TCON_COMP0_AUTO_INC
;
186 exynos4_mct_write(cycles
, EXYNOS4_MCT_G_COMP0_ADD_INCR
);
189 comp_cycle
= exynos4_frc_read(&mct_frc
) + cycles
;
190 exynos4_mct_write((u32
)comp_cycle
, EXYNOS4_MCT_G_COMP0_L
);
191 exynos4_mct_write((u32
)(comp_cycle
>> 32), EXYNOS4_MCT_G_COMP0_U
);
193 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB
);
195 tcon
|= MCT_G_TCON_COMP0_ENABLE
;
196 exynos4_mct_write(tcon
, EXYNOS4_MCT_G_TCON
);
199 static int exynos4_comp_set_next_event(unsigned long cycles
,
200 struct clock_event_device
*evt
)
202 exynos4_mct_comp0_start(evt
->mode
, cycles
);
207 static void exynos4_comp_set_mode(enum clock_event_mode mode
,
208 struct clock_event_device
*evt
)
210 unsigned long cycles_per_jiffy
;
211 exynos4_mct_comp0_stop();
214 case CLOCK_EVT_MODE_PERIODIC
:
216 (((unsigned long long) NSEC_PER_SEC
/ HZ
* evt
->mult
) >> evt
->shift
);
217 exynos4_mct_comp0_start(mode
, cycles_per_jiffy
);
220 case CLOCK_EVT_MODE_ONESHOT
:
221 case CLOCK_EVT_MODE_UNUSED
:
222 case CLOCK_EVT_MODE_SHUTDOWN
:
223 case CLOCK_EVT_MODE_RESUME
:
228 static struct clock_event_device mct_comp_device
= {
230 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
232 .set_next_event
= exynos4_comp_set_next_event
,
233 .set_mode
= exynos4_comp_set_mode
,
236 static irqreturn_t
exynos4_mct_comp_isr(int irq
, void *dev_id
)
238 struct clock_event_device
*evt
= dev_id
;
240 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT
);
242 evt
->event_handler(evt
);
247 static struct irqaction mct_comp_event_irq
= {
248 .name
= "mct_comp_irq",
249 .flags
= IRQF_TIMER
| IRQF_IRQPOLL
,
250 .handler
= exynos4_mct_comp_isr
,
251 .dev_id
= &mct_comp_device
,
254 static void exynos4_clockevent_init(void)
256 mct_comp_device
.cpumask
= cpumask_of(0);
257 clockevents_config_and_register(&mct_comp_device
, clk_rate
,
260 if (soc_is_exynos5250())
261 setup_irq(EXYNOS5_IRQ_MCT_G0
, &mct_comp_event_irq
);
263 setup_irq(EXYNOS4_IRQ_MCT_G0
, &mct_comp_event_irq
);
266 #ifdef CONFIG_LOCAL_TIMERS
268 static DEFINE_PER_CPU(struct mct_clock_event_device
, percpu_mct_tick
);
270 /* Clock event handling */
271 static void exynos4_mct_tick_stop(struct mct_clock_event_device
*mevt
)
274 unsigned long mask
= MCT_L_TCON_INT_START
| MCT_L_TCON_TIMER_START
;
275 void __iomem
*addr
= mevt
->base
+ MCT_L_TCON_OFFSET
;
277 tmp
= __raw_readl(addr
);
280 exynos4_mct_write(tmp
, addr
);
284 static void exynos4_mct_tick_start(unsigned long cycles
,
285 struct mct_clock_event_device
*mevt
)
289 exynos4_mct_tick_stop(mevt
);
291 tmp
= (1 << 31) | cycles
; /* MCT_L_UPDATE_ICNTB */
293 /* update interrupt count buffer */
294 exynos4_mct_write(tmp
, mevt
->base
+ MCT_L_ICNTB_OFFSET
);
296 /* enable MCT tick interrupt */
297 exynos4_mct_write(0x1, mevt
->base
+ MCT_L_INT_ENB_OFFSET
);
299 tmp
= __raw_readl(mevt
->base
+ MCT_L_TCON_OFFSET
);
300 tmp
|= MCT_L_TCON_INT_START
| MCT_L_TCON_TIMER_START
|
301 MCT_L_TCON_INTERVAL_MODE
;
302 exynos4_mct_write(tmp
, mevt
->base
+ MCT_L_TCON_OFFSET
);
305 static int exynos4_tick_set_next_event(unsigned long cycles
,
306 struct clock_event_device
*evt
)
308 struct mct_clock_event_device
*mevt
= this_cpu_ptr(&percpu_mct_tick
);
310 exynos4_mct_tick_start(cycles
, mevt
);
315 static inline void exynos4_tick_set_mode(enum clock_event_mode mode
,
316 struct clock_event_device
*evt
)
318 struct mct_clock_event_device
*mevt
= this_cpu_ptr(&percpu_mct_tick
);
319 unsigned long cycles_per_jiffy
;
321 exynos4_mct_tick_stop(mevt
);
324 case CLOCK_EVT_MODE_PERIODIC
:
326 (((unsigned long long) NSEC_PER_SEC
/ HZ
* evt
->mult
) >> evt
->shift
);
327 exynos4_mct_tick_start(cycles_per_jiffy
, mevt
);
330 case CLOCK_EVT_MODE_ONESHOT
:
331 case CLOCK_EVT_MODE_UNUSED
:
332 case CLOCK_EVT_MODE_SHUTDOWN
:
333 case CLOCK_EVT_MODE_RESUME
:
338 static int exynos4_mct_tick_clear(struct mct_clock_event_device
*mevt
)
340 struct clock_event_device
*evt
= mevt
->evt
;
343 * This is for supporting oneshot mode.
344 * Mct would generate interrupt periodically
345 * without explicit stopping.
347 if (evt
->mode
!= CLOCK_EVT_MODE_PERIODIC
)
348 exynos4_mct_tick_stop(mevt
);
350 /* Clear the MCT tick interrupt */
351 if (__raw_readl(mevt
->base
+ MCT_L_INT_CSTAT_OFFSET
) & 1) {
352 exynos4_mct_write(0x1, mevt
->base
+ MCT_L_INT_CSTAT_OFFSET
);
359 static irqreturn_t
exynos4_mct_tick_isr(int irq
, void *dev_id
)
361 struct mct_clock_event_device
*mevt
= dev_id
;
362 struct clock_event_device
*evt
= mevt
->evt
;
364 exynos4_mct_tick_clear(mevt
);
366 evt
->event_handler(evt
);
371 static struct irqaction mct_tick0_event_irq
= {
372 .name
= "mct_tick0_irq",
373 .flags
= IRQF_TIMER
| IRQF_NOBALANCING
,
374 .handler
= exynos4_mct_tick_isr
,
377 static struct irqaction mct_tick1_event_irq
= {
378 .name
= "mct_tick1_irq",
379 .flags
= IRQF_TIMER
| IRQF_NOBALANCING
,
380 .handler
= exynos4_mct_tick_isr
,
383 static int __cpuinit
exynos4_local_timer_setup(struct clock_event_device
*evt
)
385 struct mct_clock_event_device
*mevt
;
386 unsigned int cpu
= smp_processor_id();
389 mevt
= this_cpu_ptr(&percpu_mct_tick
);
392 mevt
->base
= EXYNOS4_MCT_L_BASE(cpu
);
393 sprintf(mevt
->name
, "mct_tick%d", cpu
);
395 evt
->name
= mevt
->name
;
396 evt
->cpumask
= cpumask_of(cpu
);
397 evt
->set_next_event
= exynos4_tick_set_next_event
;
398 evt
->set_mode
= exynos4_tick_set_mode
;
399 evt
->features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
;
401 clockevents_config_and_register(evt
, clk_rate
/ (TICK_BASE_CNT
+ 1),
404 exynos4_mct_write(TICK_BASE_CNT
, mevt
->base
+ MCT_L_TCNTB_OFFSET
);
406 if (mct_int_type
== MCT_INT_SPI
) {
408 mct_lx_irq
= soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0
:
410 mct_tick0_event_irq
.dev_id
= mevt
;
411 evt
->irq
= mct_lx_irq
;
412 setup_irq(mct_lx_irq
, &mct_tick0_event_irq
);
414 mct_lx_irq
= soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1
:
416 mct_tick1_event_irq
.dev_id
= mevt
;
417 evt
->irq
= mct_lx_irq
;
418 setup_irq(mct_lx_irq
, &mct_tick1_event_irq
);
419 irq_set_affinity(mct_lx_irq
, cpumask_of(1));
422 enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER
, 0);
428 static void exynos4_local_timer_stop(struct clock_event_device
*evt
)
430 unsigned int cpu
= smp_processor_id();
431 evt
->set_mode(CLOCK_EVT_MODE_UNUSED
, evt
);
432 if (mct_int_type
== MCT_INT_SPI
)
434 remove_irq(evt
->irq
, &mct_tick0_event_irq
);
436 remove_irq(evt
->irq
, &mct_tick1_event_irq
);
438 disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER
);
441 static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata
= {
442 .setup
= exynos4_local_timer_setup
,
443 .stop
= exynos4_local_timer_stop
,
445 #endif /* CONFIG_LOCAL_TIMERS */
447 static void __init
exynos4_timer_resources(void)
450 mct_clk
= clk_get(NULL
, "xtal");
452 clk_rate
= clk_get_rate(mct_clk
);
454 #ifdef CONFIG_LOCAL_TIMERS
455 if (mct_int_type
== MCT_INT_PPI
) {
458 err
= request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER
,
459 exynos4_mct_tick_isr
, "MCT",
461 WARN(err
, "MCT: can't request IRQ %d (%d)\n",
462 EXYNOS_IRQ_MCT_LOCALTIMER
, err
);
465 local_timer_register(&exynos4_mct_tick_ops
);
466 #endif /* CONFIG_LOCAL_TIMERS */
469 void __init
exynos4_timer_init(void)
471 if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
472 mct_int_type
= MCT_INT_SPI
;
474 mct_int_type
= MCT_INT_PPI
;
476 exynos4_timer_resources();
477 exynos4_clocksource_init();
478 exynos4_clockevent_init();