arch/arm/mach-exynos/clock-exynos4212.c

   1 /*
   2  * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS4212 - Clock support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/err.h>
  14 #include <linux/clk.h>
  15 #include <linux/io.h>
  16 #include <linux/syscore_ops.h>
  17
  18 #include <plat/cpu-freq.h>
  19 #include <plat/clock.h>
  20 #include <plat/cpu.h>
  21 #include <plat/pll.h>
  22 #include <plat/s5p-clock.h>
  23 #include <plat/clock-clksrc.h>
  24 #include <plat/pm.h>
  25
  26 #include <mach/hardware.h>
  27 #include <mach/map.h>
  28 #include <mach/regs-clock.h>
  29
  30 #include "common.h"
  31 #include "clock-exynos4.h"
  32
  33 #ifdef CONFIG_PM_SLEEP
  34 static struct sleep_save exynos4212_clock_save[] = {
  35         SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
  36         SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
  37         SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
  38         SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
  39 };
  40 #endif
  41
  42 static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
  43 {
  44         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
  45 }
  46
  47 static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
  48 {
  49         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
  50 }
  51
  52 static struct clk *clk_src_mpll_user_list[] = {
  53         [0] = &clk_fin_mpll,
  54         [1] = &exynos4_clk_mout_mpll.clk,
  55 };
  56
  57 static struct clksrc_sources clk_src_mpll_user = {
  58         .sources        = clk_src_mpll_user_list,
  59         .nr_sources     = ARRAY_SIZE(clk_src_mpll_user_list),
  60 };
  61
  62 static struct clksrc_clk clk_mout_mpll_user = {
  63         .clk = {
  64                 .name           = "mout_mpll_user",
  65         },
  66         .sources        = &clk_src_mpll_user,
  67         .reg_src        = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
  68 };
  69
  70 static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
  71         .clk    = {
  72                 .name           = "mout_g2d0",
  73         },
  74         .sources = &exynos4_clkset_mout_g2d0,
  75         .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
  76 };
  77
  78 static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
  79         .clk    = {
  80                 .name           = "mout_g2d1",
  81         },
  82         .sources = &exynos4_clkset_mout_g2d1,
  83         .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
  84 };
  85
  86 static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
  87         [0] = &exynos4x12_clk_mout_g2d0.clk,
  88         [1] = &exynos4x12_clk_mout_g2d1.clk,
  89 };
  90
  91 static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
  92         .sources        = exynos4x12_clkset_mout_g2d_list,
  93         .nr_sources     = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
  94 };
  95
  96 static struct clksrc_clk *sysclks[] = {
  97         &clk_mout_mpll_user,
  98 };
  99
 100 static struct clksrc_clk clksrcs[] = {
 101         {
 102                 .clk    = {
 103                         .name           = "sclk_fimg2d",
 104                 },
 105                 .sources = &exynos4x12_clkset_mout_g2d,
 106                 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
 107                 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
 108         },
 109 };
 110
 111 static struct clk init_clocks_off[] = {
 112         {
 113                 .name           = "sysmmu",
 114                 .devname        = "exynos-sysmmu.9",
 115                 .enable         = exynos4_clk_ip_dmc_ctrl,
 116                 .ctrlbit        = (1 << 24),
 117         }, {
 118                 .name           = "sysmmu",
 119                 .devname        = "exynos-sysmmu.12",
 120                 .enable         = exynos4212_clk_ip_isp0_ctrl,
 121                 .ctrlbit        = (7 << 8),
 122         }, {
 123                 .name           = "sysmmu",
 124                 .devname        = "exynos-sysmmu.13",
 125                 .enable         = exynos4212_clk_ip_isp1_ctrl,
 126                 .ctrlbit        = (1 << 4),
 127         }, {
 128                 .name           = "sysmmu",
 129                 .devname        = "exynos-sysmmu.14",
 130                 .enable         = exynos4212_clk_ip_isp0_ctrl,
 131                 .ctrlbit        = (1 << 11),
 132         }, {
 133                 .name           = "sysmmu",
 134                 .devname        = "exynos-sysmmu.15",
 135                 .enable         = exynos4212_clk_ip_isp0_ctrl,
 136                 .ctrlbit        = (1 << 12),
 137         }, {
 138                 .name           = "flite",
 139                 .devname        = "exynos-fimc-lite.0",
 140                 .enable         = exynos4212_clk_ip_isp0_ctrl,
 141                 .ctrlbit        = (1 << 4),
 142         }, {
 143                 .name           = "flite",
 144                 .devname        = "exynos-fimc-lite.1",
 145                 .enable         = exynos4212_clk_ip_isp0_ctrl,
 146                 .ctrlbit        = (1 << 3),
 147         }, {
 148                 .name           = "fimg2d",
 149                 .enable         = exynos4_clk_ip_dmc_ctrl,
 150                 .ctrlbit        = (1 << 23),
 151         },
 152 };
 153
 154 #ifdef CONFIG_PM_SLEEP
 155 static int exynos4212_clock_suspend(void)
 156 {
 157         s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
 158
 159         return 0;
 160 }
 161
 162 static void exynos4212_clock_resume(void)
 163 {
 164         s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
 165 }
 166
 167 #else
 168 #define exynos4212_clock_suspend NULL
 169 #define exynos4212_clock_resume NULL
 170 #endif
 171
 172 static struct syscore_ops exynos4212_clock_syscore_ops = {
 173         .suspend        = exynos4212_clock_suspend,
 174         .resume         = exynos4212_clock_resume,
 175 };
 176
 177 void __init exynos4212_register_clocks(void)
 178 {
 179         int ptr;
 180
 181         /* usbphy1 is removed */
 182         exynos4_clkset_group_list[4] = NULL;
 183
 184         /* mout_mpll_user is used */
 185         exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
 186         exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
 187
 188         exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
 189         exynos4_clk_mout_mpll.reg_src.shift = 12;
 190         exynos4_clk_mout_mpll.reg_src.size = 1;
 191
 192         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 193                 s3c_register_clksrc(sysclks[ptr], 1);
 194
 195         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 196
 197         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 198         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 199
 200         register_syscore_ops(&exynos4212_clock_syscore_ops);
 201 }