2 * EDMA3 support for DaVinci
4 * Copyright (C) 2006-2009 Texas Instruments.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/interrupt.h>
24 #include <linux/platform_device.h>
26 #include <linux/slab.h>
28 #include <mach/edma.h>
30 /* Offsets matching "struct edmacc_param" */
33 #define PARM_A_B_CNT 0x08
35 #define PARM_SRC_DST_BIDX 0x10
36 #define PARM_LINK_BCNTRLD 0x14
37 #define PARM_SRC_DST_CIDX 0x18
38 #define PARM_CCNT 0x1c
40 #define PARM_SIZE 0x20
42 /* Offsets for EDMA CC global channel registers and their shadows */
43 #define SH_ER 0x00 /* 64 bits */
44 #define SH_ECR 0x08 /* 64 bits */
45 #define SH_ESR 0x10 /* 64 bits */
46 #define SH_CER 0x18 /* 64 bits */
47 #define SH_EER 0x20 /* 64 bits */
48 #define SH_EECR 0x28 /* 64 bits */
49 #define SH_EESR 0x30 /* 64 bits */
50 #define SH_SER 0x38 /* 64 bits */
51 #define SH_SECR 0x40 /* 64 bits */
52 #define SH_IER 0x50 /* 64 bits */
53 #define SH_IECR 0x58 /* 64 bits */
54 #define SH_IESR 0x60 /* 64 bits */
55 #define SH_IPR 0x68 /* 64 bits */
56 #define SH_ICR 0x70 /* 64 bits */
66 /* Offsets for EDMA CC global registers */
67 #define EDMA_REV 0x0000
68 #define EDMA_CCCFG 0x0004
69 #define EDMA_QCHMAP 0x0200 /* 8 registers */
70 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
71 #define EDMA_QDMAQNUM 0x0260
72 #define EDMA_QUETCMAP 0x0280
73 #define EDMA_QUEPRI 0x0284
74 #define EDMA_EMR 0x0300 /* 64 bits */
75 #define EDMA_EMCR 0x0308 /* 64 bits */
76 #define EDMA_QEMR 0x0310
77 #define EDMA_QEMCR 0x0314
78 #define EDMA_CCERR 0x0318
79 #define EDMA_CCERRCLR 0x031c
80 #define EDMA_EEVAL 0x0320
81 #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
82 #define EDMA_QRAE 0x0380 /* 4 registers */
83 #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
84 #define EDMA_QSTAT 0x0600 /* 2 registers */
85 #define EDMA_QWMTHRA 0x0620
86 #define EDMA_QWMTHRB 0x0624
87 #define EDMA_CCSTAT 0x0640
89 #define EDMA_M 0x1000 /* global channel registers */
90 #define EDMA_ECR 0x1008
91 #define EDMA_ECRH 0x100C
92 #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
93 #define EDMA_PARM 0x4000 /* 128 param entries */
95 #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
97 #define EDMA_DCHMAP 0x0100 /* 64 registers */
98 #define CHMAP_EXIST BIT(24)
100 #define EDMA_MAX_DMACH 64
101 #define EDMA_MAX_PARAMENTRY 512
103 /*****************************************************************************/
105 static void __iomem
*edmacc_regs_base
[EDMA_MAX_CC
];
107 static inline unsigned int edma_read(unsigned ctlr
, int offset
)
109 return (unsigned int)__raw_readl(edmacc_regs_base
[ctlr
] + offset
);
112 static inline void edma_write(unsigned ctlr
, int offset
, int val
)
114 __raw_writel(val
, edmacc_regs_base
[ctlr
] + offset
);
116 static inline void edma_modify(unsigned ctlr
, int offset
, unsigned and,
119 unsigned val
= edma_read(ctlr
, offset
);
122 edma_write(ctlr
, offset
, val
);
124 static inline void edma_and(unsigned ctlr
, int offset
, unsigned and)
126 unsigned val
= edma_read(ctlr
, offset
);
128 edma_write(ctlr
, offset
, val
);
130 static inline void edma_or(unsigned ctlr
, int offset
, unsigned or)
132 unsigned val
= edma_read(ctlr
, offset
);
134 edma_write(ctlr
, offset
, val
);
136 static inline unsigned int edma_read_array(unsigned ctlr
, int offset
, int i
)
138 return edma_read(ctlr
, offset
+ (i
<< 2));
140 static inline void edma_write_array(unsigned ctlr
, int offset
, int i
,
143 edma_write(ctlr
, offset
+ (i
<< 2), val
);
145 static inline void edma_modify_array(unsigned ctlr
, int offset
, int i
,
146 unsigned and, unsigned or)
148 edma_modify(ctlr
, offset
+ (i
<< 2), and, or);
150 static inline void edma_or_array(unsigned ctlr
, int offset
, int i
, unsigned or)
152 edma_or(ctlr
, offset
+ (i
<< 2), or);
154 static inline void edma_or_array2(unsigned ctlr
, int offset
, int i
, int j
,
157 edma_or(ctlr
, offset
+ ((i
*2 + j
) << 2), or);
159 static inline void edma_write_array2(unsigned ctlr
, int offset
, int i
, int j
,
162 edma_write(ctlr
, offset
+ ((i
*2 + j
) << 2), val
);
164 static inline unsigned int edma_shadow0_read(unsigned ctlr
, int offset
)
166 return edma_read(ctlr
, EDMA_SHADOW0
+ offset
);
168 static inline unsigned int edma_shadow0_read_array(unsigned ctlr
, int offset
,
171 return edma_read(ctlr
, EDMA_SHADOW0
+ offset
+ (i
<< 2));
173 static inline void edma_shadow0_write(unsigned ctlr
, int offset
, unsigned val
)
175 edma_write(ctlr
, EDMA_SHADOW0
+ offset
, val
);
177 static inline void edma_shadow0_write_array(unsigned ctlr
, int offset
, int i
,
180 edma_write(ctlr
, EDMA_SHADOW0
+ offset
+ (i
<< 2), val
);
182 static inline unsigned int edma_parm_read(unsigned ctlr
, int offset
,
185 return edma_read(ctlr
, EDMA_PARM
+ offset
+ (param_no
<< 5));
187 static inline void edma_parm_write(unsigned ctlr
, int offset
, int param_no
,
190 edma_write(ctlr
, EDMA_PARM
+ offset
+ (param_no
<< 5), val
);
192 static inline void edma_parm_modify(unsigned ctlr
, int offset
, int param_no
,
193 unsigned and, unsigned or)
195 edma_modify(ctlr
, EDMA_PARM
+ offset
+ (param_no
<< 5), and, or);
197 static inline void edma_parm_and(unsigned ctlr
, int offset
, int param_no
,
200 edma_and(ctlr
, EDMA_PARM
+ offset
+ (param_no
<< 5), and);
202 static inline void edma_parm_or(unsigned ctlr
, int offset
, int param_no
,
205 edma_or(ctlr
, EDMA_PARM
+ offset
+ (param_no
<< 5), or);
208 static inline void set_bits(int offset
, int len
, unsigned long *p
)
210 for (; len
> 0; len
--)
211 set_bit(offset
+ (len
- 1), p
);
214 static inline void clear_bits(int offset
, int len
, unsigned long *p
)
216 for (; len
> 0; len
--)
217 clear_bit(offset
+ (len
- 1), p
);
220 /*****************************************************************************/
222 /* actual number of DMA channels and slots on this silicon */
224 /* how many dma resources of each type */
225 unsigned num_channels
;
230 enum dma_event_q default_queue
;
232 /* list of channels with no even trigger; terminated by "-1" */
235 /* The edma_inuse bit for each PaRAM slot is clear unless the
236 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
238 DECLARE_BITMAP(edma_inuse
, EDMA_MAX_PARAMENTRY
);
240 /* The edma_unused bit for each channel is clear unless
241 * it is not being used on this platform. It uses a bit
242 * of SOC-specific initialization code.
244 DECLARE_BITMAP(edma_unused
, EDMA_MAX_DMACH
);
246 unsigned irq_res_start
;
247 unsigned irq_res_end
;
249 struct dma_interrupt_data
{
250 void (*callback
)(unsigned channel
, unsigned short ch_status
,
253 } intr_data
[EDMA_MAX_DMACH
];
256 static struct edma
*edma_cc
[EDMA_MAX_CC
];
257 static int arch_num_cc
;
259 /* dummy param set used to (re)initialize parameter RAM slots */
260 static const struct edmacc_param dummy_paramset
= {
261 .link_bcntrld
= 0xffff,
265 /*****************************************************************************/
267 static void map_dmach_queue(unsigned ctlr
, unsigned ch_no
,
268 enum dma_event_q queue_no
)
270 int bit
= (ch_no
& 0x7) * 4;
272 /* default to low priority queue */
273 if (queue_no
== EVENTQ_DEFAULT
)
274 queue_no
= edma_cc
[ctlr
]->default_queue
;
277 edma_modify_array(ctlr
, EDMA_DMAQNUM
, (ch_no
>> 3),
278 ~(0x7 << bit
), queue_no
<< bit
);
281 static void __init
map_queue_tc(unsigned ctlr
, int queue_no
, int tc_no
)
283 int bit
= queue_no
* 4;
284 edma_modify(ctlr
, EDMA_QUETCMAP
, ~(0x7 << bit
), ((tc_no
& 0x7) << bit
));
287 static void __init
assign_priority_to_queue(unsigned ctlr
, int queue_no
,
290 int bit
= queue_no
* 4;
291 edma_modify(ctlr
, EDMA_QUEPRI
, ~(0x7 << bit
),
292 ((priority
& 0x7) << bit
));
296 * map_dmach_param - Maps channel number to param entry number
298 * This maps the dma channel number to param entry numberter. In
299 * other words using the DMA channel mapping registers a param entry
300 * can be mapped to any channel
302 * Callers are responsible for ensuring the channel mapping logic is
303 * included in that particular EDMA variant (Eg : dm646x)
306 static void __init
map_dmach_param(unsigned ctlr
)
309 for (i
= 0; i
< EDMA_MAX_DMACH
; i
++)
310 edma_write_array(ctlr
, EDMA_DCHMAP
, i
, (i
<< 5));
314 setup_dma_interrupt(unsigned lch
,
315 void (*callback
)(unsigned channel
, u16 ch_status
, void *data
),
320 ctlr
= EDMA_CTLR(lch
);
321 lch
= EDMA_CHAN_SLOT(lch
);
324 edma_shadow0_write_array(ctlr
, SH_IECR
, lch
>> 5,
327 edma_cc
[ctlr
]->intr_data
[lch
].callback
= callback
;
328 edma_cc
[ctlr
]->intr_data
[lch
].data
= data
;
331 edma_shadow0_write_array(ctlr
, SH_ICR
, lch
>> 5,
333 edma_shadow0_write_array(ctlr
, SH_IESR
, lch
>> 5,
338 static int irq2ctlr(int irq
)
340 if (irq
>= edma_cc
[0]->irq_res_start
&& irq
<= edma_cc
[0]->irq_res_end
)
342 else if (irq
>= edma_cc
[1]->irq_res_start
&&
343 irq
<= edma_cc
[1]->irq_res_end
)
349 /******************************************************************************
351 * DMA interrupt handler
353 *****************************************************************************/
354 static irqreturn_t
dma_irq_handler(int irq
, void *data
)
361 ctlr
= irq2ctlr(irq
);
365 dev_dbg(data
, "dma_irq_handler\n");
367 sh_ipr
= edma_shadow0_read_array(ctlr
, SH_IPR
, 0);
369 sh_ipr
= edma_shadow0_read_array(ctlr
, SH_IPR
, 1);
372 sh_ier
= edma_shadow0_read_array(ctlr
, SH_IER
, 1);
375 sh_ier
= edma_shadow0_read_array(ctlr
, SH_IER
, 0);
383 dev_dbg(data
, "IPR%d %08x\n", bank
, sh_ipr
);
385 slot
= __ffs(sh_ipr
);
386 sh_ipr
&= ~(BIT(slot
));
388 if (sh_ier
& BIT(slot
)) {
389 channel
= (bank
<< 5) | slot
;
390 /* Clear the corresponding IPR bits */
391 edma_shadow0_write_array(ctlr
, SH_ICR
, bank
,
393 if (edma_cc
[ctlr
]->intr_data
[channel
].callback
)
394 edma_cc
[ctlr
]->intr_data
[channel
].callback(
395 channel
, DMA_COMPLETE
,
396 edma_cc
[ctlr
]->intr_data
[channel
].data
);
400 edma_shadow0_write(ctlr
, SH_IEVAL
, 1);
404 /******************************************************************************
406 * DMA error interrupt handler
408 *****************************************************************************/
409 static irqreturn_t
dma_ccerr_handler(int irq
, void *data
)
413 unsigned int cnt
= 0;
415 ctlr
= irq2ctlr(irq
);
419 dev_dbg(data
, "dma_ccerr_handler\n");
421 if ((edma_read_array(ctlr
, EDMA_EMR
, 0) == 0) &&
422 (edma_read_array(ctlr
, EDMA_EMR
, 1) == 0) &&
423 (edma_read(ctlr
, EDMA_QEMR
) == 0) &&
424 (edma_read(ctlr
, EDMA_CCERR
) == 0))
429 if (edma_read_array(ctlr
, EDMA_EMR
, 0))
431 else if (edma_read_array(ctlr
, EDMA_EMR
, 1))
434 dev_dbg(data
, "EMR%d %08x\n", j
,
435 edma_read_array(ctlr
, EDMA_EMR
, j
));
436 for (i
= 0; i
< 32; i
++) {
437 int k
= (j
<< 5) + i
;
438 if (edma_read_array(ctlr
, EDMA_EMR
, j
) &
440 /* Clear the corresponding EMR bits */
441 edma_write_array(ctlr
, EDMA_EMCR
, j
,
444 edma_shadow0_write_array(ctlr
, SH_SECR
,
446 if (edma_cc
[ctlr
]->intr_data
[k
].
448 edma_cc
[ctlr
]->intr_data
[k
].
451 edma_cc
[ctlr
]->intr_data
456 } else if (edma_read(ctlr
, EDMA_QEMR
)) {
457 dev_dbg(data
, "QEMR %02x\n",
458 edma_read(ctlr
, EDMA_QEMR
));
459 for (i
= 0; i
< 8; i
++) {
460 if (edma_read(ctlr
, EDMA_QEMR
) & BIT(i
)) {
461 /* Clear the corresponding IPR bits */
462 edma_write(ctlr
, EDMA_QEMCR
, BIT(i
));
463 edma_shadow0_write(ctlr
, SH_QSECR
,
466 /* NOTE: not reported!! */
469 } else if (edma_read(ctlr
, EDMA_CCERR
)) {
470 dev_dbg(data
, "CCERR %08x\n",
471 edma_read(ctlr
, EDMA_CCERR
));
472 /* FIXME: CCERR.BIT(16) ignored! much better
473 * to just write CCERRCLR with CCERR value...
475 for (i
= 0; i
< 8; i
++) {
476 if (edma_read(ctlr
, EDMA_CCERR
) & BIT(i
)) {
477 /* Clear the corresponding IPR bits */
478 edma_write(ctlr
, EDMA_CCERRCLR
, BIT(i
));
480 /* NOTE: not reported!! */
484 if ((edma_read_array(ctlr
, EDMA_EMR
, 0) == 0) &&
485 (edma_read_array(ctlr
, EDMA_EMR
, 1) == 0) &&
486 (edma_read(ctlr
, EDMA_QEMR
) == 0) &&
487 (edma_read(ctlr
, EDMA_CCERR
) == 0))
493 edma_write(ctlr
, EDMA_EEVAL
, 1);
497 /******************************************************************************
499 * Transfer controller error interrupt handlers
501 *****************************************************************************/
503 #define tc_errs_handled false /* disabled as long as they're NOPs */
505 static irqreturn_t
dma_tc0err_handler(int irq
, void *data
)
507 dev_dbg(data
, "dma_tc0err_handler\n");
511 static irqreturn_t
dma_tc1err_handler(int irq
, void *data
)
513 dev_dbg(data
, "dma_tc1err_handler\n");
517 static int reserve_contiguous_slots(int ctlr
, unsigned int id
,
518 unsigned int num_slots
,
519 unsigned int start_slot
)
522 unsigned int count
= num_slots
;
523 int stop_slot
= start_slot
;
524 DECLARE_BITMAP(tmp_inuse
, EDMA_MAX_PARAMENTRY
);
526 for (i
= start_slot
; i
< edma_cc
[ctlr
]->num_slots
; ++i
) {
527 j
= EDMA_CHAN_SLOT(i
);
528 if (!test_and_set_bit(j
, edma_cc
[ctlr
]->edma_inuse
)) {
529 /* Record our current beginning slot */
530 if (count
== num_slots
)
534 set_bit(j
, tmp_inuse
);
539 clear_bit(j
, tmp_inuse
);
541 if (id
== EDMA_CONT_PARAMS_FIXED_EXACT
) {
551 * We have to clear any bits that we set
552 * if we run out parameter RAM slots, i.e we do find a set
553 * of contiguous parameter RAM slots but do not find the exact number
554 * requested as we may reach the total number of parameter RAM slots
556 if (i
== edma_cc
[ctlr
]->num_slots
)
560 for_each_set_bit_from(j
, tmp_inuse
, stop_slot
)
561 clear_bit(j
, edma_cc
[ctlr
]->edma_inuse
);
566 for (j
= i
- num_slots
+ 1; j
<= i
; ++j
)
567 memcpy_toio(edmacc_regs_base
[ctlr
] + PARM_OFFSET(j
),
568 &dummy_paramset
, PARM_SIZE
);
570 return EDMA_CTLR_CHAN(ctlr
, i
- num_slots
+ 1);
573 static int prepare_unused_channel_list(struct device
*dev
, void *data
)
575 struct platform_device
*pdev
= to_platform_device(dev
);
578 for (i
= 0; i
< pdev
->num_resources
; i
++) {
579 if ((pdev
->resource
[i
].flags
& IORESOURCE_DMA
) &&
580 (int)pdev
->resource
[i
].start
>= 0) {
581 ctlr
= EDMA_CTLR(pdev
->resource
[i
].start
);
582 clear_bit(EDMA_CHAN_SLOT(pdev
->resource
[i
].start
),
583 edma_cc
[ctlr
]->edma_unused
);
590 /*-----------------------------------------------------------------------*/
592 static bool unused_chan_list_done
;
594 /* Resource alloc/free: dma channels, parameter RAM slots */
597 * edma_alloc_channel - allocate DMA channel and paired parameter RAM
598 * @channel: specific channel to allocate; negative for "any unmapped channel"
599 * @callback: optional; to be issued on DMA completion or errors
600 * @data: passed to callback
601 * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
602 * Controller (TC) executes requests using this channel. Use
603 * EVENTQ_DEFAULT unless you really need a high priority queue.
605 * This allocates a DMA channel and its associated parameter RAM slot.
606 * The parameter RAM is initialized to hold a dummy transfer.
608 * Normal use is to pass a specific channel number as @channel, to make
609 * use of hardware events mapped to that channel. When the channel will
610 * be used only for software triggering or event chaining, channels not
611 * mapped to hardware events (or mapped to unused events) are preferable.
613 * DMA transfers start from a channel using edma_start(), or by
614 * chaining. When the transfer described in that channel's parameter RAM
615 * slot completes, that slot's data may be reloaded through a link.
617 * DMA errors are only reported to the @callback associated with the
618 * channel driving that transfer, but transfer completion callbacks can
619 * be sent to another channel under control of the TCC field in
620 * the option word of the transfer's parameter RAM set. Drivers must not
621 * use DMA transfer completion callbacks for channels they did not allocate.
622 * (The same applies to TCC codes used in transfer chaining.)
624 * Returns the number of the channel, else negative errno.
626 int edma_alloc_channel(int channel
,
627 void (*callback
)(unsigned channel
, u16 ch_status
, void *data
),
629 enum dma_event_q eventq_no
)
631 unsigned i
, done
= 0, ctlr
= 0;
634 if (!unused_chan_list_done
) {
636 * Scan all the platform devices to find out the EDMA channels
637 * used and clear them in the unused list, making the rest
638 * available for ARM usage.
640 ret
= bus_for_each_dev(&platform_bus_type
, NULL
, NULL
,
641 prepare_unused_channel_list
);
645 unused_chan_list_done
= true;
649 ctlr
= EDMA_CTLR(channel
);
650 channel
= EDMA_CHAN_SLOT(channel
);
654 for (i
= 0; i
< arch_num_cc
; i
++) {
657 channel
= find_next_bit(edma_cc
[i
]->edma_unused
,
658 edma_cc
[i
]->num_channels
,
660 if (channel
== edma_cc
[i
]->num_channels
)
662 if (!test_and_set_bit(channel
,
663 edma_cc
[i
]->edma_inuse
)) {
675 } else if (channel
>= edma_cc
[ctlr
]->num_channels
) {
677 } else if (test_and_set_bit(channel
, edma_cc
[ctlr
]->edma_inuse
)) {
681 /* ensure access through shadow region 0 */
682 edma_or_array2(ctlr
, EDMA_DRAE
, 0, channel
>> 5, BIT(channel
& 0x1f));
684 /* ensure no events are pending */
685 edma_stop(EDMA_CTLR_CHAN(ctlr
, channel
));
686 memcpy_toio(edmacc_regs_base
[ctlr
] + PARM_OFFSET(channel
),
687 &dummy_paramset
, PARM_SIZE
);
690 setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr
, channel
),
693 map_dmach_queue(ctlr
, channel
, eventq_no
);
695 return EDMA_CTLR_CHAN(ctlr
, channel
);
697 EXPORT_SYMBOL(edma_alloc_channel
);
701 * edma_free_channel - deallocate DMA channel
702 * @channel: dma channel returned from edma_alloc_channel()
704 * This deallocates the DMA channel and associated parameter RAM slot
705 * allocated by edma_alloc_channel().
707 * Callers are responsible for ensuring the channel is inactive, and
708 * will not be reactivated by linking, chaining, or software calls to
711 void edma_free_channel(unsigned channel
)
715 ctlr
= EDMA_CTLR(channel
);
716 channel
= EDMA_CHAN_SLOT(channel
);
718 if (channel
>= edma_cc
[ctlr
]->num_channels
)
721 setup_dma_interrupt(channel
, NULL
, NULL
);
722 /* REVISIT should probably take out of shadow region 0 */
724 memcpy_toio(edmacc_regs_base
[ctlr
] + PARM_OFFSET(channel
),
725 &dummy_paramset
, PARM_SIZE
);
726 clear_bit(channel
, edma_cc
[ctlr
]->edma_inuse
);
728 EXPORT_SYMBOL(edma_free_channel
);
731 * edma_alloc_slot - allocate DMA parameter RAM
732 * @slot: specific slot to allocate; negative for "any unused slot"
734 * This allocates a parameter RAM slot, initializing it to hold a
735 * dummy transfer. Slots allocated using this routine have not been
736 * mapped to a hardware DMA channel, and will normally be used by
737 * linking to them from a slot associated with a DMA channel.
739 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
740 * slots may be allocated on behalf of DSP firmware.
742 * Returns the number of the slot, else negative errno.
744 int edma_alloc_slot(unsigned ctlr
, int slot
)
747 slot
= EDMA_CHAN_SLOT(slot
);
750 slot
= edma_cc
[ctlr
]->num_channels
;
752 slot
= find_next_zero_bit(edma_cc
[ctlr
]->edma_inuse
,
753 edma_cc
[ctlr
]->num_slots
, slot
);
754 if (slot
== edma_cc
[ctlr
]->num_slots
)
756 if (!test_and_set_bit(slot
, edma_cc
[ctlr
]->edma_inuse
))
759 } else if (slot
< edma_cc
[ctlr
]->num_channels
||
760 slot
>= edma_cc
[ctlr
]->num_slots
) {
762 } else if (test_and_set_bit(slot
, edma_cc
[ctlr
]->edma_inuse
)) {
766 memcpy_toio(edmacc_regs_base
[ctlr
] + PARM_OFFSET(slot
),
767 &dummy_paramset
, PARM_SIZE
);
769 return EDMA_CTLR_CHAN(ctlr
, slot
);
771 EXPORT_SYMBOL(edma_alloc_slot
);
774 * edma_free_slot - deallocate DMA parameter RAM
775 * @slot: parameter RAM slot returned from edma_alloc_slot()
777 * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
778 * Callers are responsible for ensuring the slot is inactive, and will
781 void edma_free_slot(unsigned slot
)
785 ctlr
= EDMA_CTLR(slot
);
786 slot
= EDMA_CHAN_SLOT(slot
);
788 if (slot
< edma_cc
[ctlr
]->num_channels
||
789 slot
>= edma_cc
[ctlr
]->num_slots
)
792 memcpy_toio(edmacc_regs_base
[ctlr
] + PARM_OFFSET(slot
),
793 &dummy_paramset
, PARM_SIZE
);
794 clear_bit(slot
, edma_cc
[ctlr
]->edma_inuse
);
796 EXPORT_SYMBOL(edma_free_slot
);
800 * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
801 * The API will return the starting point of a set of
802 * contiguous parameter RAM slots that have been requested
804 * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
805 * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
806 * @count: number of contiguous Paramter RAM slots
807 * @slot - the start value of Parameter RAM slot that should be passed if id
808 * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
810 * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
811 * contiguous Parameter RAM slots from parameter RAM 64 in the case of
812 * DaVinci SOCs and 32 in the case of DA8xx SOCs.
814 * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
815 * set of contiguous parameter RAM slots from the "slot" that is passed as an
816 * argument to the API.
818 * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
819 * starts looking for a set of contiguous parameter RAMs from the "slot"
820 * that is passed as an argument to the API. On failure the API will try to
821 * find a set of contiguous Parameter RAM slots from the remaining Parameter
824 int edma_alloc_cont_slots(unsigned ctlr
, unsigned int id
, int slot
, int count
)
827 * The start slot requested should be greater than
828 * the number of channels and lesser than the total number
831 if ((id
!= EDMA_CONT_PARAMS_ANY
) &&
832 (slot
< edma_cc
[ctlr
]->num_channels
||
833 slot
>= edma_cc
[ctlr
]->num_slots
))
837 * The number of parameter RAM slots requested cannot be less than 1
838 * and cannot be more than the number of slots minus the number of
841 if (count
< 1 || count
>
842 (edma_cc
[ctlr
]->num_slots
- edma_cc
[ctlr
]->num_channels
))
846 case EDMA_CONT_PARAMS_ANY
:
847 return reserve_contiguous_slots(ctlr
, id
, count
,
848 edma_cc
[ctlr
]->num_channels
);
849 case EDMA_CONT_PARAMS_FIXED_EXACT
:
850 case EDMA_CONT_PARAMS_FIXED_NOT_EXACT
:
851 return reserve_contiguous_slots(ctlr
, id
, count
, slot
);
857 EXPORT_SYMBOL(edma_alloc_cont_slots
);
860 * edma_free_cont_slots - deallocate DMA parameter RAM slots
861 * @slot: first parameter RAM of a set of parameter RAM slots to be freed
862 * @count: the number of contiguous parameter RAM slots to be freed
864 * This deallocates the parameter RAM slots allocated by
865 * edma_alloc_cont_slots.
866 * Callers/applications need to keep track of sets of contiguous
867 * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
869 * Callers are responsible for ensuring the slots are inactive, and will
872 int edma_free_cont_slots(unsigned slot
, int count
)
874 unsigned ctlr
, slot_to_free
;
877 ctlr
= EDMA_CTLR(slot
);
878 slot
= EDMA_CHAN_SLOT(slot
);
880 if (slot
< edma_cc
[ctlr
]->num_channels
||
881 slot
>= edma_cc
[ctlr
]->num_slots
||
885 for (i
= slot
; i
< slot
+ count
; ++i
) {
887 slot_to_free
= EDMA_CHAN_SLOT(i
);
889 memcpy_toio(edmacc_regs_base
[ctlr
] + PARM_OFFSET(slot_to_free
),
890 &dummy_paramset
, PARM_SIZE
);
891 clear_bit(slot_to_free
, edma_cc
[ctlr
]->edma_inuse
);
896 EXPORT_SYMBOL(edma_free_cont_slots
);
898 /*-----------------------------------------------------------------------*/
900 /* Parameter RAM operations (i) -- read/write partial slots */
903 * edma_set_src - set initial DMA source address in parameter RAM slot
904 * @slot: parameter RAM slot being configured
905 * @src_port: physical address of source (memory, controller FIFO, etc)
906 * @addressMode: INCR, except in very rare cases
907 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
908 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
910 * Note that the source address is modified during the DMA transfer
911 * according to edma_set_src_index().
913 void edma_set_src(unsigned slot
, dma_addr_t src_port
,
914 enum address_mode mode
, enum fifo_width width
)
918 ctlr
= EDMA_CTLR(slot
);
919 slot
= EDMA_CHAN_SLOT(slot
);
921 if (slot
< edma_cc
[ctlr
]->num_slots
) {
922 unsigned int i
= edma_parm_read(ctlr
, PARM_OPT
, slot
);
925 /* set SAM and program FWID */
926 i
= (i
& ~(EDMA_FWID
)) | (SAM
| ((width
& 0x7) << 8));
931 edma_parm_write(ctlr
, PARM_OPT
, slot
, i
);
933 /* set the source port address
934 in source register of param structure */
935 edma_parm_write(ctlr
, PARM_SRC
, slot
, src_port
);
938 EXPORT_SYMBOL(edma_set_src
);
941 * edma_set_dest - set initial DMA destination address in parameter RAM slot
942 * @slot: parameter RAM slot being configured
943 * @dest_port: physical address of destination (memory, controller FIFO, etc)
944 * @addressMode: INCR, except in very rare cases
945 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
946 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
948 * Note that the destination address is modified during the DMA transfer
949 * according to edma_set_dest_index().
951 void edma_set_dest(unsigned slot
, dma_addr_t dest_port
,
952 enum address_mode mode
, enum fifo_width width
)
956 ctlr
= EDMA_CTLR(slot
);
957 slot
= EDMA_CHAN_SLOT(slot
);
959 if (slot
< edma_cc
[ctlr
]->num_slots
) {
960 unsigned int i
= edma_parm_read(ctlr
, PARM_OPT
, slot
);
963 /* set DAM and program FWID */
964 i
= (i
& ~(EDMA_FWID
)) | (DAM
| ((width
& 0x7) << 8));
969 edma_parm_write(ctlr
, PARM_OPT
, slot
, i
);
970 /* set the destination port address
971 in dest register of param structure */
972 edma_parm_write(ctlr
, PARM_DST
, slot
, dest_port
);
975 EXPORT_SYMBOL(edma_set_dest
);
978 * edma_get_position - returns the current transfer points
979 * @slot: parameter RAM slot being examined
980 * @src: pointer to source port position
981 * @dst: pointer to destination port position
983 * Returns current source and destination addresses for a particular
984 * parameter RAM slot. Its channel should not be active when this is called.
986 void edma_get_position(unsigned slot
, dma_addr_t
*src
, dma_addr_t
*dst
)
988 struct edmacc_param temp
;
991 ctlr
= EDMA_CTLR(slot
);
992 slot
= EDMA_CHAN_SLOT(slot
);
994 edma_read_slot(EDMA_CTLR_CHAN(ctlr
, slot
), &temp
);
1000 EXPORT_SYMBOL(edma_get_position
);
1003 * edma_set_src_index - configure DMA source address indexing
1004 * @slot: parameter RAM slot being configured
1005 * @src_bidx: byte offset between source arrays in a frame
1006 * @src_cidx: byte offset between source frames in a block
1008 * Offsets are specified to support either contiguous or discontiguous
1009 * memory transfers, or repeated access to a hardware register, as needed.
1010 * When accessing hardware registers, both offsets are normally zero.
1012 void edma_set_src_index(unsigned slot
, s16 src_bidx
, s16 src_cidx
)
1016 ctlr
= EDMA_CTLR(slot
);
1017 slot
= EDMA_CHAN_SLOT(slot
);
1019 if (slot
< edma_cc
[ctlr
]->num_slots
) {
1020 edma_parm_modify(ctlr
, PARM_SRC_DST_BIDX
, slot
,
1021 0xffff0000, src_bidx
);
1022 edma_parm_modify(ctlr
, PARM_SRC_DST_CIDX
, slot
,
1023 0xffff0000, src_cidx
);
1026 EXPORT_SYMBOL(edma_set_src_index
);
1029 * edma_set_dest_index - configure DMA destination address indexing
1030 * @slot: parameter RAM slot being configured
1031 * @dest_bidx: byte offset between destination arrays in a frame
1032 * @dest_cidx: byte offset between destination frames in a block
1034 * Offsets are specified to support either contiguous or discontiguous
1035 * memory transfers, or repeated access to a hardware register, as needed.
1036 * When accessing hardware registers, both offsets are normally zero.
1038 void edma_set_dest_index(unsigned slot
, s16 dest_bidx
, s16 dest_cidx
)
1042 ctlr
= EDMA_CTLR(slot
);
1043 slot
= EDMA_CHAN_SLOT(slot
);
1045 if (slot
< edma_cc
[ctlr
]->num_slots
) {
1046 edma_parm_modify(ctlr
, PARM_SRC_DST_BIDX
, slot
,
1047 0x0000ffff, dest_bidx
<< 16);
1048 edma_parm_modify(ctlr
, PARM_SRC_DST_CIDX
, slot
,
1049 0x0000ffff, dest_cidx
<< 16);
1052 EXPORT_SYMBOL(edma_set_dest_index
);
1055 * edma_set_transfer_params - configure DMA transfer parameters
1056 * @slot: parameter RAM slot being configured
1057 * @acnt: how many bytes per array (at least one)
1058 * @bcnt: how many arrays per frame (at least one)
1059 * @ccnt: how many frames per block (at least one)
1060 * @bcnt_rld: used only for A-Synchronized transfers; this specifies
1061 * the value to reload into bcnt when it decrements to zero
1062 * @sync_mode: ASYNC or ABSYNC
1064 * See the EDMA3 documentation to understand how to configure and link
1065 * transfers using the fields in PaRAM slots. If you are not doing it
1066 * all at once with edma_write_slot(), you will use this routine
1067 * plus two calls each for source and destination, setting the initial
1068 * address and saying how to index that address.
1070 * An example of an A-Synchronized transfer is a serial link using a
1071 * single word shift register. In that case, @acnt would be equal to
1072 * that word size; the serial controller issues a DMA synchronization
1073 * event to transfer each word, and memory access by the DMA transfer
1074 * controller will be word-at-a-time.
1076 * An example of an AB-Synchronized transfer is a device using a FIFO.
1077 * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
1078 * The controller with the FIFO issues DMA synchronization events when
1079 * the FIFO threshold is reached, and the DMA transfer controller will
1080 * transfer one frame to (or from) the FIFO. It will probably use
1081 * efficient burst modes to access memory.
1083 void edma_set_transfer_params(unsigned slot
,
1084 u16 acnt
, u16 bcnt
, u16 ccnt
,
1085 u16 bcnt_rld
, enum sync_dimension sync_mode
)
1089 ctlr
= EDMA_CTLR(slot
);
1090 slot
= EDMA_CHAN_SLOT(slot
);
1092 if (slot
< edma_cc
[ctlr
]->num_slots
) {
1093 edma_parm_modify(ctlr
, PARM_LINK_BCNTRLD
, slot
,
1094 0x0000ffff, bcnt_rld
<< 16);
1095 if (sync_mode
== ASYNC
)
1096 edma_parm_and(ctlr
, PARM_OPT
, slot
, ~SYNCDIM
);
1098 edma_parm_or(ctlr
, PARM_OPT
, slot
, SYNCDIM
);
1099 /* Set the acount, bcount, ccount registers */
1100 edma_parm_write(ctlr
, PARM_A_B_CNT
, slot
, (bcnt
<< 16) | acnt
);
1101 edma_parm_write(ctlr
, PARM_CCNT
, slot
, ccnt
);
1104 EXPORT_SYMBOL(edma_set_transfer_params
);
1107 * edma_link - link one parameter RAM slot to another
1108 * @from: parameter RAM slot originating the link
1109 * @to: parameter RAM slot which is the link target
1111 * The originating slot should not be part of any active DMA transfer.
1113 void edma_link(unsigned from
, unsigned to
)
1115 unsigned ctlr_from
, ctlr_to
;
1117 ctlr_from
= EDMA_CTLR(from
);
1118 from
= EDMA_CHAN_SLOT(from
);
1119 ctlr_to
= EDMA_CTLR(to
);
1120 to
= EDMA_CHAN_SLOT(to
);
1122 if (from
>= edma_cc
[ctlr_from
]->num_slots
)
1124 if (to
>= edma_cc
[ctlr_to
]->num_slots
)
1126 edma_parm_modify(ctlr_from
, PARM_LINK_BCNTRLD
, from
, 0xffff0000,
1129 EXPORT_SYMBOL(edma_link
);
1132 * edma_unlink - cut link from one parameter RAM slot
1133 * @from: parameter RAM slot originating the link
1135 * The originating slot should not be part of any active DMA transfer.
1136 * Its link is set to 0xffff.
1138 void edma_unlink(unsigned from
)
1142 ctlr
= EDMA_CTLR(from
);
1143 from
= EDMA_CHAN_SLOT(from
);
1145 if (from
>= edma_cc
[ctlr
]->num_slots
)
1147 edma_parm_or(ctlr
, PARM_LINK_BCNTRLD
, from
, 0xffff);
1149 EXPORT_SYMBOL(edma_unlink
);
1151 /*-----------------------------------------------------------------------*/
1153 /* Parameter RAM operations (ii) -- read/write whole parameter sets */
1156 * edma_write_slot - write parameter RAM data for slot
1157 * @slot: number of parameter RAM slot being modified
1158 * @param: data to be written into parameter RAM slot
1160 * Use this to assign all parameters of a transfer at once. This
1161 * allows more efficient setup of transfers than issuing multiple
1162 * calls to set up those parameters in small pieces, and provides
1163 * complete control over all transfer options.
1165 void edma_write_slot(unsigned slot
, const struct edmacc_param
*param
)
1169 ctlr
= EDMA_CTLR(slot
);
1170 slot
= EDMA_CHAN_SLOT(slot
);
1172 if (slot
>= edma_cc
[ctlr
]->num_slots
)
1174 memcpy_toio(edmacc_regs_base
[ctlr
] + PARM_OFFSET(slot
), param
,
1177 EXPORT_SYMBOL(edma_write_slot
);
1180 * edma_read_slot - read parameter RAM data from slot
1181 * @slot: number of parameter RAM slot being copied
1182 * @param: where to store copy of parameter RAM data
1184 * Use this to read data from a parameter RAM slot, perhaps to
1185 * save them as a template for later reuse.
1187 void edma_read_slot(unsigned slot
, struct edmacc_param
*param
)
1191 ctlr
= EDMA_CTLR(slot
);
1192 slot
= EDMA_CHAN_SLOT(slot
);
1194 if (slot
>= edma_cc
[ctlr
]->num_slots
)
1196 memcpy_fromio(param
, edmacc_regs_base
[ctlr
] + PARM_OFFSET(slot
),
1199 EXPORT_SYMBOL(edma_read_slot
);
1201 /*-----------------------------------------------------------------------*/
1203 /* Various EDMA channel control operations */
1206 * edma_pause - pause dma on a channel
1207 * @channel: on which edma_start() has been called
1209 * This temporarily disables EDMA hardware events on the specified channel,
1210 * preventing them from triggering new transfers on its behalf
1212 void edma_pause(unsigned channel
)
1216 ctlr
= EDMA_CTLR(channel
);
1217 channel
= EDMA_CHAN_SLOT(channel
);
1219 if (channel
< edma_cc
[ctlr
]->num_channels
) {
1220 unsigned int mask
= BIT(channel
& 0x1f);
1222 edma_shadow0_write_array(ctlr
, SH_EECR
, channel
>> 5, mask
);
1225 EXPORT_SYMBOL(edma_pause
);
1228 * edma_resume - resumes dma on a paused channel
1229 * @channel: on which edma_pause() has been called
1231 * This re-enables EDMA hardware events on the specified channel.
1233 void edma_resume(unsigned channel
)
1237 ctlr
= EDMA_CTLR(channel
);
1238 channel
= EDMA_CHAN_SLOT(channel
);
1240 if (channel
< edma_cc
[ctlr
]->num_channels
) {
1241 unsigned int mask
= BIT(channel
& 0x1f);
1243 edma_shadow0_write_array(ctlr
, SH_EESR
, channel
>> 5, mask
);
1246 EXPORT_SYMBOL(edma_resume
);
1249 * edma_start - start dma on a channel
1250 * @channel: channel being activated
1252 * Channels with event associations will be triggered by their hardware
1253 * events, and channels without such associations will be triggered by
1254 * software. (At this writing there is no interface for using software
1255 * triggers except with channels that don't support hardware triggers.)
1257 * Returns zero on success, else negative errno.
1259 int edma_start(unsigned channel
)
1263 ctlr
= EDMA_CTLR(channel
);
1264 channel
= EDMA_CHAN_SLOT(channel
);
1266 if (channel
< edma_cc
[ctlr
]->num_channels
) {
1267 int j
= channel
>> 5;
1268 unsigned int mask
= BIT(channel
& 0x1f);
1270 /* EDMA channels without event association */
1271 if (test_bit(channel
, edma_cc
[ctlr
]->edma_unused
)) {
1272 pr_debug("EDMA: ESR%d %08x\n", j
,
1273 edma_shadow0_read_array(ctlr
, SH_ESR
, j
));
1274 edma_shadow0_write_array(ctlr
, SH_ESR
, j
, mask
);
1278 /* EDMA channel with event association */
1279 pr_debug("EDMA: ER%d %08x\n", j
,
1280 edma_shadow0_read_array(ctlr
, SH_ER
, j
));
1281 /* Clear any pending event or error */
1282 edma_write_array(ctlr
, EDMA_ECR
, j
, mask
);
1283 edma_write_array(ctlr
, EDMA_EMCR
, j
, mask
);
1285 edma_shadow0_write_array(ctlr
, SH_SECR
, j
, mask
);
1286 edma_shadow0_write_array(ctlr
, SH_EESR
, j
, mask
);
1287 pr_debug("EDMA: EER%d %08x\n", j
,
1288 edma_shadow0_read_array(ctlr
, SH_EER
, j
));
1294 EXPORT_SYMBOL(edma_start
);
1297 * edma_stop - stops dma on the channel passed
1298 * @channel: channel being deactivated
1300 * When @lch is a channel, any active transfer is paused and
1301 * all pending hardware events are cleared. The current transfer
1302 * may not be resumed, and the channel's Parameter RAM should be
1303 * reinitialized before being reused.
1305 void edma_stop(unsigned channel
)
1309 ctlr
= EDMA_CTLR(channel
);
1310 channel
= EDMA_CHAN_SLOT(channel
);
1312 if (channel
< edma_cc
[ctlr
]->num_channels
) {
1313 int j
= channel
>> 5;
1314 unsigned int mask
= BIT(channel
& 0x1f);
1316 edma_shadow0_write_array(ctlr
, SH_EECR
, j
, mask
);
1317 edma_shadow0_write_array(ctlr
, SH_ECR
, j
, mask
);
1318 edma_shadow0_write_array(ctlr
, SH_SECR
, j
, mask
);
1319 edma_write_array(ctlr
, EDMA_EMCR
, j
, mask
);
1321 pr_debug("EDMA: EER%d %08x\n", j
,
1322 edma_shadow0_read_array(ctlr
, SH_EER
, j
));
1324 /* REVISIT: consider guarding against inappropriate event
1325 * chaining by overwriting with dummy_paramset.
1329 EXPORT_SYMBOL(edma_stop
);
1331 /******************************************************************************
1333 * It cleans ParamEntry qand bring back EDMA to initial state if media has
1334 * been removed before EDMA has finished.It is usedful for removable media.
1336 * ch_no - channel no
1338 * Return: zero on success, or corresponding error no on failure
1340 * FIXME this should not be needed ... edma_stop() should suffice.
1342 *****************************************************************************/
1344 void edma_clean_channel(unsigned channel
)
1348 ctlr
= EDMA_CTLR(channel
);
1349 channel
= EDMA_CHAN_SLOT(channel
);
1351 if (channel
< edma_cc
[ctlr
]->num_channels
) {
1352 int j
= (channel
>> 5);
1353 unsigned int mask
= BIT(channel
& 0x1f);
1355 pr_debug("EDMA: EMR%d %08x\n", j
,
1356 edma_read_array(ctlr
, EDMA_EMR
, j
));
1357 edma_shadow0_write_array(ctlr
, SH_ECR
, j
, mask
);
1358 /* Clear the corresponding EMR bits */
1359 edma_write_array(ctlr
, EDMA_EMCR
, j
, mask
);
1361 edma_shadow0_write_array(ctlr
, SH_SECR
, j
, mask
);
1362 edma_write(ctlr
, EDMA_CCERRCLR
, BIT(16) | BIT(1) | BIT(0));
1365 EXPORT_SYMBOL(edma_clean_channel
);
1368 * edma_clear_event - clear an outstanding event on the DMA channel
1370 * channel - channel number
1372 void edma_clear_event(unsigned channel
)
1376 ctlr
= EDMA_CTLR(channel
);
1377 channel
= EDMA_CHAN_SLOT(channel
);
1379 if (channel
>= edma_cc
[ctlr
]->num_channels
)
1382 edma_write(ctlr
, EDMA_ECR
, BIT(channel
));
1384 edma_write(ctlr
, EDMA_ECRH
, BIT(channel
- 32));
1386 EXPORT_SYMBOL(edma_clear_event
);
1388 /*-----------------------------------------------------------------------*/
1390 static int __init
edma_probe(struct platform_device
*pdev
)
1392 struct edma_soc_info
**info
= pdev
->dev
.platform_data
;
1393 const s8 (*queue_priority_mapping
)[2];
1394 const s8 (*queue_tc_mapping
)[2];
1395 int i
, j
, off
, ln
, found
= 0;
1397 const s16 (*rsv_chans
)[2];
1398 const s16 (*rsv_slots
)[2];
1399 int irq
[EDMA_MAX_CC
] = {0, 0};
1400 int err_irq
[EDMA_MAX_CC
] = {0, 0};
1401 struct resource
*r
[EDMA_MAX_CC
] = {NULL
};
1402 resource_size_t len
[EDMA_MAX_CC
];
1409 for (j
= 0; j
< EDMA_MAX_CC
; j
++) {
1410 sprintf(res_name
, "edma_cc%d", j
);
1411 r
[j
] = platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
1413 if (!r
[j
] || !info
[j
]) {
1422 len
[j
] = resource_size(r
[j
]);
1424 r
[j
] = request_mem_region(r
[j
]->start
, len
[j
],
1425 dev_name(&pdev
->dev
));
1431 edmacc_regs_base
[j
] = ioremap(r
[j
]->start
, len
[j
]);
1432 if (!edmacc_regs_base
[j
]) {
1437 edma_cc
[j
] = kzalloc(sizeof(struct edma
), GFP_KERNEL
);
1443 edma_cc
[j
]->num_channels
= min_t(unsigned, info
[j
]->n_channel
,
1445 edma_cc
[j
]->num_slots
= min_t(unsigned, info
[j
]->n_slot
,
1446 EDMA_MAX_PARAMENTRY
);
1447 edma_cc
[j
]->num_cc
= min_t(unsigned, info
[j
]->n_cc
,
1450 edma_cc
[j
]->default_queue
= info
[j
]->default_queue
;
1452 dev_dbg(&pdev
->dev
, "DMA REG BASE ADDR=%p\n",
1453 edmacc_regs_base
[j
]);
1455 for (i
= 0; i
< edma_cc
[j
]->num_slots
; i
++)
1456 memcpy_toio(edmacc_regs_base
[j
] + PARM_OFFSET(i
),
1457 &dummy_paramset
, PARM_SIZE
);
1459 /* Mark all channels as unused */
1460 memset(edma_cc
[j
]->edma_unused
, 0xff,
1461 sizeof(edma_cc
[j
]->edma_unused
));
1465 /* Clear the reserved channels in unused list */
1466 rsv_chans
= info
[j
]->rsv
->rsv_chans
;
1468 for (i
= 0; rsv_chans
[i
][0] != -1; i
++) {
1469 off
= rsv_chans
[i
][0];
1470 ln
= rsv_chans
[i
][1];
1472 edma_cc
[j
]->edma_unused
);
1476 /* Set the reserved slots in inuse list */
1477 rsv_slots
= info
[j
]->rsv
->rsv_slots
;
1479 for (i
= 0; rsv_slots
[i
][0] != -1; i
++) {
1480 off
= rsv_slots
[i
][0];
1481 ln
= rsv_slots
[i
][1];
1483 edma_cc
[j
]->edma_inuse
);
1488 sprintf(irq_name
, "edma%d", j
);
1489 irq
[j
] = platform_get_irq_byname(pdev
, irq_name
);
1490 edma_cc
[j
]->irq_res_start
= irq
[j
];
1491 status
= request_irq(irq
[j
], dma_irq_handler
, 0, "edma",
1494 dev_dbg(&pdev
->dev
, "request_irq %d failed --> %d\n",
1499 sprintf(irq_name
, "edma%d_err", j
);
1500 err_irq
[j
] = platform_get_irq_byname(pdev
, irq_name
);
1501 edma_cc
[j
]->irq_res_end
= err_irq
[j
];
1502 status
= request_irq(err_irq
[j
], dma_ccerr_handler
, 0,
1503 "edma_error", &pdev
->dev
);
1505 dev_dbg(&pdev
->dev
, "request_irq %d failed --> %d\n",
1506 err_irq
[j
], status
);
1510 for (i
= 0; i
< edma_cc
[j
]->num_channels
; i
++)
1511 map_dmach_queue(j
, i
, info
[j
]->default_queue
);
1513 queue_tc_mapping
= info
[j
]->queue_tc_mapping
;
1514 queue_priority_mapping
= info
[j
]->queue_priority_mapping
;
1516 /* Event queue to TC mapping */
1517 for (i
= 0; queue_tc_mapping
[i
][0] != -1; i
++)
1518 map_queue_tc(j
, queue_tc_mapping
[i
][0],
1519 queue_tc_mapping
[i
][1]);
1521 /* Event queue priority mapping */
1522 for (i
= 0; queue_priority_mapping
[i
][0] != -1; i
++)
1523 assign_priority_to_queue(j
,
1524 queue_priority_mapping
[i
][0],
1525 queue_priority_mapping
[i
][1]);
1527 /* Map the channel to param entry if channel mapping logic
1530 if (edma_read(j
, EDMA_CCCFG
) & CHMAP_EXIST
)
1533 for (i
= 0; i
< info
[j
]->n_region
; i
++) {
1534 edma_write_array2(j
, EDMA_DRAE
, i
, 0, 0x0);
1535 edma_write_array2(j
, EDMA_DRAE
, i
, 1, 0x0);
1536 edma_write_array(j
, EDMA_QRAE
, i
, 0x0);
1541 if (tc_errs_handled
) {
1542 status
= request_irq(IRQ_TCERRINT0
, dma_tc0err_handler
, 0,
1543 "edma_tc0", &pdev
->dev
);
1545 dev_dbg(&pdev
->dev
, "request_irq %d failed --> %d\n",
1546 IRQ_TCERRINT0
, status
);
1549 status
= request_irq(IRQ_TCERRINT
, dma_tc1err_handler
, 0,
1550 "edma_tc1", &pdev
->dev
);
1552 dev_dbg(&pdev
->dev
, "request_irq %d --> %d\n",
1553 IRQ_TCERRINT
, status
);
1561 for (i
= 0; i
< EDMA_MAX_CC
; i
++) {
1563 free_irq(err_irq
[i
], &pdev
->dev
);
1565 free_irq(irq
[i
], &pdev
->dev
);
1568 for (i
= 0; i
< EDMA_MAX_CC
; i
++) {
1570 release_mem_region(r
[i
]->start
, len
[i
]);
1571 if (edmacc_regs_base
[i
])
1572 iounmap(edmacc_regs_base
[i
]);
1579 static struct platform_driver edma_driver
= {
1580 .driver
.name
= "edma",
1583 static int __init
edma_init(void)
1585 return platform_driver_probe(&edma_driver
, edma_probe
);
1587 arch_initcall(edma_init
);