Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / kernel / head-nommu.S
1 /*
2 * linux/arch/arm/kernel/head-nommu.S
3 *
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (C) 2003-2006 Hyok S. Choi
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Common kernel startup code (non-paged MM)
12 *
13 */
14 #include <linux/linkage.h>
15 #include <linux/init.h>
16
17 #include <asm/assembler.h>
18 #include <asm/ptrace.h>
19 #include <asm/asm-offsets.h>
20 #include <asm/cp15.h>
21 #include <asm/thread_info.h>
22
23 /*
24 * Kernel startup entry point.
25 * ---------------------------
26 *
27 * This is normally called from the decompressor code. The requirements
28 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
29 * r1 = machine nr.
30 *
31 * See linux/arch/arm/tools/mach-types for the complete list of machine
32 * numbers for r1.
33 *
34 */
35
36 __HEAD
37
38 #ifdef CONFIG_CPU_THUMBONLY
39 .thumb
40 ENTRY(stext)
41 #else
42 .arm
43 ENTRY(stext)
44
45 THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM.
46 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
47 THUMB( .thumb ) @ switch to Thumb now.
48 THUMB(1: )
49 #endif
50
51 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
52 @ and irqs disabled
53 #ifndef CONFIG_CPU_CP15
54 ldr r9, =CONFIG_PROCESSOR_ID
55 #else
56 mrc p15, 0, r9, c0, c0 @ get processor id
57 #endif
58 bl __lookup_processor_type @ r5=procinfo r9=cpuid
59 movs r10, r5 @ invalid processor (r5=0)?
60 beq __error_p @ yes, error 'p'
61
62 adr lr, BSYM(__after_proc_init) @ return (PIC) address
63 ARM( add pc, r10, #PROCINFO_INITFUNC )
64 THUMB( add r12, r10, #PROCINFO_INITFUNC )
65 THUMB( mov pc, r12 )
66 ENDPROC(stext)
67
68 /*
69 * Set the Control Register and Read the process ID.
70 */
71 __after_proc_init:
72 #ifdef CONFIG_CPU_CP15
73 /*
74 * CP15 system control register value returned in r0 from
75 * the CPU init function.
76 */
77 #if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
78 orr r0, r0, #CR_A
79 #else
80 bic r0, r0, #CR_A
81 #endif
82 #ifdef CONFIG_CPU_DCACHE_DISABLE
83 bic r0, r0, #CR_C
84 #endif
85 #ifdef CONFIG_CPU_BPREDICT_DISABLE
86 bic r0, r0, #CR_Z
87 #endif
88 #ifdef CONFIG_CPU_ICACHE_DISABLE
89 bic r0, r0, #CR_I
90 #endif
91 #ifdef CONFIG_CPU_HIGH_VECTOR
92 orr r0, r0, #CR_V
93 #else
94 bic r0, r0, #CR_V
95 #endif
96 mcr p15, 0, r0, c1, c0, 0 @ write control reg
97 #endif /* CONFIG_CPU_CP15 */
98
99 b __mmap_switched @ clear the BSS and jump
100 @ to start_kernel
101 ENDPROC(__after_proc_init)
102 .ltorg
103
104 #include "head-common.S"