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ARM: entry: prefetch abort: tail-call the main prefetch abort handler
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / kernel / entry-armv.S
1 /*
2 * linux/arch/arm/kernel/entry-armv.S
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Low-level vector interface routines
13 *
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
16 */
17
18 #include <asm/memory.h>
19 #include <asm/glue-df.h>
20 #include <asm/glue-pf.h>
21 #include <asm/vfpmacros.h>
22 #include <mach/entry-macro.S>
23 #include <asm/thread_notify.h>
24 #include <asm/unwind.h>
25 #include <asm/unistd.h>
26 #include <asm/tls.h>
27
28 #include "entry-header.S"
29 #include <asm/entry-macro-multi.S>
30
31 /*
32 * Interrupt handling.
33 */
34 .macro irq_handler
35 #ifdef CONFIG_MULTI_IRQ_HANDLER
36 ldr r1, =handle_arch_irq
37 mov r0, sp
38 ldr r1, [r1]
39 adr lr, BSYM(9997f)
40 teq r1, #0
41 movne pc, r1
42 #endif
43 arch_irq_handler_default
44 9997:
45 .endm
46
47 .macro pabt_helper
48 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
49 #ifdef MULTI_PABORT
50 ldr ip, .LCprocfns
51 mov lr, pc
52 ldr pc, [ip, #PROCESSOR_PABT_FUNC]
53 #else
54 bl CPU_PABORT_HANDLER
55 #endif
56 .endm
57
58 .macro dabt_helper
59 mov r2, r4
60 mov r3, r5
61
62 @
63 @ Call the processor-specific abort handler:
64 @
65 @ r2 - aborted context pc
66 @ r3 - aborted context cpsr
67 @
68 @ The abort handler must return the aborted address in r0, and
69 @ the fault status register in r1. r9 must be preserved.
70 @
71 #ifdef MULTI_DABORT
72 ldr ip, .LCprocfns
73 mov lr, pc
74 ldr pc, [ip, #PROCESSOR_DABT_FUNC]
75 #else
76 bl CPU_DABORT_HANDLER
77 #endif
78 .endm
79
80 #ifdef CONFIG_KPROBES
81 .section .kprobes.text,"ax",%progbits
82 #else
83 .text
84 #endif
85
86 /*
87 * Invalid mode handlers
88 */
89 .macro inv_entry, reason
90 sub sp, sp, #S_FRAME_SIZE
91 ARM( stmib sp, {r1 - lr} )
92 THUMB( stmia sp, {r0 - r12} )
93 THUMB( str sp, [sp, #S_SP] )
94 THUMB( str lr, [sp, #S_LR] )
95 mov r1, #\reason
96 .endm
97
98 __pabt_invalid:
99 inv_entry BAD_PREFETCH
100 b common_invalid
101 ENDPROC(__pabt_invalid)
102
103 __dabt_invalid:
104 inv_entry BAD_DATA
105 b common_invalid
106 ENDPROC(__dabt_invalid)
107
108 __irq_invalid:
109 inv_entry BAD_IRQ
110 b common_invalid
111 ENDPROC(__irq_invalid)
112
113 __und_invalid:
114 inv_entry BAD_UNDEFINSTR
115
116 @
117 @ XXX fall through to common_invalid
118 @
119
120 @
121 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
122 @
123 common_invalid:
124 zero_fp
125
126 ldmia r0, {r4 - r6}
127 add r0, sp, #S_PC @ here for interlock avoidance
128 mov r7, #-1 @ "" "" "" ""
129 str r4, [sp] @ save preserved r0
130 stmia r0, {r5 - r7} @ lr_<exception>,
131 @ cpsr_<exception>, "old_r0"
132
133 mov r0, sp
134 b bad_mode
135 ENDPROC(__und_invalid)
136
137 /*
138 * SVC mode handlers
139 */
140
141 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
142 #define SPFIX(code...) code
143 #else
144 #define SPFIX(code...)
145 #endif
146
147 .macro svc_entry, stack_hole=0
148 UNWIND(.fnstart )
149 UNWIND(.save {r0 - pc} )
150 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
151 #ifdef CONFIG_THUMB2_KERNEL
152 SPFIX( str r0, [sp] ) @ temporarily saved
153 SPFIX( mov r0, sp )
154 SPFIX( tst r0, #4 ) @ test original stack alignment
155 SPFIX( ldr r0, [sp] ) @ restored
156 #else
157 SPFIX( tst sp, #4 )
158 #endif
159 SPFIX( subeq sp, sp, #4 )
160 stmia sp, {r1 - r12}
161
162 ldmia r0, {r3 - r5}
163 add r7, sp, #S_SP - 4 @ here for interlock avoidance
164 mov r6, #-1 @ "" "" "" ""
165 add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4)
166 SPFIX( addeq r2, r2, #4 )
167 str r3, [sp, #-4]! @ save the "real" r0 copied
168 @ from the exception stack
169
170 mov r3, lr
171
172 @
173 @ We are now ready to fill in the remaining blanks on the stack:
174 @
175 @ r2 - sp_svc
176 @ r3 - lr_svc
177 @ r4 - lr_<exception>, already fixed up for correct return/restart
178 @ r5 - spsr_<exception>
179 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
180 @
181 stmia r7, {r2 - r6}
182
183 #ifdef CONFIG_TRACE_IRQFLAGS
184 bl trace_hardirqs_off
185 #endif
186 .endm
187
188 .align 5
189 __dabt_svc:
190 svc_entry
191 dabt_helper
192
193 @
194 @ call main handler
195 @
196 mov r2, sp
197 bl do_DataAbort
198
199 @
200 @ IRQs off again before pulling preserved data off the stack
201 @
202 disable_irq_notrace
203
204 @
205 @ restore SPSR and restart the instruction
206 @
207 ldr r5, [sp, #S_PSR]
208 #ifdef CONFIG_TRACE_IRQFLAGS
209 tst r5, #PSR_I_BIT
210 bleq trace_hardirqs_on
211 tst r5, #PSR_I_BIT
212 blne trace_hardirqs_off
213 #endif
214 svc_exit r5 @ return from exception
215 UNWIND(.fnend )
216 ENDPROC(__dabt_svc)
217
218 .align 5
219 __irq_svc:
220 svc_entry
221 irq_handler
222
223 #ifdef CONFIG_PREEMPT
224 get_thread_info tsk
225 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
226 ldr r0, [tsk, #TI_FLAGS] @ get flags
227 teq r8, #0 @ if preempt count != 0
228 movne r0, #0 @ force flags to 0
229 tst r0, #_TIF_NEED_RESCHED
230 blne svc_preempt
231 #endif
232 ldr r5, [sp, #S_PSR]
233 #ifdef CONFIG_TRACE_IRQFLAGS
234 @ The parent context IRQs must have been enabled to get here in
235 @ the first place, so there's no point checking the PSR I bit.
236 bl trace_hardirqs_on
237 #endif
238 svc_exit r5 @ return from exception
239 UNWIND(.fnend )
240 ENDPROC(__irq_svc)
241
242 .ltorg
243
244 #ifdef CONFIG_PREEMPT
245 svc_preempt:
246 mov r8, lr
247 1: bl preempt_schedule_irq @ irq en/disable is done inside
248 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
249 tst r0, #_TIF_NEED_RESCHED
250 moveq pc, r8 @ go again
251 b 1b
252 #endif
253
254 .align 5
255 __und_svc:
256 #ifdef CONFIG_KPROBES
257 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
258 @ it obviously needs free stack space which then will belong to
259 @ the saved context.
260 svc_entry 64
261 #else
262 svc_entry
263 #endif
264 @
265 @ call emulation code, which returns using r9 if it has emulated
266 @ the instruction, or the more conventional lr if we are to treat
267 @ this as a real undefined instruction
268 @
269 @ r0 - instruction
270 @
271 #ifndef CONFIG_THUMB2_KERNEL
272 ldr r0, [r4, #-4]
273 #else
274 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
275 and r9, r0, #0xf800
276 cmp r9, #0xe800 @ 32-bit instruction if xx >= 0
277 ldrhhs r9, [r4] @ bottom 16 bits
278 orrhs r0, r9, r0, lsl #16
279 #endif
280 adr r9, BSYM(1f)
281 mov r2, r4
282 bl call_fpe
283
284 mov r0, sp @ struct pt_regs *regs
285 bl do_undefinstr
286
287 @
288 @ IRQs off again before pulling preserved data off the stack
289 @
290 1: disable_irq_notrace
291
292 @
293 @ restore SPSR and restart the instruction
294 @
295 ldr r5, [sp, #S_PSR] @ Get SVC cpsr
296 #ifdef CONFIG_TRACE_IRQFLAGS
297 tst r5, #PSR_I_BIT
298 bleq trace_hardirqs_on
299 tst r5, #PSR_I_BIT
300 blne trace_hardirqs_off
301 #endif
302 svc_exit r5 @ return from exception
303 UNWIND(.fnend )
304 ENDPROC(__und_svc)
305
306 .align 5
307 __pabt_svc:
308 svc_entry
309 mov r2, sp @ regs
310 pabt_helper
311
312 @
313 @ IRQs off again before pulling preserved data off the stack
314 @
315 disable_irq_notrace
316
317 @
318 @ restore SPSR and restart the instruction
319 @
320 ldr r5, [sp, #S_PSR]
321 #ifdef CONFIG_TRACE_IRQFLAGS
322 tst r5, #PSR_I_BIT
323 bleq trace_hardirqs_on
324 tst r5, #PSR_I_BIT
325 blne trace_hardirqs_off
326 #endif
327 svc_exit r5 @ return from exception
328 UNWIND(.fnend )
329 ENDPROC(__pabt_svc)
330
331 .align 5
332 .LCcralign:
333 .word cr_alignment
334 #ifdef MULTI_DABORT
335 .LCprocfns:
336 .word processor
337 #endif
338 .LCfp:
339 .word fp_enter
340
341 /*
342 * User mode handlers
343 *
344 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
345 */
346
347 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
348 #error "sizeof(struct pt_regs) must be a multiple of 8"
349 #endif
350
351 .macro usr_entry
352 UNWIND(.fnstart )
353 UNWIND(.cantunwind ) @ don't unwind the user space
354 sub sp, sp, #S_FRAME_SIZE
355 ARM( stmib sp, {r1 - r12} )
356 THUMB( stmia sp, {r0 - r12} )
357
358 ldmia r0, {r3 - r5}
359 add r0, sp, #S_PC @ here for interlock avoidance
360 mov r6, #-1 @ "" "" "" ""
361
362 str r3, [sp] @ save the "real" r0 copied
363 @ from the exception stack
364
365 @
366 @ We are now ready to fill in the remaining blanks on the stack:
367 @
368 @ r4 - lr_<exception>, already fixed up for correct return/restart
369 @ r5 - spsr_<exception>
370 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
371 @
372 @ Also, separately save sp_usr and lr_usr
373 @
374 stmia r0, {r4 - r6}
375 ARM( stmdb r0, {sp, lr}^ )
376 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
377
378 @
379 @ Enable the alignment trap while in kernel mode
380 @
381 alignment_trap r0
382
383 @
384 @ Clear FP to mark the first stack frame
385 @
386 zero_fp
387
388 #ifdef CONFIG_IRQSOFF_TRACER
389 bl trace_hardirqs_off
390 #endif
391 .endm
392
393 .macro kuser_cmpxchg_check
394 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
395 #ifndef CONFIG_MMU
396 #warning "NPTL on non MMU needs fixing"
397 #else
398 @ Make sure our user space atomic helper is restarted
399 @ if it was interrupted in a critical region. Here we
400 @ perform a quick test inline since it should be false
401 @ 99.9999% of the time. The rest is done out of line.
402 cmp r4, #TASK_SIZE
403 blhs kuser_cmpxchg_fixup
404 #endif
405 #endif
406 .endm
407
408 .align 5
409 __dabt_usr:
410 usr_entry
411 kuser_cmpxchg_check
412 dabt_helper
413
414 mov r2, sp
415 adr lr, BSYM(ret_from_exception)
416 b do_DataAbort
417 UNWIND(.fnend )
418 ENDPROC(__dabt_usr)
419
420 .align 5
421 __irq_usr:
422 usr_entry
423 kuser_cmpxchg_check
424 irq_handler
425 get_thread_info tsk
426 mov why, #0
427 b ret_to_user_from_irq
428 UNWIND(.fnend )
429 ENDPROC(__irq_usr)
430
431 .ltorg
432
433 .align 5
434 __und_usr:
435 usr_entry
436
437 mov r2, r4
438 mov r3, r5
439
440 @
441 @ fall through to the emulation code, which returns using r9 if
442 @ it has emulated the instruction, or the more conventional lr
443 @ if we are to treat this as a real undefined instruction
444 @
445 @ r0 - instruction
446 @
447 adr r9, BSYM(ret_from_exception)
448 adr lr, BSYM(__und_usr_unknown)
449 tst r3, #PSR_T_BIT @ Thumb mode?
450 itet eq @ explicit IT needed for the 1f label
451 subeq r4, r2, #4 @ ARM instr at LR - 4
452 subne r4, r2, #2 @ Thumb instr at LR - 2
453 1: ldreqt r0, [r4]
454 #ifdef CONFIG_CPU_ENDIAN_BE8
455 reveq r0, r0 @ little endian instruction
456 #endif
457 beq call_fpe
458 @ Thumb instruction
459 #if __LINUX_ARM_ARCH__ >= 7
460 2:
461 ARM( ldrht r5, [r4], #2 )
462 THUMB( ldrht r5, [r4] )
463 THUMB( add r4, r4, #2 )
464 and r0, r5, #0xf800 @ mask bits 111x x... .... ....
465 cmp r0, #0xe800 @ 32bit instruction if xx != 0
466 blo __und_usr_unknown
467 3: ldrht r0, [r4]
468 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
469 orr r0, r0, r5, lsl #16
470 #else
471 b __und_usr_unknown
472 #endif
473 UNWIND(.fnend )
474 ENDPROC(__und_usr)
475
476 @
477 @ fallthrough to call_fpe
478 @
479
480 /*
481 * The out of line fixup for the ldrt above.
482 */
483 .pushsection .fixup, "ax"
484 4: mov pc, r9
485 .popsection
486 .pushsection __ex_table,"a"
487 .long 1b, 4b
488 #if __LINUX_ARM_ARCH__ >= 7
489 .long 2b, 4b
490 .long 3b, 4b
491 #endif
492 .popsection
493
494 /*
495 * Check whether the instruction is a co-processor instruction.
496 * If yes, we need to call the relevant co-processor handler.
497 *
498 * Note that we don't do a full check here for the co-processor
499 * instructions; all instructions with bit 27 set are well
500 * defined. The only instructions that should fault are the
501 * co-processor instructions. However, we have to watch out
502 * for the ARM6/ARM7 SWI bug.
503 *
504 * NEON is a special case that has to be handled here. Not all
505 * NEON instructions are co-processor instructions, so we have
506 * to make a special case of checking for them. Plus, there's
507 * five groups of them, so we have a table of mask/opcode pairs
508 * to check against, and if any match then we branch off into the
509 * NEON handler code.
510 *
511 * Emulators may wish to make use of the following registers:
512 * r0 = instruction opcode.
513 * r2 = PC+4
514 * r9 = normal "successful" return address
515 * r10 = this threads thread_info structure.
516 * lr = unrecognised instruction return address
517 */
518 @
519 @ Fall-through from Thumb-2 __und_usr
520 @
521 #ifdef CONFIG_NEON
522 adr r6, .LCneon_thumb_opcodes
523 b 2f
524 #endif
525 call_fpe:
526 #ifdef CONFIG_NEON
527 adr r6, .LCneon_arm_opcodes
528 2:
529 ldr r7, [r6], #4 @ mask value
530 cmp r7, #0 @ end mask?
531 beq 1f
532 and r8, r0, r7
533 ldr r7, [r6], #4 @ opcode bits matching in mask
534 cmp r8, r7 @ NEON instruction?
535 bne 2b
536 get_thread_info r10
537 mov r7, #1
538 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
539 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
540 b do_vfp @ let VFP handler handle this
541 1:
542 #endif
543 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
544 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
545 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
546 and r8, r0, #0x0f000000 @ mask out op-code bits
547 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
548 #endif
549 moveq pc, lr
550 get_thread_info r10 @ get current thread
551 and r8, r0, #0x00000f00 @ mask out CP number
552 THUMB( lsr r8, r8, #8 )
553 mov r7, #1
554 add r6, r10, #TI_USED_CP
555 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
556 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
557 #ifdef CONFIG_IWMMXT
558 @ Test if we need to give access to iWMMXt coprocessors
559 ldr r5, [r10, #TI_FLAGS]
560 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
561 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
562 bcs iwmmxt_task_enable
563 #endif
564 ARM( add pc, pc, r8, lsr #6 )
565 THUMB( lsl r8, r8, #2 )
566 THUMB( add pc, r8 )
567 nop
568
569 movw_pc lr @ CP#0
570 W(b) do_fpe @ CP#1 (FPE)
571 W(b) do_fpe @ CP#2 (FPE)
572 movw_pc lr @ CP#3
573 #ifdef CONFIG_CRUNCH
574 b crunch_task_enable @ CP#4 (MaverickCrunch)
575 b crunch_task_enable @ CP#5 (MaverickCrunch)
576 b crunch_task_enable @ CP#6 (MaverickCrunch)
577 #else
578 movw_pc lr @ CP#4
579 movw_pc lr @ CP#5
580 movw_pc lr @ CP#6
581 #endif
582 movw_pc lr @ CP#7
583 movw_pc lr @ CP#8
584 movw_pc lr @ CP#9
585 #ifdef CONFIG_VFP
586 W(b) do_vfp @ CP#10 (VFP)
587 W(b) do_vfp @ CP#11 (VFP)
588 #else
589 movw_pc lr @ CP#10 (VFP)
590 movw_pc lr @ CP#11 (VFP)
591 #endif
592 movw_pc lr @ CP#12
593 movw_pc lr @ CP#13
594 movw_pc lr @ CP#14 (Debug)
595 movw_pc lr @ CP#15 (Control)
596
597 #ifdef CONFIG_NEON
598 .align 6
599
600 .LCneon_arm_opcodes:
601 .word 0xfe000000 @ mask
602 .word 0xf2000000 @ opcode
603
604 .word 0xff100000 @ mask
605 .word 0xf4000000 @ opcode
606
607 .word 0x00000000 @ mask
608 .word 0x00000000 @ opcode
609
610 .LCneon_thumb_opcodes:
611 .word 0xef000000 @ mask
612 .word 0xef000000 @ opcode
613
614 .word 0xff100000 @ mask
615 .word 0xf9000000 @ opcode
616
617 .word 0x00000000 @ mask
618 .word 0x00000000 @ opcode
619 #endif
620
621 do_fpe:
622 enable_irq
623 ldr r4, .LCfp
624 add r10, r10, #TI_FPSTATE @ r10 = workspace
625 ldr pc, [r4] @ Call FP module USR entry point
626
627 /*
628 * The FP module is called with these registers set:
629 * r0 = instruction
630 * r2 = PC+4
631 * r9 = normal "successful" return address
632 * r10 = FP workspace
633 * lr = unrecognised FP instruction return address
634 */
635
636 .pushsection .data
637 ENTRY(fp_enter)
638 .word no_fp
639 .popsection
640
641 ENTRY(no_fp)
642 mov pc, lr
643 ENDPROC(no_fp)
644
645 __und_usr_unknown:
646 enable_irq
647 mov r0, sp
648 adr lr, BSYM(ret_from_exception)
649 b do_undefinstr
650 ENDPROC(__und_usr_unknown)
651
652 .align 5
653 __pabt_usr:
654 usr_entry
655 mov r2, sp @ regs
656 pabt_helper
657 UNWIND(.fnend )
658 /* fall through */
659 /*
660 * This is the return code to user mode for abort handlers
661 */
662 ENTRY(ret_from_exception)
663 UNWIND(.fnstart )
664 UNWIND(.cantunwind )
665 get_thread_info tsk
666 mov why, #0
667 b ret_to_user
668 UNWIND(.fnend )
669 ENDPROC(__pabt_usr)
670 ENDPROC(ret_from_exception)
671
672 /*
673 * Register switch for ARMv3 and ARMv4 processors
674 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
675 * previous and next are guaranteed not to be the same.
676 */
677 ENTRY(__switch_to)
678 UNWIND(.fnstart )
679 UNWIND(.cantunwind )
680 add ip, r1, #TI_CPU_SAVE
681 ldr r3, [r2, #TI_TP_VALUE]
682 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
683 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
684 THUMB( str sp, [ip], #4 )
685 THUMB( str lr, [ip], #4 )
686 #ifdef CONFIG_CPU_USE_DOMAINS
687 ldr r6, [r2, #TI_CPU_DOMAIN]
688 #endif
689 set_tls r3, r4, r5
690 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
691 ldr r7, [r2, #TI_TASK]
692 ldr r8, =__stack_chk_guard
693 ldr r7, [r7, #TSK_STACK_CANARY]
694 #endif
695 #ifdef CONFIG_CPU_USE_DOMAINS
696 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
697 #endif
698 mov r5, r0
699 add r4, r2, #TI_CPU_SAVE
700 ldr r0, =thread_notify_head
701 mov r1, #THREAD_NOTIFY_SWITCH
702 bl atomic_notifier_call_chain
703 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
704 str r7, [r8]
705 #endif
706 THUMB( mov ip, r4 )
707 mov r0, r5
708 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
709 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
710 THUMB( ldr sp, [ip], #4 )
711 THUMB( ldr pc, [ip] )
712 UNWIND(.fnend )
713 ENDPROC(__switch_to)
714
715 __INIT
716
717 /*
718 * User helpers.
719 *
720 * These are segment of kernel provided user code reachable from user space
721 * at a fixed address in kernel memory. This is used to provide user space
722 * with some operations which require kernel help because of unimplemented
723 * native feature and/or instructions in many ARM CPUs. The idea is for
724 * this code to be executed directly in user mode for best efficiency but
725 * which is too intimate with the kernel counter part to be left to user
726 * libraries. In fact this code might even differ from one CPU to another
727 * depending on the available instruction set and restrictions like on
728 * SMP systems. In other words, the kernel reserves the right to change
729 * this code as needed without warning. Only the entry points and their
730 * results are guaranteed to be stable.
731 *
732 * Each segment is 32-byte aligned and will be moved to the top of the high
733 * vector page. New segments (if ever needed) must be added in front of
734 * existing ones. This mechanism should be used only for things that are
735 * really small and justified, and not be abused freely.
736 *
737 * User space is expected to implement those things inline when optimizing
738 * for a processor that has the necessary native support, but only if such
739 * resulting binaries are already to be incompatible with earlier ARM
740 * processors due to the use of unsupported instructions other than what
741 * is provided here. In other words don't make binaries unable to run on
742 * earlier processors just for the sake of not using these kernel helpers
743 * if your compiled code is not going to use the new instructions for other
744 * purpose.
745 */
746 THUMB( .arm )
747
748 .macro usr_ret, reg
749 #ifdef CONFIG_ARM_THUMB
750 bx \reg
751 #else
752 mov pc, \reg
753 #endif
754 .endm
755
756 .align 5
757 .globl __kuser_helper_start
758 __kuser_helper_start:
759
760 /*
761 * Reference prototype:
762 *
763 * void __kernel_memory_barrier(void)
764 *
765 * Input:
766 *
767 * lr = return address
768 *
769 * Output:
770 *
771 * none
772 *
773 * Clobbered:
774 *
775 * none
776 *
777 * Definition and user space usage example:
778 *
779 * typedef void (__kernel_dmb_t)(void);
780 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
781 *
782 * Apply any needed memory barrier to preserve consistency with data modified
783 * manually and __kuser_cmpxchg usage.
784 *
785 * This could be used as follows:
786 *
787 * #define __kernel_dmb() \
788 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
789 * : : : "r0", "lr","cc" )
790 */
791
792 __kuser_memory_barrier: @ 0xffff0fa0
793 smp_dmb arm
794 usr_ret lr
795
796 .align 5
797
798 /*
799 * Reference prototype:
800 *
801 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
802 *
803 * Input:
804 *
805 * r0 = oldval
806 * r1 = newval
807 * r2 = ptr
808 * lr = return address
809 *
810 * Output:
811 *
812 * r0 = returned value (zero or non-zero)
813 * C flag = set if r0 == 0, clear if r0 != 0
814 *
815 * Clobbered:
816 *
817 * r3, ip, flags
818 *
819 * Definition and user space usage example:
820 *
821 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
822 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
823 *
824 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
825 * Return zero if *ptr was changed or non-zero if no exchange happened.
826 * The C flag is also set if *ptr was changed to allow for assembly
827 * optimization in the calling code.
828 *
829 * Notes:
830 *
831 * - This routine already includes memory barriers as needed.
832 *
833 * For example, a user space atomic_add implementation could look like this:
834 *
835 * #define atomic_add(ptr, val) \
836 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
837 * register unsigned int __result asm("r1"); \
838 * asm volatile ( \
839 * "1: @ atomic_add\n\t" \
840 * "ldr r0, [r2]\n\t" \
841 * "mov r3, #0xffff0fff\n\t" \
842 * "add lr, pc, #4\n\t" \
843 * "add r1, r0, %2\n\t" \
844 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
845 * "bcc 1b" \
846 * : "=&r" (__result) \
847 * : "r" (__ptr), "rIL" (val) \
848 * : "r0","r3","ip","lr","cc","memory" ); \
849 * __result; })
850 */
851
852 __kuser_cmpxchg: @ 0xffff0fc0
853
854 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
855
856 /*
857 * Poor you. No fast solution possible...
858 * The kernel itself must perform the operation.
859 * A special ghost syscall is used for that (see traps.c).
860 */
861 stmfd sp!, {r7, lr}
862 ldr r7, 1f @ it's 20 bits
863 swi __ARM_NR_cmpxchg
864 ldmfd sp!, {r7, pc}
865 1: .word __ARM_NR_cmpxchg
866
867 #elif __LINUX_ARM_ARCH__ < 6
868
869 #ifdef CONFIG_MMU
870
871 /*
872 * The only thing that can break atomicity in this cmpxchg
873 * implementation is either an IRQ or a data abort exception
874 * causing another process/thread to be scheduled in the middle
875 * of the critical sequence. To prevent this, code is added to
876 * the IRQ and data abort exception handlers to set the pc back
877 * to the beginning of the critical section if it is found to be
878 * within that critical section (see kuser_cmpxchg_fixup).
879 */
880 1: ldr r3, [r2] @ load current val
881 subs r3, r3, r0 @ compare with oldval
882 2: streq r1, [r2] @ store newval if eq
883 rsbs r0, r3, #0 @ set return val and C flag
884 usr_ret lr
885
886 .text
887 kuser_cmpxchg_fixup:
888 @ Called from kuser_cmpxchg_check macro.
889 @ r4 = address of interrupted insn (must be preserved).
890 @ sp = saved regs. r7 and r8 are clobbered.
891 @ 1b = first critical insn, 2b = last critical insn.
892 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
893 mov r7, #0xffff0fff
894 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
895 subs r8, r4, r7
896 rsbcss r8, r8, #(2b - 1b)
897 strcs r7, [sp, #S_PC]
898 mov pc, lr
899 .previous
900
901 #else
902 #warning "NPTL on non MMU needs fixing"
903 mov r0, #-1
904 adds r0, r0, #0
905 usr_ret lr
906 #endif
907
908 #else
909
910 smp_dmb arm
911 1: ldrex r3, [r2]
912 subs r3, r3, r0
913 strexeq r3, r1, [r2]
914 teqeq r3, #1
915 beq 1b
916 rsbs r0, r3, #0
917 /* beware -- each __kuser slot must be 8 instructions max */
918 ALT_SMP(b __kuser_memory_barrier)
919 ALT_UP(usr_ret lr)
920
921 #endif
922
923 .align 5
924
925 /*
926 * Reference prototype:
927 *
928 * int __kernel_get_tls(void)
929 *
930 * Input:
931 *
932 * lr = return address
933 *
934 * Output:
935 *
936 * r0 = TLS value
937 *
938 * Clobbered:
939 *
940 * none
941 *
942 * Definition and user space usage example:
943 *
944 * typedef int (__kernel_get_tls_t)(void);
945 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
946 *
947 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
948 *
949 * This could be used as follows:
950 *
951 * #define __kernel_get_tls() \
952 * ({ register unsigned int __val asm("r0"); \
953 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
954 * : "=r" (__val) : : "lr","cc" ); \
955 * __val; })
956 */
957
958 __kuser_get_tls: @ 0xffff0fe0
959 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
960 usr_ret lr
961 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
962 .rep 4
963 .word 0 @ 0xffff0ff0 software TLS value, then
964 .endr @ pad up to __kuser_helper_version
965
966 /*
967 * Reference declaration:
968 *
969 * extern unsigned int __kernel_helper_version;
970 *
971 * Definition and user space usage example:
972 *
973 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
974 *
975 * User space may read this to determine the curent number of helpers
976 * available.
977 */
978
979 __kuser_helper_version: @ 0xffff0ffc
980 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
981
982 .globl __kuser_helper_end
983 __kuser_helper_end:
984
985 THUMB( .thumb )
986
987 /*
988 * Vector stubs.
989 *
990 * This code is copied to 0xffff0200 so we can use branches in the
991 * vectors, rather than ldr's. Note that this code must not
992 * exceed 0x300 bytes.
993 *
994 * Common stub entry macro:
995 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
996 *
997 * SP points to a minimal amount of processor-private memory, the address
998 * of which is copied into r0 for the mode specific abort handler.
999 */
1000 .macro vector_stub, name, mode, correction=0
1001 .align 5
1002
1003 vector_\name:
1004 .if \correction
1005 sub lr, lr, #\correction
1006 .endif
1007
1008 @
1009 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1010 @ (parent CPSR)
1011 @
1012 stmia sp, {r0, lr} @ save r0, lr
1013 mrs lr, spsr
1014 str lr, [sp, #8] @ save spsr
1015
1016 @
1017 @ Prepare for SVC32 mode. IRQs remain disabled.
1018 @
1019 mrs r0, cpsr
1020 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1021 msr spsr_cxsf, r0
1022
1023 @
1024 @ the branch table must immediately follow this code
1025 @
1026 and lr, lr, #0x0f
1027 THUMB( adr r0, 1f )
1028 THUMB( ldr lr, [r0, lr, lsl #2] )
1029 mov r0, sp
1030 ARM( ldr lr, [pc, lr, lsl #2] )
1031 movs pc, lr @ branch to handler in SVC mode
1032 ENDPROC(vector_\name)
1033
1034 .align 2
1035 @ handler addresses follow this label
1036 1:
1037 .endm
1038
1039 .globl __stubs_start
1040 __stubs_start:
1041 /*
1042 * Interrupt dispatcher
1043 */
1044 vector_stub irq, IRQ_MODE, 4
1045
1046 .long __irq_usr @ 0 (USR_26 / USR_32)
1047 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1048 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1049 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1050 .long __irq_invalid @ 4
1051 .long __irq_invalid @ 5
1052 .long __irq_invalid @ 6
1053 .long __irq_invalid @ 7
1054 .long __irq_invalid @ 8
1055 .long __irq_invalid @ 9
1056 .long __irq_invalid @ a
1057 .long __irq_invalid @ b
1058 .long __irq_invalid @ c
1059 .long __irq_invalid @ d
1060 .long __irq_invalid @ e
1061 .long __irq_invalid @ f
1062
1063 /*
1064 * Data abort dispatcher
1065 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1066 */
1067 vector_stub dabt, ABT_MODE, 8
1068
1069 .long __dabt_usr @ 0 (USR_26 / USR_32)
1070 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1071 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1072 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1073 .long __dabt_invalid @ 4
1074 .long __dabt_invalid @ 5
1075 .long __dabt_invalid @ 6
1076 .long __dabt_invalid @ 7
1077 .long __dabt_invalid @ 8
1078 .long __dabt_invalid @ 9
1079 .long __dabt_invalid @ a
1080 .long __dabt_invalid @ b
1081 .long __dabt_invalid @ c
1082 .long __dabt_invalid @ d
1083 .long __dabt_invalid @ e
1084 .long __dabt_invalid @ f
1085
1086 /*
1087 * Prefetch abort dispatcher
1088 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1089 */
1090 vector_stub pabt, ABT_MODE, 4
1091
1092 .long __pabt_usr @ 0 (USR_26 / USR_32)
1093 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1094 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1095 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1096 .long __pabt_invalid @ 4
1097 .long __pabt_invalid @ 5
1098 .long __pabt_invalid @ 6
1099 .long __pabt_invalid @ 7
1100 .long __pabt_invalid @ 8
1101 .long __pabt_invalid @ 9
1102 .long __pabt_invalid @ a
1103 .long __pabt_invalid @ b
1104 .long __pabt_invalid @ c
1105 .long __pabt_invalid @ d
1106 .long __pabt_invalid @ e
1107 .long __pabt_invalid @ f
1108
1109 /*
1110 * Undef instr entry dispatcher
1111 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1112 */
1113 vector_stub und, UND_MODE
1114
1115 .long __und_usr @ 0 (USR_26 / USR_32)
1116 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1117 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1118 .long __und_svc @ 3 (SVC_26 / SVC_32)
1119 .long __und_invalid @ 4
1120 .long __und_invalid @ 5
1121 .long __und_invalid @ 6
1122 .long __und_invalid @ 7
1123 .long __und_invalid @ 8
1124 .long __und_invalid @ 9
1125 .long __und_invalid @ a
1126 .long __und_invalid @ b
1127 .long __und_invalid @ c
1128 .long __und_invalid @ d
1129 .long __und_invalid @ e
1130 .long __und_invalid @ f
1131
1132 .align 5
1133
1134 /*=============================================================================
1135 * Undefined FIQs
1136 *-----------------------------------------------------------------------------
1137 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1138 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1139 * Basically to switch modes, we *HAVE* to clobber one register... brain
1140 * damage alert! I don't think that we can execute any code in here in any
1141 * other mode than FIQ... Ok you can switch to another mode, but you can't
1142 * get out of that mode without clobbering one register.
1143 */
1144 vector_fiq:
1145 disable_fiq
1146 subs pc, lr, #4
1147
1148 /*=============================================================================
1149 * Address exception handler
1150 *-----------------------------------------------------------------------------
1151 * These aren't too critical.
1152 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1153 */
1154
1155 vector_addrexcptn:
1156 b vector_addrexcptn
1157
1158 /*
1159 * We group all the following data together to optimise
1160 * for CPUs with separate I & D caches.
1161 */
1162 .align 5
1163
1164 .LCvswi:
1165 .word vector_swi
1166
1167 .globl __stubs_end
1168 __stubs_end:
1169
1170 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1171
1172 .globl __vectors_start
1173 __vectors_start:
1174 ARM( swi SYS_ERROR0 )
1175 THUMB( svc #0 )
1176 THUMB( nop )
1177 W(b) vector_und + stubs_offset
1178 W(ldr) pc, .LCvswi + stubs_offset
1179 W(b) vector_pabt + stubs_offset
1180 W(b) vector_dabt + stubs_offset
1181 W(b) vector_addrexcptn + stubs_offset
1182 W(b) vector_irq + stubs_offset
1183 W(b) vector_fiq + stubs_offset
1184
1185 .globl __vectors_end
1186 __vectors_end:
1187
1188 .data
1189
1190 .globl cr_alignment
1191 .globl cr_no_alignment
1192 cr_alignment:
1193 .space 4
1194 cr_no_alignment:
1195 .space 4
1196
1197 #ifdef CONFIG_MULTI_IRQ_HANDLER
1198 .globl handle_arch_irq
1199 handle_arch_irq:
1200 .space 4
1201 #endif
kernel source for telekom puls (alcatel/mediatek)