arch/arm/include/asm/spinlock.h

   1 #ifndef __ASM_SPINLOCK_H
   2 #define __ASM_SPINLOCK_H
   3
   4 #if __LINUX_ARM_ARCH__ < 6
   5 #error SMP not supported on pre-ARMv6 CPUs
   6 #endif
   7
   8 #include <asm/processor.h>
   9
  10 /*
  11  * sev and wfe are ARMv6K extensions.  Uniprocessor ARMv6 may not have the K
  12  * extensions, so when running on UP, we have to patch these instructions away.
  13  */
  14 #define ALT_SMP(smp, up)                                        \
  15         "9998:  " smp "\n"                                      \
  16         "       .pushsection \".alt.smp.init\", \"a\"\n"        \
  17         "       .long   9998b\n"                                \
  18         "       " up "\n"                                       \
  19         "       .popsection\n"
  20
  21 #ifdef CONFIG_THUMB2_KERNEL
  22 #define SEV             ALT_SMP("sev.w", "nop.w")
  23 /*
  24  * For Thumb-2, special care is needed to ensure that the conditional WFE
  25  * instruction really does assemble to exactly 4 bytes (as required by
  26  * the SMP_ON_UP fixup code).   By itself "wfene" might cause the
  27  * assembler to insert a extra (16-bit) IT instruction, depending on the
  28  * presence or absence of neighbouring conditional instructions.
  29  *
  30  * To avoid this unpredictableness, an approprite IT is inserted explicitly:
  31  * the assembler won't change IT instructions which are explicitly present
  32  * in the input.
  33  */
  34 #define WFE(cond)       ALT_SMP(                \
  35         "it " cond "\n\t"                       \
  36         "wfe" cond ".n",                        \
  37                                                 \
  38         "nop.w"                                 \
  39 )
  40 #else
  41 #define SEV             ALT_SMP("sev", "nop")
  42 #define WFE(cond)       ALT_SMP("wfe" cond, "nop")
  43 #endif
  44
  45 static inline void dsb_sev(void)
  46 {
  47 #if __LINUX_ARM_ARCH__ >= 7
  48         __asm__ __volatile__ (
  49                 "dsb\n"
  50                 SEV
  51         );
  52 #else
  53         __asm__ __volatile__ (
  54                 "mcr p15, 0, %0, c7, c10, 4\n"
  55                 SEV
  56                 : : "r" (0)
  57         );
  58 #endif
  59 }
  60
  61 /*
  62  * ARMv6 ticket-based spin-locking.
  63  *
  64  * A memory barrier is required after we get a lock, and before we
  65  * release it, because V6 CPUs are assumed to have weakly ordered
  66  * memory.
  67  */
  68
  69 #define arch_spin_unlock_wait(lock) \
  70         do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
  71
  72 #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
  73
  74 static inline void arch_spin_lock(arch_spinlock_t *lock)
  75 {
  76         unsigned long tmp;
  77         u32 newval;
  78         arch_spinlock_t lockval;
  79
  80         __asm__ __volatile__(
  81 "1:     ldrex   %0, [%3]\n"
  82 "       add     %1, %0, %4\n"
  83 "       strex   %2, %1, [%3]\n"
  84 "       teq     %2, #0\n"
  85 "       bne     1b"
  86         : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
  87         : "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
  88         : "cc");
  89
  90         while (lockval.tickets.next != lockval.tickets.owner) {
  91                 wfe();
  92                 lockval.tickets.owner = ACCESS_ONCE(lock->tickets.owner);
  93         }
  94
  95         smp_mb();
  96 }
  97
  98 static inline int arch_spin_trylock(arch_spinlock_t *lock)
  99 {
 100         unsigned long tmp;
 101         u32 slock;
 102
 103         __asm__ __volatile__(
 104 "       ldrex   %0, [%2]\n"
 105 "       subs    %1, %0, %0, ror #16\n"
 106 "       addeq   %0, %0, %3\n"
 107 "       strexeq %1, %0, [%2]"
 108         : "=&r" (slock), "=&r" (tmp)
 109         : "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
 110         : "cc");
 111
 112         if (tmp == 0) {
 113                 smp_mb();
 114                 return 1;
 115         } else {
 116                 return 0;
 117         }
 118 }
 119
 120 static inline void arch_spin_unlock(arch_spinlock_t *lock)
 121 {
 122         smp_mb();
 123         lock->tickets.owner++;
 124         dsb_sev();
 125 }
 126
 127 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
 128 {
 129         struct __raw_tickets tickets = ACCESS_ONCE(lock->tickets);
 130         return tickets.owner != tickets.next;
 131 }
 132
 133 static inline int arch_spin_is_contended(arch_spinlock_t *lock)
 134 {
 135         struct __raw_tickets tickets = ACCESS_ONCE(lock->tickets);
 136         return (tickets.next - tickets.owner) > 1;
 137 }
 138 #define arch_spin_is_contended  arch_spin_is_contended
 139
 140 /*
 141  * RWLOCKS
 142  *
 143  *
 144  * Write locks are easy - we just set bit 31.  When unlocking, we can
 145  * just write zero since the lock is exclusively held.
 146  */
 147
 148 static inline void arch_write_lock(arch_rwlock_t *rw)
 149 {
 150         unsigned long tmp;
 151
 152         __asm__ __volatile__(
 153 "1:     ldrex   %0, [%1]\n"
 154 "       teq     %0, #0\n"
 155         WFE("ne")
 156 "       strexeq %0, %2, [%1]\n"
 157 "       teq     %0, #0\n"
 158 "       bne     1b"
 159         : "=&r" (tmp)
 160         : "r" (&rw->lock), "r" (0x80000000)
 161         : "cc");
 162
 163         smp_mb();
 164 }
 165
 166 static inline int arch_write_trylock(arch_rwlock_t *rw)
 167 {
 168         unsigned long tmp;
 169
 170         __asm__ __volatile__(
 171 "       ldrex   %0, [%1]\n"
 172 "       teq     %0, #0\n"
 173 "       strexeq %0, %2, [%1]"
 174         : "=&r" (tmp)
 175         : "r" (&rw->lock), "r" (0x80000000)
 176         : "cc");
 177
 178         if (tmp == 0) {
 179                 smp_mb();
 180                 return 1;
 181         } else {
 182                 return 0;
 183         }
 184 }
 185
 186 static inline void arch_write_unlock(arch_rwlock_t *rw)
 187 {
 188         smp_mb();
 189
 190         __asm__ __volatile__(
 191         "str    %1, [%0]\n"
 192         :
 193         : "r" (&rw->lock), "r" (0)
 194         : "cc");
 195
 196         dsb_sev();
 197 }
 198
 199 /* write_can_lock - would write_trylock() succeed? */
 200 #define arch_write_can_lock(x)          ((x)->lock == 0)
 201
 202 /*
 203  * Read locks are a bit more hairy:
 204  *  - Exclusively load the lock value.
 205  *  - Increment it.
 206  *  - Store new lock value if positive, and we still own this location.
 207  *    If the value is negative, we've already failed.
 208  *  - If we failed to store the value, we want a negative result.
 209  *  - If we failed, try again.
 210  * Unlocking is similarly hairy.  We may have multiple read locks
 211  * currently active.  However, we know we won't have any write
 212  * locks.
 213  */
 214 static inline void arch_read_lock(arch_rwlock_t *rw)
 215 {
 216         unsigned long tmp, tmp2;
 217
 218         __asm__ __volatile__(
 219 "1:     ldrex   %0, [%2]\n"
 220 "       adds    %0, %0, #1\n"
 221 "       strexpl %1, %0, [%2]\n"
 222         WFE("mi")
 223 "       rsbpls  %0, %1, #0\n"
 224 "       bmi     1b"
 225         : "=&r" (tmp), "=&r" (tmp2)
 226         : "r" (&rw->lock)
 227         : "cc");
 228
 229         smp_mb();
 230 }
 231
 232 static inline void arch_read_unlock(arch_rwlock_t *rw)
 233 {
 234         unsigned long tmp, tmp2;
 235
 236         smp_mb();
 237
 238         __asm__ __volatile__(
 239 "1:     ldrex   %0, [%2]\n"
 240 "       sub     %0, %0, #1\n"
 241 "       strex   %1, %0, [%2]\n"
 242 "       teq     %1, #0\n"
 243 "       bne     1b"
 244         : "=&r" (tmp), "=&r" (tmp2)
 245         : "r" (&rw->lock)
 246         : "cc");
 247
 248         if (tmp == 0)
 249                 dsb_sev();
 250 }
 251
 252 static inline int arch_read_trylock(arch_rwlock_t *rw)
 253 {
 254         unsigned long tmp, tmp2 = 1;
 255
 256         __asm__ __volatile__(
 257 "       ldrex   %0, [%2]\n"
 258 "       adds    %0, %0, #1\n"
 259 "       strexpl %1, %0, [%2]\n"
 260         : "=&r" (tmp), "+r" (tmp2)
 261         : "r" (&rw->lock)
 262         : "cc");
 263
 264         smp_mb();
 265         return tmp2 == 0;
 266 }
 267
 268 /* read_can_lock - would read_trylock() succeed? */
 269 #define arch_read_can_lock(x)           ((x)->lock < 0x80000000)
 270
 271 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
 272 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
 273
 274 #define arch_spin_relax(lock)   cpu_relax()
 275 #define arch_read_relax(lock)   cpu_relax()
 276 #define arch_write_relax(lock)  cpu_relax()
 277
 278 #endif /* __ASM_SPINLOCK_H */