arch/arm/include/asm/io.h

   1 /*
   2  *  arch/arm/include/asm/io.h
   3  *
   4  *  Copyright (C) 1996-2000 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Modifications:
  11  *  16-Sep-1996 RMK     Inlined the inx/outx functions & optimised for both
  12  *                      constant addresses and variable addresses.
  13  *  04-Dec-1997 RMK     Moved a lot of this stuff to the new architecture
  14  *                      specific IO header files.
  15  *  27-Mar-1999 PJB     Second parameter of memcpy_toio is const..
  16  *  04-Apr-1999 PJB     Added check_signature.
  17  *  12-Dec-1999 RMK     More cleanups
  18  *  18-Jun-2000 RMK     Removed virt_to_* and friends definitions
  19  *  05-Oct-2004 BJD     Moved memory string functions to use void __iomem
  20  */
  21 #ifndef __ASM_ARM_IO_H
  22 #define __ASM_ARM_IO_H
  23
  24 #ifdef __KERNEL__
  25
  26 #include <linux/types.h>
  27 #include <asm/byteorder.h>
  28 #include <asm/memory.h>
  29 #include <asm/system.h>
  30
  31 /*
  32  * ISA I/O bus memory addresses are 1:1 with the physical address.
  33  */
  34 #define isa_virt_to_bus virt_to_phys
  35 #define isa_page_to_bus page_to_phys
  36 #define isa_bus_to_virt phys_to_virt
  37
  38 /*
  39  * Generic IO read/write.  These perform native-endian accesses.  Note
  40  * that some architectures will want to re-define __raw_{read,write}w.
  41  */
  42 extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
  43 extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
  44 extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
  45
  46 extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
  47 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
  48 extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
  49
  50 #define __raw_writeb(v,a)       (__chk_io_ptr(a), *(volatile unsigned char __force  *)(a) = (v))
  51 #define __raw_writew(v,a)       (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))
  52 #define __raw_writel(v,a)       (__chk_io_ptr(a), *(volatile unsigned int __force   *)(a) = (v))
  53
  54 #define __raw_readb(a)          (__chk_io_ptr(a), *(volatile unsigned char __force  *)(a))
  55 #define __raw_readw(a)          (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
  56 #define __raw_readl(a)          (__chk_io_ptr(a), *(volatile unsigned int __force   *)(a))
  57
  58 /*
  59  * Architecture ioremap implementation.
  60  */
  61 #define MT_DEVICE               0
  62 #define MT_DEVICE_NONSHARED     1
  63 #define MT_DEVICE_CACHED        2
  64 #define MT_DEVICE_WC            3
  65 /*
  66  * types 4 onwards can be found in asm/mach/map.h and are undefined
  67  * for ioremap
  68  */
  69
  70 /*
  71  * __arm_ioremap takes CPU physical address.
  72  * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
  73  * The _caller variety takes a __builtin_return_address(0) value for
  74  * /proc/vmalloc to use - and should only be used in non-inline functions.
  75  */
  76 extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long,
  77         size_t, unsigned int, void *);
  78 extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int,
  79         void *);
  80
  81 extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
  82 extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
  83 extern void __iounmap(volatile void __iomem *addr);
  84
  85 /*
  86  * Bad read/write accesses...
  87  */
  88 extern void __readwrite_bug(const char *fn);
  89
  90 /*
  91  * A typesafe __io() helper
  92  */
  93 static inline void __iomem *__typesafe_io(unsigned long addr)
  94 {
  95         return (void __iomem *)addr;
  96 }
  97
  98 /*
  99  * Now, pick up the machine-defined IO definitions
 100  */
 101 #include <mach/io.h>
 102
 103 /*
 104  *  IO port access primitives
 105  *  -------------------------
 106  *
 107  * The ARM doesn't have special IO access instructions; all IO is memory
 108  * mapped.  Note that these are defined to perform little endian accesses
 109  * only.  Their primary purpose is to access PCI and ISA peripherals.
 110  *
 111  * Note that for a big endian machine, this implies that the following
 112  * big endian mode connectivity is in place, as described by numerous
 113  * ARM documents:
 114  *
 115  *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
 116  *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
 117  *
 118  * The machine specific io.h include defines __io to translate an "IO"
 119  * address to a memory address.
 120  *
 121  * Note that we prevent GCC re-ordering or caching values in expressions
 122  * by introducing sequence points into the in*() definitions.  Note that
 123  * __raw_* do not guarantee this behaviour.
 124  *
 125  * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
 126  */
 127 #ifdef __io
 128 #define outb(v,p)               __raw_writeb(v,__io(p))
 129 #define outw(v,p)               __raw_writew((__force __u16) \
 130                                         cpu_to_le16(v),__io(p))
 131 #define outl(v,p)               __raw_writel((__force __u32) \
 132                                         cpu_to_le32(v),__io(p))
 133
 134 #define inb(p)  ({ __u8 __v = __raw_readb(__io(p)); __v; })
 135 #define inw(p)  ({ __u16 __v = le16_to_cpu((__force __le16) \
 136                         __raw_readw(__io(p))); __v; })
 137 #define inl(p)  ({ __u32 __v = le32_to_cpu((__force __le32) \
 138                         __raw_readl(__io(p))); __v; })
 139
 140 #define outsb(p,d,l)            __raw_writesb(__io(p),d,l)
 141 #define outsw(p,d,l)            __raw_writesw(__io(p),d,l)
 142 #define outsl(p,d,l)            __raw_writesl(__io(p),d,l)
 143
 144 #define insb(p,d,l)             __raw_readsb(__io(p),d,l)
 145 #define insw(p,d,l)             __raw_readsw(__io(p),d,l)
 146 #define insl(p,d,l)             __raw_readsl(__io(p),d,l)
 147 #endif
 148
 149 #define outb_p(val,port)        outb((val),(port))
 150 #define outw_p(val,port)        outw((val),(port))
 151 #define outl_p(val,port)        outl((val),(port))
 152 #define inb_p(port)             inb((port))
 153 #define inw_p(port)             inw((port))
 154 #define inl_p(port)             inl((port))
 155
 156 #define outsb_p(port,from,len)  outsb(port,from,len)
 157 #define outsw_p(port,from,len)  outsw(port,from,len)
 158 #define outsl_p(port,from,len)  outsl(port,from,len)
 159 #define insb_p(port,to,len)     insb(port,to,len)
 160 #define insw_p(port,to,len)     insw(port,to,len)
 161 #define insl_p(port,to,len)     insl(port,to,len)
 162
 163 /*
 164  * String version of IO memory access ops:
 165  */
 166 extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
 167 extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
 168 extern void _memset_io(volatile void __iomem *, int, size_t);
 169
 170 #define mmiowb()
 171
 172 /*
 173  *  Memory access primitives
 174  *  ------------------------
 175  *
 176  * These perform PCI memory accesses via an ioremap region.  They don't
 177  * take an address as such, but a cookie.
 178  *
 179  * Again, this are defined to perform little endian accesses.  See the
 180  * IO port primitives for more information.
 181  */
 182 #ifdef __mem_pci
 183 #define readb_relaxed(c) ({ u8  __v = __raw_readb(__mem_pci(c)); __v; })
 184 #define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16) \
 185                                         __raw_readw(__mem_pci(c))); __v; })
 186 #define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32) \
 187                                         __raw_readl(__mem_pci(c))); __v; })
 188
 189 #define writeb_relaxed(v,c)     ((void)__raw_writeb(v,__mem_pci(c)))
 190 #define writew_relaxed(v,c)     ((void)__raw_writew((__force u16) \
 191                                         cpu_to_le16(v),__mem_pci(c)))
 192 #define writel_relaxed(v,c)     ((void)__raw_writel((__force u32) \
 193                                         cpu_to_le32(v),__mem_pci(c)))
 194
 195 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 196 #define readb(c)                ({ u8  __v = readb_relaxed(c); rmb(); __v; })
 197 #define readw(c)                ({ u16 __v = readw_relaxed(c); rmb(); __v; })
 198 #define readl(c)                ({ u32 __v = readl_relaxed(c); rmb(); __v; })
 199
 200 #define writeb(v,c)             ({ wmb(); writeb_relaxed(v,c); })
 201 #define writew(v,c)             ({ wmb(); writew_relaxed(v,c); })
 202 #define writel(v,c)             ({ wmb(); writel_relaxed(v,c); })
 203 #else
 204 #define readb(c)                readb_relaxed(c)
 205 #define readw(c)                readw_relaxed(c)
 206 #define readl(c)                readl_relaxed(c)
 207
 208 #define writeb(v,c)             writeb_relaxed(v,c)
 209 #define writew(v,c)             writew_relaxed(v,c)
 210 #define writel(v,c)             writel_relaxed(v,c)
 211 #endif
 212
 213 #define readsb(p,d,l)           __raw_readsb(__mem_pci(p),d,l)
 214 #define readsw(p,d,l)           __raw_readsw(__mem_pci(p),d,l)
 215 #define readsl(p,d,l)           __raw_readsl(__mem_pci(p),d,l)
 216
 217 #define writesb(p,d,l)          __raw_writesb(__mem_pci(p),d,l)
 218 #define writesw(p,d,l)          __raw_writesw(__mem_pci(p),d,l)
 219 #define writesl(p,d,l)          __raw_writesl(__mem_pci(p),d,l)
 220
 221 #define memset_io(c,v,l)        _memset_io(__mem_pci(c),(v),(l))
 222 #define memcpy_fromio(a,c,l)    _memcpy_fromio((a),__mem_pci(c),(l))
 223 #define memcpy_toio(c,a,l)      _memcpy_toio(__mem_pci(c),(a),(l))
 224
 225 #elif !defined(readb)
 226
 227 #define readb(c)                        (__readwrite_bug("readb"),0)
 228 #define readw(c)                        (__readwrite_bug("readw"),0)
 229 #define readl(c)                        (__readwrite_bug("readl"),0)
 230 #define writeb(v,c)                     __readwrite_bug("writeb")
 231 #define writew(v,c)                     __readwrite_bug("writew")
 232 #define writel(v,c)                     __readwrite_bug("writel")
 233
 234 #define check_signature(io,sig,len)     (0)
 235
 236 #endif  /* __mem_pci */
 237
 238 /*
 239  * ioremap and friends.
 240  *
 241  * ioremap takes a PCI memory address, as specified in
 242  * Documentation/IO-mapping.txt.
 243  *
 244  */
 245 #ifndef __arch_ioremap
 246 #define ioremap(cookie,size)            __arm_ioremap(cookie, size, MT_DEVICE)
 247 #define ioremap_nocache(cookie,size)    __arm_ioremap(cookie, size, MT_DEVICE)
 248 #define ioremap_cached(cookie,size)     __arm_ioremap(cookie, size, MT_DEVICE_CACHED)
 249 #define ioremap_wc(cookie,size)         __arm_ioremap(cookie, size, MT_DEVICE_WC)
 250 #define iounmap(cookie)                 __iounmap(cookie)
 251 #else
 252 #define ioremap(cookie,size)            __arch_ioremap((cookie), (size), MT_DEVICE)
 253 #define ioremap_nocache(cookie,size)    __arch_ioremap((cookie), (size), MT_DEVICE)
 254 #define ioremap_cached(cookie,size)     __arch_ioremap((cookie), (size), MT_DEVICE_CACHED)
 255 #define ioremap_wc(cookie,size)         __arch_ioremap((cookie), (size), MT_DEVICE_WC)
 256 #define iounmap(cookie)                 __arch_iounmap(cookie)
 257 #endif
 258
 259 /*
 260  * io{read,write}{8,16,32} macros
 261  */
 262 #ifndef ioread8
 263 #define ioread8(p)      ({ unsigned int __v = __raw_readb(p); __v; })
 264 #define ioread16(p)     ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __v; })
 265 #define ioread32(p)     ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __v; })
 266
 267 #define iowrite8(v,p)   __raw_writeb(v, p)
 268 #define iowrite16(v,p)  __raw_writew((__force __u16)cpu_to_le16(v), p)
 269 #define iowrite32(v,p)  __raw_writel((__force __u32)cpu_to_le32(v), p)
 270
 271 #define ioread8_rep(p,d,c)      __raw_readsb(p,d,c)
 272 #define ioread16_rep(p,d,c)     __raw_readsw(p,d,c)
 273 #define ioread32_rep(p,d,c)     __raw_readsl(p,d,c)
 274
 275 #define iowrite8_rep(p,s,c)     __raw_writesb(p,s,c)
 276 #define iowrite16_rep(p,s,c)    __raw_writesw(p,s,c)
 277 #define iowrite32_rep(p,s,c)    __raw_writesl(p,s,c)
 278
 279 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
 280 extern void ioport_unmap(void __iomem *addr);
 281 #endif
 282
 283 struct pci_dev;
 284
 285 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen);
 286 extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
 287
 288 /*
 289  * can the hardware map this into one segment or not, given no other
 290  * constraints.
 291  */
 292 #define BIOVEC_MERGEABLE(vec1, vec2)    \
 293         ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
 294
 295 #ifdef CONFIG_MMU
 296 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
 297 extern int valid_phys_addr_range(unsigned long addr, size_t size);
 298 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
 299 #endif
 300
 301 /*
 302  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 303  * access
 304  */
 305 #define xlate_dev_mem_ptr(p)    __va(p)
 306
 307 /*
 308  * Convert a virtual cached pointer to an uncached pointer
 309  */
 310 #define xlate_dev_kmem_ptr(p)   p
 311
 312 /*
 313  * Register ISA memory and port locations for glibc iopl/inb/outb
 314  * emulation.
 315  */
 316 extern void register_isa_ports(unsigned int mmio, unsigned int io,
 317                                unsigned int io_shift);
 318
 319 #endif  /* __KERNEL__ */
 320 #endif  /* __ASM_ARM_IO_H */