arch/arm/boot/dts/tegra30.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 / {
   4         compatible = "nvidia,tegra30";
   5         interrupt-parent = <&intc>;
   6
   7         aliases {
   8                 serial0 = &uarta;
   9                 serial1 = &uartb;
  10                 serial2 = &uartc;
  11                 serial3 = &uartd;
  12                 serial4 = &uarte;
  13         };
  14
  15         host1x {
  16                 compatible = "nvidia,tegra30-host1x", "simple-bus";
  17                 reg = <0x50000000 0x00024000>;
  18                 interrupts = <0 65 0x04   /* mpcore syncpt */
  19                               0 67 0x04>; /* mpcore general */
  20                 clocks = <&tegra_car 28>;
  21
  22                 #address-cells = <1>;
  23                 #size-cells = <1>;
  24
  25                 ranges = <0x54000000 0x54000000 0x04000000>;
  26
  27                 mpe {
  28                         compatible = "nvidia,tegra30-mpe";
  29                         reg = <0x54040000 0x00040000>;
  30                         interrupts = <0 68 0x04>;
  31                         clocks = <&tegra_car 60>;
  32                 };
  33
  34                 vi {
  35                         compatible = "nvidia,tegra30-vi";
  36                         reg = <0x54080000 0x00040000>;
  37                         interrupts = <0 69 0x04>;
  38                         clocks = <&tegra_car 164>;
  39                 };
  40
  41                 epp {
  42                         compatible = "nvidia,tegra30-epp";
  43                         reg = <0x540c0000 0x00040000>;
  44                         interrupts = <0 70 0x04>;
  45                         clocks = <&tegra_car 19>;
  46                 };
  47
  48                 isp {
  49                         compatible = "nvidia,tegra30-isp";
  50                         reg = <0x54100000 0x00040000>;
  51                         interrupts = <0 71 0x04>;
  52                         clocks = <&tegra_car 23>;
  53                 };
  54
  55                 gr2d {
  56                         compatible = "nvidia,tegra30-gr2d";
  57                         reg = <0x54140000 0x00040000>;
  58                         interrupts = <0 72 0x04>;
  59                         clocks = <&tegra_car 21>;
  60                 };
  61
  62                 gr3d {
  63                         compatible = "nvidia,tegra30-gr3d";
  64                         reg = <0x54180000 0x00040000>;
  65                         clocks = <&tegra_car 24 &tegra_car 98>;
  66                         clock-names = "3d", "3d2";
  67                 };
  68
  69                 dc@54200000 {
  70                         compatible = "nvidia,tegra30-dc";
  71                         reg = <0x54200000 0x00040000>;
  72                         interrupts = <0 73 0x04>;
  73                         clocks = <&tegra_car 27>, <&tegra_car 179>;
  74                         clock-names = "disp1", "parent";
  75
  76                         rgb {
  77                                 status = "disabled";
  78                         };
  79                 };
  80
  81                 dc@54240000 {
  82                         compatible = "nvidia,tegra30-dc";
  83                         reg = <0x54240000 0x00040000>;
  84                         interrupts = <0 74 0x04>;
  85                         clocks = <&tegra_car 26>, <&tegra_car 179>;
  86                         clock-names = "disp2", "parent";
  87
  88                         rgb {
  89                                 status = "disabled";
  90                         };
  91                 };
  92
  93                 hdmi {
  94                         compatible = "nvidia,tegra30-hdmi";
  95                         reg = <0x54280000 0x00040000>;
  96                         interrupts = <0 75 0x04>;
  97                         clocks = <&tegra_car 51>, <&tegra_car 189>;
  98                         clock-names = "hdmi", "parent";
  99                         status = "disabled";
 100                 };
 101
 102                 tvo {
 103                         compatible = "nvidia,tegra30-tvo";
 104                         reg = <0x542c0000 0x00040000>;
 105                         interrupts = <0 76 0x04>;
 106                         clocks = <&tegra_car 169>;
 107                         status = "disabled";
 108                 };
 109
 110                 dsi {
 111                         compatible = "nvidia,tegra30-dsi";
 112                         reg = <0x54300000 0x00040000>;
 113                         clocks = <&tegra_car 48>;
 114                         status = "disabled";
 115                 };
 116         };
 117
 118         timer@50004600 {
 119                 compatible = "arm,cortex-a9-twd-timer";
 120                 reg = <0x50040600 0x20>;
 121                 interrupts = <1 13 0xf04>;
 122                 clocks = <&tegra_car 214>;
 123         };
 124
 125         intc: interrupt-controller {
 126                 compatible = "arm,cortex-a9-gic";
 127                 reg = <0x50041000 0x1000
 128                        0x50040100 0x0100>;
 129                 interrupt-controller;
 130                 #interrupt-cells = <3>;
 131         };
 132
 133         cache-controller {
 134                 compatible = "arm,pl310-cache";
 135                 reg = <0x50043000 0x1000>;
 136                 arm,data-latency = <6 6 2>;
 137                 arm,tag-latency = <5 5 2>;
 138                 cache-unified;
 139                 cache-level = <2>;
 140         };
 141
 142         timer@60005000 {
 143                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 144                 reg = <0x60005000 0x400>;
 145                 interrupts = <0 0 0x04
 146                               0 1 0x04
 147                               0 41 0x04
 148                               0 42 0x04
 149                               0 121 0x04
 150                               0 122 0x04>;
 151                 clocks = <&tegra_car 5>;
 152         };
 153
 154         tegra_car: clock {
 155                 compatible = "nvidia,tegra30-car";
 156                 reg = <0x60006000 0x1000>;
 157                 #clock-cells = <1>;
 158         };
 159
 160         apbdma: dma {
 161                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 162                 reg = <0x6000a000 0x1400>;
 163                 interrupts = <0 104 0x04
 164                               0 105 0x04
 165                               0 106 0x04
 166                               0 107 0x04
 167                               0 108 0x04
 168                               0 109 0x04
 169                               0 110 0x04
 170                               0 111 0x04
 171                               0 112 0x04
 172                               0 113 0x04
 173                               0 114 0x04
 174                               0 115 0x04
 175                               0 116 0x04
 176                               0 117 0x04
 177                               0 118 0x04
 178                               0 119 0x04
 179                               0 128 0x04
 180                               0 129 0x04
 181                               0 130 0x04
 182                               0 131 0x04
 183                               0 132 0x04
 184                               0 133 0x04
 185                               0 134 0x04
 186                               0 135 0x04
 187                               0 136 0x04
 188                               0 137 0x04
 189                               0 138 0x04
 190                               0 139 0x04
 191                               0 140 0x04
 192                               0 141 0x04
 193                               0 142 0x04
 194                               0 143 0x04>;
 195                 clocks = <&tegra_car 34>;
 196         };
 197
 198         ahb: ahb {
 199                 compatible = "nvidia,tegra30-ahb";
 200                 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
 201         };
 202
 203         gpio: gpio {
 204                 compatible = "nvidia,tegra30-gpio";
 205                 reg = <0x6000d000 0x1000>;
 206                 interrupts = <0 32 0x04
 207                               0 33 0x04
 208                               0 34 0x04
 209                               0 35 0x04
 210                               0 55 0x04
 211                               0 87 0x04
 212                               0 89 0x04
 213                               0 125 0x04>;
 214                 #gpio-cells = <2>;
 215                 gpio-controller;
 216                 #interrupt-cells = <2>;
 217                 interrupt-controller;
 218         };
 219
 220         pinmux: pinmux {
 221                 compatible = "nvidia,tegra30-pinmux";
 222                 reg = <0x70000868 0xd4    /* Pad control registers */
 223                        0x70003000 0x3e4>; /* Mux registers */
 224         };
 225
 226         /*
 227          * There are two serial driver i.e. 8250 based simple serial
 228          * driver and APB DMA based serial driver for higher baudrate
 229          * and performace. To enable the 8250 based driver, the compatible
 230          * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
 231          * the APB DMA based serial driver, the comptible is
 232          * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
 233          */
 234         uarta: serial@70006000 {
 235                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 236                 reg = <0x70006000 0x40>;
 237                 reg-shift = <2>;
 238                 interrupts = <0 36 0x04>;
 239                 nvidia,dma-request-selector = <&apbdma 8>;
 240                 clocks = <&tegra_car 6>;
 241                 status = "disabled";
 242         };
 243
 244         uartb: serial@70006040 {
 245                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 246                 reg = <0x70006040 0x40>;
 247                 reg-shift = <2>;
 248                 interrupts = <0 37 0x04>;
 249                 nvidia,dma-request-selector = <&apbdma 9>;
 250                 clocks = <&tegra_car 160>;
 251                 status = "disabled";
 252         };
 253
 254         uartc: serial@70006200 {
 255                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 256                 reg = <0x70006200 0x100>;
 257                 reg-shift = <2>;
 258                 interrupts = <0 46 0x04>;
 259                 nvidia,dma-request-selector = <&apbdma 10>;
 260                 clocks = <&tegra_car 55>;
 261                 status = "disabled";
 262         };
 263
 264         uartd: serial@70006300 {
 265                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 266                 reg = <0x70006300 0x100>;
 267                 reg-shift = <2>;
 268                 interrupts = <0 90 0x04>;
 269                 nvidia,dma-request-selector = <&apbdma 19>;
 270                 clocks = <&tegra_car 65>;
 271                 status = "disabled";
 272         };
 273
 274         uarte: serial@70006400 {
 275                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 276                 reg = <0x70006400 0x100>;
 277                 reg-shift = <2>;
 278                 interrupts = <0 91 0x04>;
 279                 nvidia,dma-request-selector = <&apbdma 20>;
 280                 clocks = <&tegra_car 66>;
 281                 status = "disabled";
 282         };
 283
 284         pwm: pwm {
 285                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 286                 reg = <0x7000a000 0x100>;
 287                 #pwm-cells = <2>;
 288                 clocks = <&tegra_car 17>;
 289                 status = "disabled";
 290         };
 291
 292         rtc {
 293                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
 294                 reg = <0x7000e000 0x100>;
 295                 interrupts = <0 2 0x04>;
 296                 clocks = <&tegra_car 4>;
 297         };
 298
 299         i2c@7000c000 {
 300                 compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 301                 reg = <0x7000c000 0x100>;
 302                 interrupts = <0 38 0x04>;
 303                 #address-cells = <1>;
 304                 #size-cells = <0>;
 305                 clocks = <&tegra_car 12>, <&tegra_car 182>;
 306                 clock-names = "div-clk", "fast-clk";
 307                 status = "disabled";
 308         };
 309
 310         i2c@7000c400 {
 311                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 312                 reg = <0x7000c400 0x100>;
 313                 interrupts = <0 84 0x04>;
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316                 clocks = <&tegra_car 54>, <&tegra_car 182>;
 317                 clock-names = "div-clk", "fast-clk";
 318                 status = "disabled";
 319         };
 320
 321         i2c@7000c500 {
 322                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 323                 reg = <0x7000c500 0x100>;
 324                 interrupts = <0 92 0x04>;
 325                 #address-cells = <1>;
 326                 #size-cells = <0>;
 327                 clocks = <&tegra_car 67>, <&tegra_car 182>;
 328                 clock-names = "div-clk", "fast-clk";
 329                 status = "disabled";
 330         };
 331
 332         i2c@7000c700 {
 333                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 334                 reg = <0x7000c700 0x100>;
 335                 interrupts = <0 120 0x04>;
 336                 #address-cells = <1>;
 337                 #size-cells = <0>;
 338                 clocks = <&tegra_car 103>, <&tegra_car 182>;
 339                 clock-names = "div-clk", "fast-clk";
 340                 status = "disabled";
 341         };
 342
 343         i2c@7000d000 {
 344                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 345                 reg = <0x7000d000 0x100>;
 346                 interrupts = <0 53 0x04>;
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 clocks = <&tegra_car 47>, <&tegra_car 182>;
 350                 clock-names = "div-clk", "fast-clk";
 351                 status = "disabled";
 352         };
 353
 354         spi@7000d400 {
 355                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 356                 reg = <0x7000d400 0x200>;
 357                 interrupts = <0 59 0x04>;
 358                 nvidia,dma-request-selector = <&apbdma 15>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 clocks = <&tegra_car 41>;
 362                 status = "disabled";
 363         };
 364
 365         spi@7000d600 {
 366                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 367                 reg = <0x7000d600 0x200>;
 368                 interrupts = <0 82 0x04>;
 369                 nvidia,dma-request-selector = <&apbdma 16>;
 370                 #address-cells = <1>;
 371                 #size-cells = <0>;
 372                 clocks = <&tegra_car 44>;
 373                 status = "disabled";
 374         };
 375
 376         spi@7000d800 {
 377                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 378                 reg = <0x7000d800 0x200>;
 379                 interrupts = <0 83 0x04>;
 380                 nvidia,dma-request-selector = <&apbdma 17>;
 381                 #address-cells = <1>;
 382                 #size-cells = <0>;
 383                 clocks = <&tegra_car 46>;
 384                 status = "disabled";
 385         };
 386
 387         spi@7000da00 {
 388                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 389                 reg = <0x7000da00 0x200>;
 390                 interrupts = <0 93 0x04>;
 391                 nvidia,dma-request-selector = <&apbdma 18>;
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394                 clocks = <&tegra_car 68>;
 395                 status = "disabled";
 396         };
 397
 398         spi@7000dc00 {
 399                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 400                 reg = <0x7000dc00 0x200>;
 401                 interrupts = <0 94 0x04>;
 402                 nvidia,dma-request-selector = <&apbdma 27>;
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 clocks = <&tegra_car 104>;
 406                 status = "disabled";
 407         };
 408
 409         spi@7000de00 {
 410                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 411                 reg = <0x7000de00 0x200>;
 412                 interrupts = <0 79 0x04>;
 413                 nvidia,dma-request-selector = <&apbdma 28>;
 414                 #address-cells = <1>;
 415                 #size-cells = <0>;
 416                 clocks = <&tegra_car 105>;
 417                 status = "disabled";
 418         };
 419
 420         kbc {
 421                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
 422                 reg = <0x7000e200 0x100>;
 423                 interrupts = <0 85 0x04>;
 424                 clocks = <&tegra_car 36>;
 425                 status = "disabled";
 426         };
 427
 428         pmc {
 429                 compatible = "nvidia,tegra30-pmc";
 430                 reg = <0x7000e400 0x400>;
 431                 clocks = <&tegra_car 218>, <&clk32k_in>;
 432                 clock-names = "pclk", "clk32k_in";
 433         };
 434
 435         memory-controller {
 436                 compatible = "nvidia,tegra30-mc";
 437                 reg = <0x7000f000 0x010
 438                        0x7000f03c 0x1b4
 439                        0x7000f200 0x028
 440                        0x7000f284 0x17c>;
 441                 interrupts = <0 77 0x04>;
 442         };
 443
 444         iommu {
 445                 compatible = "nvidia,tegra30-smmu";
 446                 reg = <0x7000f010 0x02c
 447                        0x7000f1f0 0x010
 448                        0x7000f228 0x05c>;
 449                 nvidia,#asids = <4>;            /* # of ASIDs */
 450                 dma-window = <0 0x40000000>;    /* IOVA start & length */
 451                 nvidia,ahb = <&ahb>;
 452         };
 453
 454         ahub {
 455                 compatible = "nvidia,tegra30-ahub";
 456                 reg = <0x70080000 0x200
 457                        0x70080200 0x100>;
 458                 interrupts = <0 103 0x04>;
 459                 nvidia,dma-request-selector = <&apbdma 1>;
 460                 clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
 461                          <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
 462                          <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
 463                          <&tegra_car 110>, <&tegra_car 162>;
 464                 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 465                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 466                               "spdif_in";
 467                 ranges;
 468                 #address-cells = <1>;
 469                 #size-cells = <1>;
 470
 471                 tegra_i2s0: i2s@70080300 {
 472                         compatible = "nvidia,tegra30-i2s";
 473                         reg = <0x70080300 0x100>;
 474                         nvidia,ahub-cif-ids = <4 4>;
 475                         clocks = <&tegra_car 30>;
 476                         status = "disabled";
 477                 };
 478
 479                 tegra_i2s1: i2s@70080400 {
 480                         compatible = "nvidia,tegra30-i2s";
 481                         reg = <0x70080400 0x100>;
 482                         nvidia,ahub-cif-ids = <5 5>;
 483                         clocks = <&tegra_car 11>;
 484                         status = "disabled";
 485                 };
 486
 487                 tegra_i2s2: i2s@70080500 {
 488                         compatible = "nvidia,tegra30-i2s";
 489                         reg = <0x70080500 0x100>;
 490                         nvidia,ahub-cif-ids = <6 6>;
 491                         clocks = <&tegra_car 18>;
 492                         status = "disabled";
 493                 };
 494
 495                 tegra_i2s3: i2s@70080600 {
 496                         compatible = "nvidia,tegra30-i2s";
 497                         reg = <0x70080600 0x100>;
 498                         nvidia,ahub-cif-ids = <7 7>;
 499                         clocks = <&tegra_car 101>;
 500                         status = "disabled";
 501                 };
 502
 503                 tegra_i2s4: i2s@70080700 {
 504                         compatible = "nvidia,tegra30-i2s";
 505                         reg = <0x70080700 0x100>;
 506                         nvidia,ahub-cif-ids = <8 8>;
 507                         clocks = <&tegra_car 102>;
 508                         status = "disabled";
 509                 };
 510         };
 511
 512         sdhci@78000000 {
 513                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 514                 reg = <0x78000000 0x200>;
 515                 interrupts = <0 14 0x04>;
 516                 clocks = <&tegra_car 14>;
 517                 status = "disabled";
 518         };
 519
 520         sdhci@78000200 {
 521                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 522                 reg = <0x78000200 0x200>;
 523                 interrupts = <0 15 0x04>;
 524                 clocks = <&tegra_car 9>;
 525                 status = "disabled";
 526         };
 527
 528         sdhci@78000400 {
 529                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 530                 reg = <0x78000400 0x200>;
 531                 interrupts = <0 19 0x04>;
 532                 clocks = <&tegra_car 69>;
 533                 status = "disabled";
 534         };
 535
 536         sdhci@78000600 {
 537                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 538                 reg = <0x78000600 0x200>;
 539                 interrupts = <0 31 0x04>;
 540                 clocks = <&tegra_car 15>;
 541                 status = "disabled";
 542         };
 543
 544         cpus {
 545                 #address-cells = <1>;
 546                 #size-cells = <0>;
 547
 548                 cpu@0 {
 549                         device_type = "cpu";
 550                         compatible = "arm,cortex-a9";
 551                         reg = <0>;
 552                 };
 553
 554                 cpu@1 {
 555                         device_type = "cpu";
 556                         compatible = "arm,cortex-a9";
 557                         reg = <1>;
 558                 };
 559
 560                 cpu@2 {
 561                         device_type = "cpu";
 562                         compatible = "arm,cortex-a9";
 563                         reg = <2>;
 564                 };
 565
 566                 cpu@3 {
 567                         device_type = "cpu";
 568                         compatible = "arm,cortex-a9";
 569                         reg = <3>;
 570                 };
 571         };
 572
 573         pmu {
 574                 compatible = "arm,cortex-a9-pmu";
 575                 interrupts = <0 144 0x04
 576                               0 145 0x04
 577                               0 146 0x04
 578                               0 147 0x04>;
 579         };
 580 };