arch/arm/boot/dts/sun4i-a10.dtsi

   1 /*
   2  * Copyright 2012 Stefan Roese
   3  * Stefan Roese <sr@denx.de>
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         interrupt-parent = <&intc>;
  17
  18         cpus {
  19                 cpu@0 {
  20                         compatible = "arm,cortex-a8";
  21                 };
  22         };
  23
  24         memory {
  25                 reg = <0x40000000 0x80000000>;
  26         };
  27
  28         clocks {
  29                 #address-cells = <1>;
  30                 #size-cells = <1>;
  31                 ranges;
  32
  33                 /*
  34                  * This is a dummy clock, to be used as placeholder on
  35                  * other mux clocks when a specific parent clock is not
  36                  * yet implemented. It should be dropped when the driver
  37                  * is complete.
  38                  */
  39                 dummy: dummy {
  40                         #clock-cells = <0>;
  41                         compatible = "fixed-clock";
  42                         clock-frequency = <0>;
  43                 };
  44
  45                 osc24M: osc24M@01c20050 {
  46                         #clock-cells = <0>;
  47                         compatible = "allwinner,sun4i-osc-clk";
  48                         reg = <0x01c20050 0x4>;
  49                         clock-frequency = <24000000>;
  50                 };
  51
  52                 osc32k: osc32k {
  53                         #clock-cells = <0>;
  54                         compatible = "fixed-clock";
  55                         clock-frequency = <32768>;
  56                 };
  57
  58                 pll1: pll1@01c20000 {
  59                         #clock-cells = <0>;
  60                         compatible = "allwinner,sun4i-pll1-clk";
  61                         reg = <0x01c20000 0x4>;
  62                         clocks = <&osc24M>;
  63                 };
  64
  65                 /* dummy is 200M */
  66                 cpu: cpu@01c20054 {
  67                         #clock-cells = <0>;
  68                         compatible = "allwinner,sun4i-cpu-clk";
  69                         reg = <0x01c20054 0x4>;
  70                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
  71                 };
  72
  73                 axi: axi@01c20054 {
  74                         #clock-cells = <0>;
  75                         compatible = "allwinner,sun4i-axi-clk";
  76                         reg = <0x01c20054 0x4>;
  77                         clocks = <&cpu>;
  78                 };
  79
  80                 axi_gates: axi_gates@01c2005c {
  81                         #clock-cells = <1>;
  82                         compatible = "allwinner,sun4i-axi-gates-clk";
  83                         reg = <0x01c2005c 0x4>;
  84                         clocks = <&axi>;
  85                         clock-output-names = "axi_dram";
  86                 };
  87
  88                 ahb: ahb@01c20054 {
  89                         #clock-cells = <0>;
  90                         compatible = "allwinner,sun4i-ahb-clk";
  91                         reg = <0x01c20054 0x4>;
  92                         clocks = <&axi>;
  93                 };
  94
  95                 ahb_gates: ahb_gates@01c20060 {
  96                         #clock-cells = <1>;
  97                         compatible = "allwinner,sun4i-ahb-gates-clk";
  98                         reg = <0x01c20060 0x8>;
  99                         clocks = <&ahb>;
 100                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 101                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
 102                                 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
 103                                 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
 104                                 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
 105                                 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
 106                                 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
 107                                 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
 108                                 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
 109                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 110                                 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
 111                 };
 112
 113                 apb0: apb0@01c20054 {
 114                         #clock-cells = <0>;
 115                         compatible = "allwinner,sun4i-apb0-clk";
 116                         reg = <0x01c20054 0x4>;
 117                         clocks = <&ahb>;
 118                 };
 119
 120                 apb0_gates: apb0_gates@01c20068 {
 121                         #clock-cells = <1>;
 122                         compatible = "allwinner,sun4i-apb0-gates-clk";
 123                         reg = <0x01c20068 0x4>;
 124                         clocks = <&apb0>;
 125                         clock-output-names = "apb0_codec", "apb0_spdif",
 126                                 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
 127                                 "apb0_ir1", "apb0_keypad";
 128                 };
 129
 130                 /* dummy is pll62 */
 131                 apb1_mux: apb1_mux@01c20058 {
 132                         #clock-cells = <0>;
 133                         compatible = "allwinner,sun4i-apb1-mux-clk";
 134                         reg = <0x01c20058 0x4>;
 135                         clocks = <&osc24M>, <&dummy>, <&osc32k>;
 136                 };
 137
 138                 apb1: apb1@01c20058 {
 139                         #clock-cells = <0>;
 140                         compatible = "allwinner,sun4i-apb1-clk";
 141                         reg = <0x01c20058 0x4>;
 142                         clocks = <&apb1_mux>;
 143                 };
 144
 145                 apb1_gates: apb1_gates@01c2006c {
 146                         #clock-cells = <1>;
 147                         compatible = "allwinner,sun4i-apb1-gates-clk";
 148                         reg = <0x01c2006c 0x4>;
 149                         clocks = <&apb1>;
 150                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 151                                 "apb1_i2c2", "apb1_can", "apb1_scr",
 152                                 "apb1_ps20", "apb1_ps21", "apb1_uart0",
 153                                 "apb1_uart1", "apb1_uart2", "apb1_uart3",
 154                                 "apb1_uart4", "apb1_uart5", "apb1_uart6",
 155                                 "apb1_uart7";
 156                 };
 157         };
 158
 159         soc@01c20000 {
 160                 compatible = "simple-bus";
 161                 #address-cells = <1>;
 162                 #size-cells = <1>;
 163                 reg = <0x01c20000 0x300000>;
 164                 ranges;
 165
 166                 intc: interrupt-controller@01c20400 {
 167                         compatible = "allwinner,sun4i-ic";
 168                         reg = <0x01c20400 0x400>;
 169                         interrupt-controller;
 170                         #interrupt-cells = <1>;
 171                 };
 172
 173                 pio: pinctrl@01c20800 {
 174                         compatible = "allwinner,sun4i-a10-pinctrl";
 175                         reg = <0x01c20800 0x400>;
 176                         clocks = <&apb0_gates 5>;
 177                         gpio-controller;
 178                         #address-cells = <1>;
 179                         #size-cells = <0>;
 180                         #gpio-cells = <3>;
 181
 182                         uart0_pins_a: uart0@0 {
 183                                 allwinner,pins = "PB22", "PB23";
 184                                 allwinner,function = "uart0";
 185                                 allwinner,drive = <0>;
 186                                 allwinner,pull = <0>;
 187                         };
 188
 189                         uart0_pins_b: uart0@1 {
 190                                 allwinner,pins = "PF2", "PF4";
 191                                 allwinner,function = "uart0";
 192                                 allwinner,drive = <0>;
 193                                 allwinner,pull = <0>;
 194                         };
 195
 196                         uart1_pins_a: uart1@0 {
 197                                 allwinner,pins = "PA10", "PA11";
 198                                 allwinner,function = "uart1";
 199                                 allwinner,drive = <0>;
 200                                 allwinner,pull = <0>;
 201                         };
 202                 };
 203
 204                 timer@01c20c00 {
 205                         compatible = "allwinner,sun4i-timer";
 206                         reg = <0x01c20c00 0x90>;
 207                         interrupts = <22>;
 208                         clocks = <&osc24M>;
 209                 };
 210
 211                 wdt: watchdog@01c20c90 {
 212                         compatible = "allwinner,sun4i-wdt";
 213                         reg = <0x01c20c90 0x10>;
 214                 };
 215
 216                 uart0: serial@01c28000 {
 217                         compatible = "snps,dw-apb-uart";
 218                         reg = <0x01c28000 0x400>;
 219                         interrupts = <1>;
 220                         reg-shift = <2>;
 221                         reg-io-width = <4>;
 222                         clocks = <&apb1_gates 16>;
 223                         status = "disabled";
 224                 };
 225
 226                 uart1: serial@01c28400 {
 227                         compatible = "snps,dw-apb-uart";
 228                         reg = <0x01c28400 0x400>;
 229                         interrupts = <2>;
 230                         reg-shift = <2>;
 231                         reg-io-width = <4>;
 232                         clocks = <&apb1_gates 17>;
 233                         status = "disabled";
 234                 };
 235
 236                 uart2: serial@01c28800 {
 237                         compatible = "snps,dw-apb-uart";
 238                         reg = <0x01c28800 0x400>;
 239                         interrupts = <3>;
 240                         reg-shift = <2>;
 241                         reg-io-width = <4>;
 242                         clocks = <&apb1_gates 18>;
 243                         status = "disabled";
 244                 };
 245
 246                 uart3: serial@01c28c00 {
 247                         compatible = "snps,dw-apb-uart";
 248                         reg = <0x01c28c00 0x400>;
 249                         interrupts = <4>;
 250                         reg-shift = <2>;
 251                         reg-io-width = <4>;
 252                         clocks = <&apb1_gates 19>;
 253                         status = "disabled";
 254                 };
 255
 256                 uart4: serial@01c29000 {
 257                         compatible = "snps,dw-apb-uart";
 258                         reg = <0x01c29000 0x400>;
 259                         interrupts = <17>;
 260                         reg-shift = <2>;
 261                         reg-io-width = <4>;
 262                         clocks = <&apb1_gates 20>;
 263                         status = "disabled";
 264                 };
 265
 266                 uart5: serial@01c29400 {
 267                         compatible = "snps,dw-apb-uart";
 268                         reg = <0x01c29400 0x400>;
 269                         interrupts = <18>;
 270                         reg-shift = <2>;
 271                         reg-io-width = <4>;
 272                         clocks = <&apb1_gates 21>;
 273                         status = "disabled";
 274                 };
 275
 276                 uart6: serial@01c29800 {
 277                         compatible = "snps,dw-apb-uart";
 278                         reg = <0x01c29800 0x400>;
 279                         interrupts = <19>;
 280                         reg-shift = <2>;
 281                         reg-io-width = <4>;
 282                         clocks = <&apb1_gates 22>;
 283                         status = "disabled";
 284                 };
 285
 286                 uart7: serial@01c29c00 {
 287                         compatible = "snps,dw-apb-uart";
 288                         reg = <0x01c29c00 0x400>;
 289                         interrupts = <20>;
 290                         reg-shift = <2>;
 291                         reg-io-width = <4>;
 292                         clocks = <&apb1_gates 23>;
 293                         status = "disabled";
 294                 };
 295         };
 296 };