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Merge tag 'for-linus-v3.10-rc3' of git://oss.sgi.com/xfs/xfs
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / boot / dts / sama5d3.dtsi
1 /*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC
4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
11 /include/ "skeleton.dtsi"
12
13 / {
14 model = "Atmel SAMA5D3 family SoC";
15 compatible = "atmel,sama5d3", "atmel,sama5";
16 interrupt-parent = <&aic>;
17
18 aliases {
19 serial0 = &dbgu;
20 serial1 = &usart0;
21 serial2 = &usart1;
22 serial3 = &usart2;
23 serial4 = &usart3;
24 gpio0 = &pioA;
25 gpio1 = &pioB;
26 gpio2 = &pioC;
27 gpio3 = &pioD;
28 gpio4 = &pioE;
29 tcb0 = &tcb0;
30 tcb1 = &tcb1;
31 i2c0 = &i2c0;
32 i2c1 = &i2c1;
33 i2c2 = &i2c2;
34 ssc0 = &ssc0;
35 ssc1 = &ssc1;
36 };
37 cpus {
38 cpu@0 {
39 compatible = "arm,cortex-a5";
40 };
41 };
42
43 memory {
44 reg = <0x20000000 0x8000000>;
45 };
46
47 ahb {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 ranges;
52
53 apb {
54 compatible = "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges;
58
59 mmc0: mmc@f0000000 {
60 compatible = "atmel,hsmci";
61 reg = <0xf0000000 0x600>;
62 interrupts = <21 4 0>;
63 dmas = <&dma0 2 0>;
64 dma-names = "rxtx";
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
67 status = "disabled";
68 #address-cells = <1>;
69 #size-cells = <0>;
70 };
71
72 spi0: spi@f0004000 {
73 #address-cells = <1>;
74 #size-cells = <0>;
75 compatible = "atmel,at91sam9x5-spi";
76 reg = <0xf0004000 0x100>;
77 interrupts = <24 4 3>;
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_spi0>;
80 status = "disabled";
81 };
82
83 ssc0: ssc@f0008000 {
84 compatible = "atmel,at91sam9g45-ssc";
85 reg = <0xf0008000 0x4000>;
86 interrupts = <38 4 4>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
89 status = "disabled";
90 };
91
92 can0: can@f000c000 {
93 compatible = "atmel,at91sam9x5-can";
94 reg = <0xf000c000 0x300>;
95 interrupts = <40 4 3>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_can0_rx_tx>;
98 status = "disabled";
99 };
100
101 tcb0: timer@f0010000 {
102 compatible = "atmel,at91sam9x5-tcb";
103 reg = <0xf0010000 0x100>;
104 interrupts = <26 4 0>;
105 };
106
107 i2c0: i2c@f0014000 {
108 compatible = "atmel,at91sam9x5-i2c";
109 reg = <0xf0014000 0x4000>;
110 interrupts = <18 4 6>;
111 dmas = <&dma0 2 7>,
112 <&dma0 2 8>;
113 dma-names = "tx", "rx";
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_i2c0>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 status = "disabled";
119 };
120
121 i2c1: i2c@f0018000 {
122 compatible = "atmel,at91sam9x5-i2c";
123 reg = <0xf0018000 0x4000>;
124 interrupts = <19 4 6>;
125 dmas = <&dma0 2 9>,
126 <&dma0 2 10>;
127 dma-names = "tx", "rx";
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_i2c1>;
130 #address-cells = <1>;
131 #size-cells = <0>;
132 status = "disabled";
133 };
134
135 usart0: serial@f001c000 {
136 compatible = "atmel,at91sam9260-usart";
137 reg = <0xf001c000 0x100>;
138 interrupts = <12 4 5>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_usart0>;
141 status = "disabled";
142 };
143
144 usart1: serial@f0020000 {
145 compatible = "atmel,at91sam9260-usart";
146 reg = <0xf0020000 0x100>;
147 interrupts = <13 4 5>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_usart1>;
150 status = "disabled";
151 };
152
153 macb0: ethernet@f0028000 {
154 compatible = "cdns,pc302-gem", "cdns,gem";
155 reg = <0xf0028000 0x100>;
156 interrupts = <34 4 3>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
159 status = "disabled";
160 };
161
162 isi: isi@f0034000 {
163 compatible = "atmel,at91sam9g45-isi";
164 reg = <0xf0034000 0x4000>;
165 interrupts = <37 4 5>;
166 status = "disabled";
167 };
168
169 mmc1: mmc@f8000000 {
170 compatible = "atmel,hsmci";
171 reg = <0xf8000000 0x600>;
172 interrupts = <22 4 0>;
173 dmas = <&dma1 2 0>;
174 dma-names = "rxtx";
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
177 status = "disabled";
178 #address-cells = <1>;
179 #size-cells = <0>;
180 };
181
182 mmc2: mmc@f8004000 {
183 compatible = "atmel,hsmci";
184 reg = <0xf8004000 0x600>;
185 interrupts = <23 4 0>;
186 dmas = <&dma1 2 1>;
187 dma-names = "rxtx";
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
190 status = "disabled";
191 #address-cells = <1>;
192 #size-cells = <0>;
193 };
194
195 spi1: spi@f8008000 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 compatible = "atmel,at91sam9x5-spi";
199 reg = <0xf8008000 0x100>;
200 interrupts = <25 4 3>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_spi1>;
203 status = "disabled";
204 };
205
206 ssc1: ssc@f800c000 {
207 compatible = "atmel,at91sam9g45-ssc";
208 reg = <0xf800c000 0x4000>;
209 interrupts = <39 4 4>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
212 status = "disabled";
213 };
214
215 can1: can@f8010000 {
216 compatible = "atmel,at91sam9x5-can";
217 reg = <0xf8010000 0x300>;
218 interrupts = <41 4 3>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_can1_rx_tx>;
221 };
222
223 tcb1: timer@f8014000 {
224 compatible = "atmel,at91sam9x5-tcb";
225 reg = <0xf8014000 0x100>;
226 interrupts = <27 4 0>;
227 };
228
229 adc0: adc@f8018000 {
230 compatible = "atmel,at91sam9260-adc";
231 reg = <0xf8018000 0x100>;
232 interrupts = <29 4 5>;
233 pinctrl-names = "default";
234 pinctrl-0 = <
235 &pinctrl_adc0_adtrg
236 &pinctrl_adc0_ad0
237 &pinctrl_adc0_ad1
238 &pinctrl_adc0_ad2
239 &pinctrl_adc0_ad3
240 &pinctrl_adc0_ad4
241 &pinctrl_adc0_ad5
242 &pinctrl_adc0_ad6
243 &pinctrl_adc0_ad7
244 &pinctrl_adc0_ad8
245 &pinctrl_adc0_ad9
246 &pinctrl_adc0_ad10
247 &pinctrl_adc0_ad11
248 >;
249 atmel,adc-channel-base = <0x50>;
250 atmel,adc-channels-used = <0xfff>;
251 atmel,adc-drdy-mask = <0x1000000>;
252 atmel,adc-num-channels = <12>;
253 atmel,adc-startup-time = <40>;
254 atmel,adc-status-register = <0x30>;
255 atmel,adc-trigger-register = <0xc0>;
256 atmel,adc-use-external;
257 atmel,adc-vref = <3000>;
258 atmel,adc-res = <10 12>;
259 atmel,adc-res-names = "lowres", "highres";
260 status = "disabled";
261
262 trigger@0 {
263 trigger-name = "external-rising";
264 trigger-value = <0x1>;
265 trigger-external;
266 };
267 trigger@1 {
268 trigger-name = "external-falling";
269 trigger-value = <0x2>;
270 trigger-external;
271 };
272 trigger@2 {
273 trigger-name = "external-any";
274 trigger-value = <0x3>;
275 trigger-external;
276 };
277 trigger@3 {
278 trigger-name = "continuous";
279 trigger-value = <0x6>;
280 };
281 };
282
283 tsadcc: tsadcc@f8018000 {
284 compatible = "atmel,at91sam9x5-tsadcc";
285 reg = <0xf8018000 0x4000>;
286 interrupts = <29 4 5>;
287 atmel,tsadcc_clock = <300000>;
288 atmel,filtering_average = <0x03>;
289 atmel,pendet_debounce = <0x08>;
290 atmel,pendet_sensitivity = <0x02>;
291 atmel,ts_sample_hold_time = <0x0a>;
292 status = "disabled";
293 };
294
295 i2c2: i2c@f801c000 {
296 compatible = "atmel,at91sam9x5-i2c";
297 reg = <0xf801c000 0x4000>;
298 interrupts = <20 4 6>;
299 dmas = <&dma1 2 11>,
300 <&dma1 2 12>;
301 dma-names = "tx", "rx";
302 #address-cells = <1>;
303 #size-cells = <0>;
304 status = "disabled";
305 };
306
307 usart2: serial@f8020000 {
308 compatible = "atmel,at91sam9260-usart";
309 reg = <0xf8020000 0x100>;
310 interrupts = <14 4 5>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_usart2>;
313 status = "disabled";
314 };
315
316 usart3: serial@f8024000 {
317 compatible = "atmel,at91sam9260-usart";
318 reg = <0xf8024000 0x100>;
319 interrupts = <15 4 5>;
320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_usart3>;
322 status = "disabled";
323 };
324
325 macb1: ethernet@f802c000 {
326 compatible = "cdns,at32ap7000-macb", "cdns,macb";
327 reg = <0xf802c000 0x100>;
328 interrupts = <35 4 3>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_macb1_rmii>;
331 status = "disabled";
332 };
333
334 sha@f8034000 {
335 compatible = "atmel,sam9g46-sha";
336 reg = <0xf8034000 0x100>;
337 interrupts = <42 4 0>;
338 };
339
340 aes@f8038000 {
341 compatible = "atmel,sam9g46-aes";
342 reg = <0xf8038000 0x100>;
343 interrupts = <43 4 0>;
344 };
345
346 tdes@f803c000 {
347 compatible = "atmel,sam9g46-tdes";
348 reg = <0xf803c000 0x100>;
349 interrupts = <44 4 0>;
350 };
351
352 dma0: dma-controller@ffffe600 {
353 compatible = "atmel,at91sam9g45-dma";
354 reg = <0xffffe600 0x200>;
355 interrupts = <30 4 0>;
356 #dma-cells = <2>;
357 };
358
359 dma1: dma-controller@ffffe800 {
360 compatible = "atmel,at91sam9g45-dma";
361 reg = <0xffffe800 0x200>;
362 interrupts = <31 4 0>;
363 #dma-cells = <2>;
364 };
365
366 ramc0: ramc@ffffea00 {
367 compatible = "atmel,at91sam9g45-ddramc";
368 reg = <0xffffea00 0x200>;
369 };
370
371 dbgu: serial@ffffee00 {
372 compatible = "atmel,at91sam9260-usart";
373 reg = <0xffffee00 0x200>;
374 interrupts = <2 4 7>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_dbgu>;
377 status = "disabled";
378 };
379
380 aic: interrupt-controller@fffff000 {
381 #interrupt-cells = <3>;
382 compatible = "atmel,sama5d3-aic";
383 interrupt-controller;
384 reg = <0xfffff000 0x200>;
385 atmel,external-irqs = <47>;
386 };
387
388 pinctrl@fffff200 {
389 #address-cells = <1>;
390 #size-cells = <1>;
391 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
392 ranges = <0xfffff200 0xfffff200 0xa00>;
393 atmel,mux-mask = <
394 /* A B C */
395 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
396 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
397 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
398 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
399 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
400 >;
401
402 /* shared pinctrl settings */
403 adc0 {
404 pinctrl_adc0_adtrg: adc0_adtrg {
405 atmel,pins =
406 <3 19 0x1 0x0>; /* PD19 periph A ADTRG */
407 };
408 pinctrl_adc0_ad0: adc0_ad0 {
409 atmel,pins =
410 <3 20 0x1 0x0>; /* PD20 periph A AD0 */
411 };
412 pinctrl_adc0_ad1: adc0_ad1 {
413 atmel,pins =
414 <3 21 0x1 0x0>; /* PD21 periph A AD1 */
415 };
416 pinctrl_adc0_ad2: adc0_ad2 {
417 atmel,pins =
418 <3 22 0x1 0x0>; /* PD22 periph A AD2 */
419 };
420 pinctrl_adc0_ad3: adc0_ad3 {
421 atmel,pins =
422 <3 23 0x1 0x0>; /* PD23 periph A AD3 */
423 };
424 pinctrl_adc0_ad4: adc0_ad4 {
425 atmel,pins =
426 <3 24 0x1 0x0>; /* PD24 periph A AD4 */
427 };
428 pinctrl_adc0_ad5: adc0_ad5 {
429 atmel,pins =
430 <3 25 0x1 0x0>; /* PD25 periph A AD5 */
431 };
432 pinctrl_adc0_ad6: adc0_ad6 {
433 atmel,pins =
434 <3 26 0x1 0x0>; /* PD26 periph A AD6 */
435 };
436 pinctrl_adc0_ad7: adc0_ad7 {
437 atmel,pins =
438 <3 27 0x1 0x0>; /* PD27 periph A AD7 */
439 };
440 pinctrl_adc0_ad8: adc0_ad8 {
441 atmel,pins =
442 <3 28 0x1 0x0>; /* PD28 periph A AD8 */
443 };
444 pinctrl_adc0_ad9: adc0_ad9 {
445 atmel,pins =
446 <3 29 0x1 0x0>; /* PD29 periph A AD9 */
447 };
448 pinctrl_adc0_ad10: adc0_ad10 {
449 atmel,pins =
450 <3 30 0x1 0x0>; /* PD30 periph A AD10, conflicts with PCK0 */
451 };
452 pinctrl_adc0_ad11: adc0_ad11 {
453 atmel,pins =
454 <3 31 0x1 0x0>; /* PD31 periph A AD11, conflicts with PCK1 */
455 };
456 };
457
458 can0 {
459 pinctrl_can0_rx_tx: can0_rx_tx {
460 atmel,pins =
461 <3 14 0x3 0x0 /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
462 3 15 0x3 0x0>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
463 };
464 };
465
466 can1 {
467 pinctrl_can1_rx_tx: can1_rx_tx {
468 atmel,pins =
469 <1 14 0x2 0x0 /* PB14 periph B RX, conflicts with GCRS */
470 1 15 0x2 0x0>; /* PB15 periph B TX, conflicts with GCOL */
471 };
472 };
473
474 dbgu {
475 pinctrl_dbgu: dbgu-0 {
476 atmel,pins =
477 <1 30 0x1 0x0 /* PB30 periph A */
478 1 31 0x1 0x1>; /* PB31 periph A with pullup */
479 };
480 };
481
482 i2c0 {
483 pinctrl_i2c0: i2c0-0 {
484 atmel,pins =
485 <0 30 0x1 0x0 /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
486 0 31 0x1 0x0>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
487 };
488 };
489
490 i2c1 {
491 pinctrl_i2c1: i2c1-0 {
492 atmel,pins =
493 <2 26 0x2 0x0 /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
494 2 27 0x2 0x0>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
495 };
496 };
497
498 isi {
499 pinctrl_isi: isi-0 {
500 atmel,pins =
501 <0 16 0x3 0x0 /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
502 0 17 0x3 0x0 /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
503 0 18 0x3 0x0 /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
504 0 19 0x3 0x0 /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
505 0 20 0x3 0x0 /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
506 0 21 0x3 0x0 /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
507 0 22 0x3 0x0 /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
508 0 23 0x3 0x0 /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
509 2 30 0x3 0x0 /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
510 0 31 0x3 0x0 /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
511 0 30 0x3 0x0 /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
512 2 29 0x3 0x0 /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
513 2 28 0x3 0x0>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
514 };
515 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
516 atmel,pins =
517 <3 31 0x2 0x0>; /* PD31 periph B ISI_MCK */
518 };
519 };
520
521 lcd {
522 pinctrl_lcd: lcd-0 {
523 atmel,pins =
524 <0 24 0x1 0x0 /* PA24 periph A LCDPWM */
525 0 26 0x1 0x0 /* PA26 periph A LCDVSYNC */
526 0 27 0x1 0x0 /* PA27 periph A LCDHSYNC */
527 0 25 0x1 0x0 /* PA25 periph A LCDDISP */
528 0 29 0x1 0x0 /* PA29 periph A LCDDEN */
529 0 28 0x1 0x0 /* PA28 periph A LCDPCK */
530 0 0 0x1 0x0 /* PA0 periph A LCDD0 pin */
531 0 1 0x1 0x0 /* PA1 periph A LCDD1 pin */
532 0 2 0x1 0x0 /* PA2 periph A LCDD2 pin */
533 0 3 0x1 0x0 /* PA3 periph A LCDD3 pin */
534 0 4 0x1 0x0 /* PA4 periph A LCDD4 pin */
535 0 5 0x1 0x0 /* PA5 periph A LCDD5 pin */
536 0 6 0x1 0x0 /* PA6 periph A LCDD6 pin */
537 0 7 0x1 0x0 /* PA7 periph A LCDD7 pin */
538 0 8 0x1 0x0 /* PA8 periph A LCDD8 pin */
539 0 9 0x1 0x0 /* PA9 periph A LCDD9 pin */
540 0 10 0x1 0x0 /* PA10 periph A LCDD10 pin */
541 0 11 0x1 0x0 /* PA11 periph A LCDD11 pin */
542 0 12 0x1 0x0 /* PA12 periph A LCDD12 pin */
543 0 13 0x1 0x0 /* PA13 periph A LCDD13 pin */
544 0 14 0x1 0x0 /* PA14 periph A LCDD14 pin */
545 0 15 0x1 0x0 /* PA15 periph A LCDD15 pin */
546 2 14 0x3 0x0 /* PC14 periph C LCDD16 pin */
547 2 13 0x3 0x0 /* PC13 periph C LCDD17 pin */
548 2 12 0x3 0x0 /* PC12 periph C LCDD18 pin */
549 2 11 0x3 0x0 /* PC11 periph C LCDD19 pin */
550 2 10 0x3 0x0 /* PC10 periph C LCDD20 pin */
551 2 15 0x3 0x0 /* PC15 periph C LCDD21 pin */
552 4 27 0x3 0x0 /* PE27 periph C LCDD22 pin */
553 4 28 0x3 0x0>; /* PE28 periph C LCDD23 pin */
554 };
555 };
556
557 macb0 {
558 pinctrl_macb0_data_rgmii: macb0_data_rgmii {
559 atmel,pins =
560 <1 0 0x1 0x0 /* PB0 periph A GTX0, conflicts with PWMH0 */
561 1 1 0x1 0x0 /* PB1 periph A GTX1, conflicts with PWML0 */
562 1 2 0x1 0x0 /* PB2 periph A GTX2, conflicts with TK1 */
563 1 3 0x1 0x0 /* PB3 periph A GTX3, conflicts with TF1 */
564 1 4 0x1 0x0 /* PB4 periph A GRX0, conflicts with PWMH1 */
565 1 5 0x1 0x0 /* PB5 periph A GRX1, conflicts with PWML1 */
566 1 6 0x1 0x0 /* PB6 periph A GRX2, conflicts with TD1 */
567 1 7 0x1 0x0>; /* PB7 periph A GRX3, conflicts with RK1 */
568 };
569 pinctrl_macb0_data_gmii: macb0_data_gmii {
570 atmel,pins =
571 <1 19 0x2 0x0 /* PB19 periph B GTX4, conflicts with MCI1_CDA */
572 1 20 0x2 0x0 /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
573 1 21 0x2 0x0 /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
574 1 22 0x2 0x0 /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
575 1 23 0x2 0x0 /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
576 1 24 0x2 0x0 /* PB24 periph B GRX5, conflicts with MCI1_CK */
577 1 25 0x2 0x0 /* PB25 periph B GRX6, conflicts with SCK1 */
578 1 26 0x2 0x0>; /* PB26 periph B GRX7, conflicts with CTS1 */
579 };
580 pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
581 atmel,pins =
582 <1 8 0x1 0x0 /* PB8 periph A GTXCK, conflicts with PWMH2 */
583 1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */
584 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */
585 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */
586 1 16 0x1 0x0 /* PB16 periph A GMDC */
587 1 17 0x1 0x0 /* PB17 periph A GMDIO */
588 1 18 0x1 0x0>; /* PB18 periph A G125CK */
589 };
590 pinctrl_macb0_signal_gmii: macb0_signal_gmii {
591 atmel,pins =
592 <1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */
593 1 10 0x1 0x0 /* PB10 periph A GTXER, conflicts with RF1 */
594 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */
595 1 12 0x1 0x0 /* PB12 periph A GRXDV, conflicts with PWMH3 */
596 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */
597 1 14 0x1 0x0 /* PB14 periph A GCRS, conflicts with CANRX1 */
598 1 15 0x1 0x0 /* PB15 periph A GCOL, conflicts with CANTX1 */
599 1 16 0x1 0x0 /* PB16 periph A GMDC */
600 1 17 0x1 0x0 /* PB17 periph A GMDIO */
601 1 27 0x2 0x0>; /* PB27 periph B G125CKO */
602 };
603
604 };
605
606 macb1 {
607 pinctrl_macb1_rmii: macb1_rmii-0 {
608 atmel,pins =
609 <2 0 0x1 0x0 /* PC0 periph A ETX0, conflicts with TIOA3 */
610 2 1 0x1 0x0 /* PC1 periph A ETX1, conflicts with TIOB3 */
611 2 2 0x1 0x0 /* PC2 periph A ERX0, conflicts with TCLK3 */
612 2 3 0x1 0x0 /* PC3 periph A ERX1, conflicts with TIOA4 */
613 2 4 0x1 0x0 /* PC4 periph A ETXEN, conflicts with TIOB4 */
614 2 5 0x1 0x0 /* PC5 periph A ECRSDV,conflicts with TCLK4 */
615 2 6 0x1 0x0 /* PC6 periph A ERXER, conflicts with TIOA5 */
616 2 7 0x1 0x0 /* PC7 periph A EREFCK, conflicts with TIOB5 */
617 2 8 0x1 0x0 /* PC8 periph A EMDC, conflicts with TCLK5 */
618 2 9 0x1 0x0>; /* PC9 periph A EMDIO */
619 };
620 };
621
622 mmc0 {
623 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
624 atmel,pins =
625 <3 9 0x1 0x0 /* PD9 periph A MCI0_CK */
626 3 0 0x1 0x1 /* PD0 periph A MCI0_CDA with pullup */
627 3 1 0x1 0x1>; /* PD1 periph A MCI0_DA0 with pullup */
628 };
629 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
630 atmel,pins =
631 <3 2 0x1 0x1 /* PD2 periph A MCI0_DA1 with pullup */
632 3 3 0x1 0x1 /* PD3 periph A MCI0_DA2 with pullup */
633 3 4 0x1 0x1>; /* PD4 periph A MCI0_DA3 with pullup */
634 };
635 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
636 atmel,pins =
637 <3 5 0x1 0x1 /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
638 3 6 0x1 0x1 /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
639 3 7 0x1 0x1 /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
640 3 8 0x1 0x1>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
641 };
642 };
643
644 mmc1 {
645 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
646 atmel,pins =
647 <1 24 0x1 0x0 /* PB24 periph A MCI1_CK, conflicts with GRX5 */
648 1 19 0x1 0x1 /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
649 1 20 0x1 0x1>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
650 };
651 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
652 atmel,pins =
653 <1 21 0x1 0x1 /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
654 1 22 0x1 0x1 /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
655 1 23 0x1 0x1>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
656 };
657 };
658
659 mmc2 {
660 pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
661 atmel,pins =
662 <2 15 0x1 0x0 /* PC15 periph A MCI2_CK, conflicts with PCK2 */
663 2 10 0x1 0x1 /* PC10 periph A MCI2_CDA with pullup */
664 2 11 0x1 0x1>; /* PC11 periph A MCI2_DA0 with pullup */
665 };
666 pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
667 atmel,pins =
668 <2 12 0x1 0x0 /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
669 2 13 0x1 0x0 /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
670 2 14 0x1 0x0>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
671 };
672 };
673
674 nand0 {
675 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
676 atmel,pins =
677 <4 21 0x1 0x1 /* PE21 periph A with pullup */
678 4 22 0x1 0x1>; /* PE22 periph A with pullup */
679 };
680 };
681
682 pioA: gpio@fffff200 {
683 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
684 reg = <0xfffff200 0x100>;
685 interrupts = <6 4 1>;
686 #gpio-cells = <2>;
687 gpio-controller;
688 interrupt-controller;
689 #interrupt-cells = <2>;
690 };
691
692 pioB: gpio@fffff400 {
693 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
694 reg = <0xfffff400 0x100>;
695 interrupts = <7 4 1>;
696 #gpio-cells = <2>;
697 gpio-controller;
698 interrupt-controller;
699 #interrupt-cells = <2>;
700 };
701
702 pioC: gpio@fffff600 {
703 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
704 reg = <0xfffff600 0x100>;
705 interrupts = <8 4 1>;
706 #gpio-cells = <2>;
707 gpio-controller;
708 interrupt-controller;
709 #interrupt-cells = <2>;
710 };
711
712 pioD: gpio@fffff800 {
713 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
714 reg = <0xfffff800 0x100>;
715 interrupts = <9 4 1>;
716 #gpio-cells = <2>;
717 gpio-controller;
718 interrupt-controller;
719 #interrupt-cells = <2>;
720 };
721
722 pioE: gpio@fffffa00 {
723 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
724 reg = <0xfffffa00 0x100>;
725 interrupts = <10 4 1>;
726 #gpio-cells = <2>;
727 gpio-controller;
728 interrupt-controller;
729 #interrupt-cells = <2>;
730 };
731
732 spi0 {
733 pinctrl_spi0: spi0-0 {
734 atmel,pins =
735 <3 10 0x1 0x0 /* PD10 periph A SPI0_MISO pin */
736 3 11 0x1 0x0 /* PD11 periph A SPI0_MOSI pin */
737 3 12 0x1 0x0 /* PD12 periph A SPI0_SPCK pin */
738 3 13 0x0 0x0>; /* PD13 GPIO SPI0_NPCS0 pin */
739 };
740 };
741
742 spi1 {
743 pinctrl_spi1: spi1-0 {
744 atmel,pins =
745 <2 22 0x1 0x0 /* PC22 periph A SPI1_MISO pin */
746 2 23 0x1 0x0 /* PC23 periph A SPI1_MOSI pin */
747 2 24 0x1 0x0 /* PC24 periph A SPI1_SPCK pin */
748 2 25 0x0 0x0>; /* PC25 GPIO SPI1_NPCS0 pin */
749 };
750 };
751
752 ssc0 {
753 pinctrl_ssc0_tx: ssc0_tx {
754 atmel,pins =
755 <2 16 0x1 0x0 /* PC16 periph A TK0 */
756 2 17 0x1 0x0 /* PC17 periph A TF0 */
757 2 18 0x1 0x0>; /* PC18 periph A TD0 */
758 };
759
760 pinctrl_ssc0_rx: ssc0_rx {
761 atmel,pins =
762 <2 19 0x1 0x0 /* PC19 periph A RK0 */
763 2 20 0x1 0x0 /* PC20 periph A RF0 */
764 2 21 0x1 0x0>; /* PC21 periph A RD0 */
765 };
766 };
767
768 ssc1 {
769 pinctrl_ssc1_tx: ssc1_tx {
770 atmel,pins =
771 <1 2 0x2 0x0 /* PB2 periph B TK1, conflicts with GTX2 */
772 1 3 0x2 0x0 /* PB3 periph B TF1, conflicts with GTX3 */
773 1 6 0x2 0x0>; /* PB6 periph B TD1, conflicts with TD1 */
774 };
775
776 pinctrl_ssc1_rx: ssc1_rx {
777 atmel,pins =
778 <1 7 0x2 0x0 /* PB7 periph B RK1, conflicts with EREFCK */
779 1 10 0x2 0x0 /* PB10 periph B RF1, conflicts with GTXER */
780 1 11 0x2 0x0>; /* PB11 periph B RD1, conflicts with GRXCK */
781 };
782 };
783
784 uart0 {
785 pinctrl_uart0: uart0-0 {
786 atmel,pins =
787 <2 29 0x1 0x0 /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
788 2 30 0x1 0x1>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
789 };
790 };
791
792 uart1 {
793 pinctrl_uart1: uart1-0 {
794 atmel,pins =
795 <0 30 0x2 0x0 /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
796 0 31 0x2 0x1>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
797 };
798 };
799
800 usart0 {
801 pinctrl_usart0: usart0-0 {
802 atmel,pins =
803 <3 17 0x1 0x0 /* PD17 periph A */
804 3 18 0x1 0x1>; /* PD18 periph A with pullup */
805 };
806
807 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
808 atmel,pins =
809 <3 15 0x1 0x0 /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
810 3 16 0x1 0x0>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
811 };
812 };
813
814 usart1 {
815 pinctrl_usart1: usart1-0 {
816 atmel,pins =
817 <1 28 0x1 0x0 /* PB28 periph A */
818 1 29 0x1 0x1>; /* PB29 periph A with pullup */
819 };
820
821 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
822 atmel,pins =
823 <1 26 0x1 0x0 /* PB26 periph A, conflicts with GRX7 */
824 1 27 0x1 0x0>; /* PB27 periph A, conflicts with G125CKO */
825 };
826 };
827
828 usart2 {
829 pinctrl_usart2: usart2-0 {
830 atmel,pins =
831 <4 25 0x2 0x0 /* PE25 periph B, conflicts with A25 */
832 4 26 0x2 0x1>; /* PE26 periph B with pullup, conflicts NCS0 */
833 };
834
835 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
836 atmel,pins =
837 <4 23 0x2 0x0 /* PE23 periph B, conflicts with A23 */
838 4 24 0x2 0x0>; /* PE24 periph B, conflicts with A24 */
839 };
840 };
841
842 usart3 {
843 pinctrl_usart3: usart3-0 {
844 atmel,pins =
845 <4 18 0x2 0x0 /* PE18 periph B, conflicts with A18 */
846 4 19 0x2 0x1>; /* PE19 periph B with pullup, conflicts with A19 */
847 };
848
849 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
850 atmel,pins =
851 <4 16 0x2 0x0 /* PE16 periph B, conflicts with A16 */
852 4 17 0x2 0x0>; /* PE17 periph B, conflicts with A17 */
853 };
854 };
855 };
856
857 pmc: pmc@fffffc00 {
858 compatible = "atmel,at91rm9200-pmc";
859 reg = <0xfffffc00 0x120>;
860 };
861
862 rstc@fffffe00 {
863 compatible = "atmel,at91sam9g45-rstc";
864 reg = <0xfffffe00 0x10>;
865 };
866
867 pit: timer@fffffe30 {
868 compatible = "atmel,at91sam9260-pit";
869 reg = <0xfffffe30 0xf>;
870 interrupts = <3 4 5>;
871 };
872
873 watchdog@fffffe40 {
874 compatible = "atmel,at91sam9260-wdt";
875 reg = <0xfffffe40 0x10>;
876 status = "disabled";
877 };
878
879 rtc@fffffeb0 {
880 compatible = "atmel,at91rm9200-rtc";
881 reg = <0xfffffeb0 0x30>;
882 interrupts = <1 4 7>;
883 };
884 };
885
886 usb0: gadget@00500000 {
887 #address-cells = <1>;
888 #size-cells = <0>;
889 compatible = "atmel,at91sam9rl-udc";
890 reg = <0x00500000 0x100000
891 0xf8030000 0x4000>;
892 interrupts = <33 4 2>;
893 status = "disabled";
894
895 ep0 {
896 reg = <0>;
897 atmel,fifo-size = <64>;
898 atmel,nb-banks = <1>;
899 };
900
901 ep1 {
902 reg = <1>;
903 atmel,fifo-size = <1024>;
904 atmel,nb-banks = <3>;
905 atmel,can-dma;
906 atmel,can-isoc;
907 };
908
909 ep2 {
910 reg = <2>;
911 atmel,fifo-size = <1024>;
912 atmel,nb-banks = <3>;
913 atmel,can-dma;
914 atmel,can-isoc;
915 };
916
917 ep3 {
918 reg = <3>;
919 atmel,fifo-size = <1024>;
920 atmel,nb-banks = <2>;
921 atmel,can-dma;
922 };
923
924 ep4 {
925 reg = <4>;
926 atmel,fifo-size = <1024>;
927 atmel,nb-banks = <2>;
928 atmel,can-dma;
929 };
930
931 ep5 {
932 reg = <5>;
933 atmel,fifo-size = <1024>;
934 atmel,nb-banks = <2>;
935 atmel,can-dma;
936 };
937
938 ep6 {
939 reg = <6>;
940 atmel,fifo-size = <1024>;
941 atmel,nb-banks = <2>;
942 atmel,can-dma;
943 };
944
945 ep7 {
946 reg = <7>;
947 atmel,fifo-size = <1024>;
948 atmel,nb-banks = <2>;
949 atmel,can-dma;
950 };
951
952 ep8 {
953 reg = <8>;
954 atmel,fifo-size = <1024>;
955 atmel,nb-banks = <2>;
956 };
957
958 ep9 {
959 reg = <9>;
960 atmel,fifo-size = <1024>;
961 atmel,nb-banks = <2>;
962 };
963
964 ep10 {
965 reg = <10>;
966 atmel,fifo-size = <1024>;
967 atmel,nb-banks = <2>;
968 };
969
970 ep11 {
971 reg = <11>;
972 atmel,fifo-size = <1024>;
973 atmel,nb-banks = <2>;
974 };
975
976 ep12 {
977 reg = <12>;
978 atmel,fifo-size = <1024>;
979 atmel,nb-banks = <2>;
980 };
981
982 ep13 {
983 reg = <13>;
984 atmel,fifo-size = <1024>;
985 atmel,nb-banks = <2>;
986 };
987
988 ep14 {
989 reg = <14>;
990 atmel,fifo-size = <1024>;
991 atmel,nb-banks = <2>;
992 };
993
994 ep15 {
995 reg = <15>;
996 atmel,fifo-size = <1024>;
997 atmel,nb-banks = <2>;
998 };
999 };
1000
1001 usb1: ohci@00600000 {
1002 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1003 reg = <0x00600000 0x100000>;
1004 interrupts = <32 4 2>;
1005 status = "disabled";
1006 };
1007
1008 usb2: ehci@00700000 {
1009 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1010 reg = <0x00700000 0x100000>;
1011 interrupts = <32 4 2>;
1012 status = "disabled";
1013 };
1014
1015 nand0: nand@60000000 {
1016 compatible = "atmel,at91rm9200-nand";
1017 #address-cells = <1>;
1018 #size-cells = <1>;
1019 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1020 0xffffc070 0x00000490 /* SMC PMECC regs */
1021 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
1022 0x00100000 0x00100000 /* ROM code */
1023 0x70000000 0x10000000 /* NFC Command Registers */
1024 0xffffc000 0x00000070 /* NFC HSMC regs */
1025 0x00200000 0x00100000 /* NFC SRAM banks */
1026 >;
1027 interrupts = <5 4 6>;
1028 atmel,nand-addr-offset = <21>;
1029 atmel,nand-cmd-offset = <22>;
1030 pinctrl-names = "default";
1031 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
1032 atmel,pmecc-lookup-table-offset = <0x10000 0x18000>;
1033 status = "disabled";
1034 };
1035 };
1036 };
kernel source for telekom puls (alcatel/mediatek)