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x86/irq, trace: Add __irq_entry annotation to x86's platform IRQ handlers
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / arch / arm / boot / dts / qcom-mdm9615.dtsi
1 /*
2 * Device Tree Source for Qualcomm MDM9615 SoC
3 *
4 * Copyright (C) 2016 BayLibre, SAS.
5 * Author : Neil Armstrong <narmstrong@baylibre.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46 /dts-v1/;
47
48 /include/ "skeleton.dtsi"
49
50 #include <dt-bindings/interrupt-controller/arm-gic.h>
51 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
52 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
53 #include <dt-bindings/mfd/qcom-rpm.h>
54 #include <dt-bindings/soc/qcom,gsbi.h>
55
56 / {
57 model = "Qualcomm MDM9615";
58 compatible = "qcom,mdm9615";
59 interrupt-parent = <&intc>;
60
61 cpus {
62 #address-cells = <1>;
63 #size-cells = <0>;
64
65 cpu0: cpu@0 {
66 compatible = "arm,cortex-a5";
67 device_type = "cpu";
68 next-level-cache = <&L2>;
69 };
70 };
71
72 cpu-pmu {
73 compatible = "arm,cortex-a5-pmu";
74 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
75 };
76
77 clocks {
78 cxo_board {
79 compatible = "fixed-clock";
80 #clock-cells = <0>;
81 clock-frequency = <19200000>;
82 };
83 };
84
85 regulators {
86 vsdcc_fixed: vsdcc-regulator {
87 compatible = "regulator-fixed";
88 regulator-name = "SDCC Power";
89 regulator-min-microvolt = <2700000>;
90 regulator-max-microvolt = <2700000>;
91 regulator-always-on;
92 };
93 };
94
95 soc: soc {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 ranges;
99 compatible = "simple-bus";
100
101 L2: l2-cache@2040000 {
102 compatible = "arm,pl310-cache";
103 reg = <0x02040000 0x1000>;
104 arm,data-latency = <2 2 0>;
105 cache-unified;
106 cache-level = <2>;
107 };
108
109 intc: interrupt-controller@2000000 {
110 compatible = "qcom,msm-qgic2";
111 interrupt-controller;
112 #interrupt-cells = <3>;
113 reg = <0x02000000 0x1000>,
114 <0x02002000 0x1000>;
115 };
116
117 timer@200a000 {
118 compatible = "qcom,kpss-timer", "qcom,msm-timer";
119 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
120 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
121 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
122 reg = <0x0200a000 0x100>;
123 clock-frequency = <27000000>,
124 <32768>;
125 cpu-offset = <0x80000>;
126 };
127
128 msmgpio: pinctrl@800000 {
129 compatible = "qcom,mdm9615-pinctrl";
130 gpio-controller;
131 #gpio-cells = <2>;
132 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
133 interrupt-controller;
134 #interrupt-cells = <2>;
135 reg = <0x800000 0x4000>;
136 };
137
138 gcc: clock-controller@900000 {
139 compatible = "qcom,gcc-mdm9615";
140 #clock-cells = <1>;
141 #reset-cells = <1>;
142 reg = <0x900000 0x4000>;
143 };
144
145 lcc: clock-controller@28000000 {
146 compatible = "qcom,lcc-mdm9615";
147 reg = <0x28000000 0x1000>;
148 #clock-cells = <1>;
149 #reset-cells = <1>;
150 };
151
152 l2cc: clock-controller@2011000 {
153 compatible = "syscon";
154 reg = <0x02011000 0x1000>;
155 };
156
157 rng@1a500000 {
158 compatible = "qcom,prng";
159 reg = <0x1a500000 0x200>;
160 clocks = <&gcc PRNG_CLK>;
161 clock-names = "core";
162 assigned-clocks = <&gcc PRNG_CLK>;
163 assigned-clock-rates = <32000000>;
164 };
165
166 gsbi2: gsbi@16100000 {
167 compatible = "qcom,gsbi-v1.0.0";
168 cell-index = <2>;
169 reg = <0x16100000 0x100>;
170 clocks = <&gcc GSBI2_H_CLK>;
171 clock-names = "iface";
172 status = "disabled";
173 #address-cells = <1>;
174 #size-cells = <1>;
175 ranges;
176
177 gsbi2_i2c: i2c@16180000 {
178 compatible = "qcom,i2c-qup-v1.1.1";
179 #address-cells = <1>;
180 #size-cells = <0>;
181 reg = <0x16180000 0x1000>;
182 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
183
184 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
185 clock-names = "core", "iface";
186 status = "disabled";
187 };
188 };
189
190 gsbi3: gsbi@16200000 {
191 compatible = "qcom,gsbi-v1.0.0";
192 cell-index = <3>;
193 reg = <0x16200000 0x100>;
194 clocks = <&gcc GSBI3_H_CLK>;
195 clock-names = "iface";
196 status = "disabled";
197 #address-cells = <1>;
198 #size-cells = <1>;
199 ranges;
200
201 gsbi3_spi: spi@16280000 {
202 compatible = "qcom,spi-qup-v1.1.1";
203 #address-cells = <1>;
204 #size-cells = <0>;
205 reg = <0x16280000 0x1000>;
206 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
207 spi-max-frequency = <24000000>;
208
209 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
210 clock-names = "core", "iface";
211 status = "disabled";
212 };
213 };
214
215 gsbi4: gsbi@16300000 {
216 compatible = "qcom,gsbi-v1.0.0";
217 cell-index = <4>;
218 reg = <0x16300000 0x100>;
219 clocks = <&gcc GSBI4_H_CLK>;
220 clock-names = "iface";
221 status = "disabled";
222 #address-cells = <1>;
223 #size-cells = <1>;
224 ranges;
225
226 syscon-tcsr = <&tcsr>;
227
228 gsbi4_serial: serial@16340000 {
229 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
230 reg = <0x16340000 0x1000>,
231 <0x16300000 0x1000>;
232 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
234 clock-names = "core", "iface";
235 status = "disabled";
236 };
237 };
238
239 gsbi5: gsbi@16400000 {
240 compatible = "qcom,gsbi-v1.0.0";
241 cell-index = <5>;
242 reg = <0x16400000 0x100>;
243 clocks = <&gcc GSBI5_H_CLK>;
244 clock-names = "iface";
245 status = "disabled";
246 #address-cells = <1>;
247 #size-cells = <1>;
248 ranges;
249
250 syscon-tcsr = <&tcsr>;
251
252 gsbi5_i2c: i2c@16480000 {
253 compatible = "qcom,i2c-qup-v1.1.1";
254 #address-cells = <1>;
255 #size-cells = <0>;
256 reg = <0x16480000 0x1000>;
257 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
258
259 /* QUP clock is not initialized, set rate */
260 assigned-clocks = <&gcc GSBI5_QUP_CLK>;
261 assigned-clock-rates = <24000000>;
262
263 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
264 clock-names = "core", "iface";
265 status = "disabled";
266 };
267
268 gsbi5_serial: serial@16440000 {
269 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
270 reg = <0x16440000 0x1000>,
271 <0x16400000 0x1000>;
272 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
274 clock-names = "core", "iface";
275 status = "disabled";
276 };
277 };
278
279 qcom,ssbi@500000 {
280 compatible = "qcom,ssbi";
281 reg = <0x500000 0x1000>;
282 qcom,controller-type = "pmic-arbiter";
283
284 pmicintc: pmic@0 {
285 compatible = "qcom,pm8018", "qcom,pm8921";
286 interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>;
287 #interrupt-cells = <2>;
288 interrupt-controller;
289 #address-cells = <1>;
290 #size-cells = <0>;
291
292 pwrkey@1c {
293 compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey";
294 reg = <0x1c>;
295 interrupt-parent = <&pmicintc>;
296 interrupts = <50 IRQ_TYPE_EDGE_RISING>,
297 <51 IRQ_TYPE_EDGE_RISING>;
298 debounce = <15625>;
299 pull-up;
300 };
301
302 pmicmpp: mpp@50 {
303 compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp";
304 interrupt-parent = <&pmicintc>;
305 interrupts = <24 IRQ_TYPE_NONE>,
306 <25 IRQ_TYPE_NONE>,
307 <26 IRQ_TYPE_NONE>,
308 <27 IRQ_TYPE_NONE>,
309 <28 IRQ_TYPE_NONE>,
310 <29 IRQ_TYPE_NONE>;
311 reg = <0x50>;
312 gpio-controller;
313 #gpio-cells = <2>;
314 };
315
316 rtc@11d {
317 compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc";
318 interrupt-parent = <&pmicintc>;
319 interrupts = <39 IRQ_TYPE_EDGE_RISING>;
320 reg = <0x11d>;
321 allow-set-time;
322 };
323
324 pmicgpio: gpio@150 {
325 compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
326 interrupt-parent = <&pmicintc>;
327 interrupts = <24 IRQ_TYPE_NONE>,
328 <25 IRQ_TYPE_NONE>,
329 <26 IRQ_TYPE_NONE>,
330 <27 IRQ_TYPE_NONE>,
331 <28 IRQ_TYPE_NONE>,
332 <29 IRQ_TYPE_NONE>;
333 gpio-controller;
334 #gpio-cells = <2>;
335 };
336 };
337 };
338
339 sdcc1bam: dma@12182000{
340 compatible = "qcom,bam-v1.3.0";
341 reg = <0x12182000 0x8000>;
342 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&gcc SDC1_H_CLK>;
344 clock-names = "bam_clk";
345 #dma-cells = <1>;
346 qcom,ee = <0>;
347 };
348
349 sdcc2bam: dma@12142000{
350 compatible = "qcom,bam-v1.3.0";
351 reg = <0x12142000 0x8000>;
352 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&gcc SDC2_H_CLK>;
354 clock-names = "bam_clk";
355 #dma-cells = <1>;
356 qcom,ee = <0>;
357 };
358
359 amba {
360 compatible = "arm,amba-bus";
361 #address-cells = <1>;
362 #size-cells = <1>;
363 ranges;
364 sdcc1: sdcc@12180000 {
365 status = "disabled";
366 compatible = "arm,pl18x", "arm,primecell";
367 arm,primecell-periphid = <0x00051180>;
368 reg = <0x12180000 0x2000>;
369 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
370 interrupt-names = "cmd_irq";
371 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
372 clock-names = "mclk", "apb_pclk";
373 bus-width = <8>;
374 max-frequency = <48000000>;
375 cap-sd-highspeed;
376 cap-mmc-highspeed;
377 vmmc-supply = <&vsdcc_fixed>;
378 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
379 dma-names = "tx", "rx";
380 assigned-clocks = <&gcc SDC1_CLK>;
381 assigned-clock-rates = <400000>;
382 };
383
384 sdcc2: sdcc@12140000 {
385 compatible = "arm,pl18x", "arm,primecell";
386 arm,primecell-periphid = <0x00051180>;
387 status = "disabled";
388 reg = <0x12140000 0x2000>;
389 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
390 interrupt-names = "cmd_irq";
391 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
392 clock-names = "mclk", "apb_pclk";
393 bus-width = <4>;
394 cap-sd-highspeed;
395 cap-mmc-highspeed;
396 max-frequency = <48000000>;
397 no-1-8-v;
398 vmmc-supply = <&vsdcc_fixed>;
399 dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
400 dma-names = "tx", "rx";
401 assigned-clocks = <&gcc SDC2_CLK>;
402 assigned-clock-rates = <400000>;
403 };
404 };
405
406 tcsr: syscon@1a400000 {
407 compatible = "qcom,tcsr-mdm9615", "syscon";
408 reg = <0x1a400000 0x100>;
409 };
410
411 rpm: rpm@108000 {
412 compatible = "qcom,rpm-mdm9615";
413 reg = <0x108000 0x1000>;
414
415 qcom,ipc = <&l2cc 0x8 2>;
416
417 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
418 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
419 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
420 interrupt-names = "ack", "err", "wakeup";
421
422 regulators {
423 compatible = "qcom,rpm-pm8018-regulators";
424
425 vin_lvs1-supply = <&pm8018_s3>;
426
427 vdd_l7-supply = <&pm8018_s4>;
428 vdd_l8-supply = <&pm8018_s3>;
429 vdd_l9_l10_l11_l12-supply = <&pm8018_s5>;
430
431 /* Buck SMPS */
432 pm8018_s1: s1 {
433 regulator-min-microvolt = <500000>;
434 regulator-max-microvolt = <1150000>;
435 qcom,switch-mode-frequency = <1600000>;
436 bias-pull-down;
437 };
438
439 pm8018_s2: s2 {
440 regulator-min-microvolt = <1225000>;
441 regulator-max-microvolt = <1300000>;
442 qcom,switch-mode-frequency = <1600000>;
443 bias-pull-down;
444 };
445
446 pm8018_s3: s3 {
447 regulator-always-on;
448 regulator-min-microvolt = <1800000>;
449 regulator-max-microvolt = <1800000>;
450 qcom,switch-mode-frequency = <1600000>;
451 bias-pull-down;
452 };
453
454 pm8018_s4: s4 {
455 regulator-min-microvolt = <2100000>;
456 regulator-max-microvolt = <2200000>;
457 qcom,switch-mode-frequency = <1600000>;
458 bias-pull-down;
459 };
460
461 pm8018_s5: s5 {
462 regulator-always-on;
463 regulator-min-microvolt = <1350000>;
464 regulator-max-microvolt = <1350000>;
465 qcom,switch-mode-frequency = <1600000>;
466 bias-pull-down;
467 };
468
469 /* PMOS LDO */
470 pm8018_l2: l2 {
471 regulator-always-on;
472 regulator-min-microvolt = <1800000>;
473 regulator-max-microvolt = <1800000>;
474 bias-pull-down;
475 };
476
477 pm8018_l3: l3 {
478 regulator-always-on;
479 regulator-min-microvolt = <1800000>;
480 regulator-max-microvolt = <1800000>;
481 bias-pull-down;
482 };
483
484 pm8018_l4: l4 {
485 regulator-min-microvolt = <3300000>;
486 regulator-max-microvolt = <3300000>;
487 bias-pull-down;
488 };
489
490 pm8018_l5: l5 {
491 regulator-min-microvolt = <2850000>;
492 regulator-max-microvolt = <2850000>;
493 bias-pull-down;
494 };
495
496 pm8018_l6: l6 {
497 regulator-min-microvolt = <1800000>;
498 regulator-max-microvolt = <2850000>;
499 bias-pull-down;
500 };
501
502 pm8018_l7: l7 {
503 regulator-min-microvolt = <1850000>;
504 regulator-max-microvolt = <1900000>;
505 bias-pull-down;
506 };
507
508 pm8018_l8: l8 {
509 regulator-min-microvolt = <1200000>;
510 regulator-max-microvolt = <1200000>;
511 bias-pull-down;
512 };
513
514 pm8018_l9: l9 {
515 regulator-min-microvolt = <750000>;
516 regulator-max-microvolt = <1150000>;
517 bias-pull-down;
518 };
519
520 pm8018_l10: l10 {
521 regulator-min-microvolt = <1050000>;
522 regulator-max-microvolt = <1050000>;
523 bias-pull-down;
524 };
525
526 pm8018_l11: l11 {
527 regulator-min-microvolt = <1050000>;
528 regulator-max-microvolt = <1050000>;
529 bias-pull-down;
530 };
531
532 pm8018_l12: l12 {
533 regulator-min-microvolt = <1050000>;
534 regulator-max-microvolt = <1050000>;
535 bias-pull-down;
536 };
537
538 pm8018_l13: l13 {
539 regulator-min-microvolt = <1850000>;
540 regulator-max-microvolt = <2950000>;
541 bias-pull-down;
542 };
543
544 pm8018_l14: l14 {
545 regulator-min-microvolt = <2850000>;
546 regulator-max-microvolt = <2850000>;
547 bias-pull-down;
548 };
549
550 /* Low Voltage Switch */
551 pm8018_lvs1: lvs1 {
552 bias-pull-down;
553 };
554 };
555 };
556 };
557 };