arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 /*
  11  * Carveout for multimedia usecases
  12  * It should be the last 48MB of the first 512MB memory part
  13  * In theory, it should not even exist. That zone should be reserved
  14  * dynamically during the .reserve callback.
  15  */
  16 /memreserve/ 0x9d000000 0x03000000;
  17
  18 /include/ "skeleton.dtsi"
  19
  20 / {
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         compatible = "ti,omap5";
  25         interrupt-parent = <&gic>;
  26
  27         aliases {
  28                 serial0 = &uart1;
  29                 serial1 = &uart2;
  30                 serial2 = &uart3;
  31                 serial3 = &uart4;
  32                 serial4 = &uart5;
  33                 serial5 = &uart6;
  34         };
  35
  36         cpus {
  37                 cpu@0 {
  38                         compatible = "arm,cortex-a15";
  39                 };
  40                 cpu@1 {
  41                         compatible = "arm,cortex-a15";
  42                 };
  43         };
  44
  45         timer {
  46                 compatible = "arm,armv7-timer";
  47                 /* PPI secure/nonsecure IRQ, active low level-sensitive */
  48                 interrupts = <1 13 0x308>,
  49                              <1 14 0x308>,
  50                              <1 11 0x308>,
  51                              <1 10 0x308>;
  52                 clock-frequency = <6144000>;
  53         };
  54
  55         gic: interrupt-controller@48211000 {
  56                 compatible = "arm,cortex-a15-gic";
  57                 interrupt-controller;
  58                 #interrupt-cells = <3>;
  59                 reg = <0x48211000 0x1000>,
  60                       <0x48212000 0x1000>,
  61                       <0x48214000 0x2000>,
  62                       <0x48216000 0x2000>;
  63         };
  64
  65         /*
  66          * The soc node represents the soc top level view. It is uses for IPs
  67          * that are not memory mapped in the MPU view or for the MPU itself.
  68          */
  69         soc {
  70                 compatible = "ti,omap-infra";
  71                 mpu {
  72                         compatible = "ti,omap5-mpu";
  73                         ti,hwmods = "mpu";
  74                 };
  75         };
  76
  77         /*
  78          * XXX: Use a flat representation of the OMAP3 interconnect.
  79          * The real OMAP interconnect network is quite complex.
  80          * Since that will not bring real advantage to represent that in DT for
  81          * the moment, just use a fake OCP bus entry to represent the whole bus
  82          * hierarchy.
  83          */
  84         ocp {
  85                 compatible = "ti,omap4-l3-noc", "simple-bus";
  86                 #address-cells = <1>;
  87                 #size-cells = <1>;
  88                 ranges;
  89                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
  90                 reg = <0x44000000 0x2000>,
  91                       <0x44800000 0x3000>,
  92                       <0x45000000 0x4000>;
  93                 interrupts = <0 9 0x4>,
  94                              <0 10 0x4>;
  95
  96                 counter32k: counter@4ae04000 {
  97                         compatible = "ti,omap-counter32k";
  98                         reg = <0x4ae04000 0x40>;
  99                         ti,hwmods = "counter_32k";
 100                 };
 101
 102                 omap5_pmx_core: pinmux@4a002840 {
 103                         compatible = "ti,omap4-padconf", "pinctrl-single";
 104                         reg = <0x4a002840 0x01b6>;
 105                         #address-cells = <1>;
 106                         #size-cells = <0>;
 107                         pinctrl-single,register-width = <16>;
 108                         pinctrl-single,function-mask = <0x7fff>;
 109                 };
 110                 omap5_pmx_wkup: pinmux@4ae0c840 {
 111                         compatible = "ti,omap4-padconf", "pinctrl-single";
 112                         reg = <0x4ae0c840 0x0038>;
 113                         #address-cells = <1>;
 114                         #size-cells = <0>;
 115                         pinctrl-single,register-width = <16>;
 116                         pinctrl-single,function-mask = <0x7fff>;
 117                 };
 118
 119                 sdma: dma-controller@4a056000 {
 120                         compatible = "ti,omap4430-sdma";
 121                         reg = <0x4a056000 0x1000>;
 122                         interrupts = <0 12 0x4>,
 123                                      <0 13 0x4>,
 124                                      <0 14 0x4>,
 125                                      <0 15 0x4>;
 126                         #dma-cells = <1>;
 127                         #dma-channels = <32>;
 128                         #dma-requests = <127>;
 129                 };
 130
 131                 gpio1: gpio@4ae10000 {
 132                         compatible = "ti,omap4-gpio";
 133                         reg = <0x4ae10000 0x200>;
 134                         interrupts = <0 29 0x4>;
 135                         ti,hwmods = "gpio1";
 136                         gpio-controller;
 137                         #gpio-cells = <2>;
 138                         interrupt-controller;
 139                         #interrupt-cells = <2>;
 140                 };
 141
 142                 gpio2: gpio@48055000 {
 143                         compatible = "ti,omap4-gpio";
 144                         reg = <0x48055000 0x200>;
 145                         interrupts = <0 30 0x4>;
 146                         ti,hwmods = "gpio2";
 147                         gpio-controller;
 148                         #gpio-cells = <2>;
 149                         interrupt-controller;
 150                         #interrupt-cells = <2>;
 151                 };
 152
 153                 gpio3: gpio@48057000 {
 154                         compatible = "ti,omap4-gpio";
 155                         reg = <0x48057000 0x200>;
 156                         interrupts = <0 31 0x4>;
 157                         ti,hwmods = "gpio3";
 158                         gpio-controller;
 159                         #gpio-cells = <2>;
 160                         interrupt-controller;
 161                         #interrupt-cells = <2>;
 162                 };
 163
 164                 gpio4: gpio@48059000 {
 165                         compatible = "ti,omap4-gpio";
 166                         reg = <0x48059000 0x200>;
 167                         interrupts = <0 32 0x4>;
 168                         ti,hwmods = "gpio4";
 169                         gpio-controller;
 170                         #gpio-cells = <2>;
 171                         interrupt-controller;
 172                         #interrupt-cells = <2>;
 173                 };
 174
 175                 gpio5: gpio@4805b000 {
 176                         compatible = "ti,omap4-gpio";
 177                         reg = <0x4805b000 0x200>;
 178                         interrupts = <0 33 0x4>;
 179                         ti,hwmods = "gpio5";
 180                         gpio-controller;
 181                         #gpio-cells = <2>;
 182                         interrupt-controller;
 183                         #interrupt-cells = <2>;
 184                 };
 185
 186                 gpio6: gpio@4805d000 {
 187                         compatible = "ti,omap4-gpio";
 188                         reg = <0x4805d000 0x200>;
 189                         interrupts = <0 34 0x4>;
 190                         ti,hwmods = "gpio6";
 191                         gpio-controller;
 192                         #gpio-cells = <2>;
 193                         interrupt-controller;
 194                         #interrupt-cells = <2>;
 195                 };
 196
 197                 gpio7: gpio@48051000 {
 198                         compatible = "ti,omap4-gpio";
 199                         reg = <0x48051000 0x200>;
 200                         interrupts = <0 35 0x4>;
 201                         ti,hwmods = "gpio7";
 202                         gpio-controller;
 203                         #gpio-cells = <2>;
 204                         interrupt-controller;
 205                         #interrupt-cells = <2>;
 206                 };
 207
 208                 gpio8: gpio@48053000 {
 209                         compatible = "ti,omap4-gpio";
 210                         reg = <0x48053000 0x200>;
 211                         interrupts = <0 121 0x4>;
 212                         ti,hwmods = "gpio8";
 213                         gpio-controller;
 214                         #gpio-cells = <2>;
 215                         interrupt-controller;
 216                         #interrupt-cells = <2>;
 217                 };
 218
 219                 gpmc: gpmc@50000000 {
 220                         compatible = "ti,omap4430-gpmc";
 221                         reg = <0x50000000 0x1000>;
 222                         #address-cells = <2>;
 223                         #size-cells = <1>;
 224                         interrupts = <0 20 0x4>;
 225                         gpmc,num-cs = <8>;
 226                         gpmc,num-waitpins = <4>;
 227                         ti,hwmods = "gpmc";
 228                 };
 229
 230                 i2c1: i2c@48070000 {
 231                         compatible = "ti,omap4-i2c";
 232                         reg = <0x48070000 0x100>;
 233                         interrupts = <0 56 0x4>;
 234                         #address-cells = <1>;
 235                         #size-cells = <0>;
 236                         ti,hwmods = "i2c1";
 237                 };
 238
 239                 i2c2: i2c@48072000 {
 240                         compatible = "ti,omap4-i2c";
 241                         reg = <0x48072000 0x100>;
 242                         interrupts = <0 57 0x4>;
 243                         #address-cells = <1>;
 244                         #size-cells = <0>;
 245                         ti,hwmods = "i2c2";
 246                 };
 247
 248                 i2c3: i2c@48060000 {
 249                         compatible = "ti,omap4-i2c";
 250                         reg = <0x48060000 0x100>;
 251                         interrupts = <0 61 0x4>;
 252                         #address-cells = <1>;
 253                         #size-cells = <0>;
 254                         ti,hwmods = "i2c3";
 255                 };
 256
 257                 i2c4: i2c@4807a000 {
 258                         compatible = "ti,omap4-i2c";
 259                         reg = <0x4807a000 0x100>;
 260                         interrupts = <0 62 0x4>;
 261                         #address-cells = <1>;
 262                         #size-cells = <0>;
 263                         ti,hwmods = "i2c4";
 264                 };
 265
 266                 i2c5: i2c@4807c000 {
 267                         compatible = "ti,omap4-i2c";
 268                         reg = <0x4807c000 0x100>;
 269                         interrupts = <0 60 0x4>;
 270                         #address-cells = <1>;
 271                         #size-cells = <0>;
 272                         ti,hwmods = "i2c5";
 273                 };
 274
 275                 mcspi1: spi@48098000 {
 276                         compatible = "ti,omap4-mcspi";
 277                         reg = <0x48098000 0x200>;
 278                         interrupts = <0 65 0x4>;
 279                         #address-cells = <1>;
 280                         #size-cells = <0>;
 281                         ti,hwmods = "mcspi1";
 282                         ti,spi-num-cs = <4>;
 283                         dmas = <&sdma 35>,
 284                                <&sdma 36>,
 285                                <&sdma 37>,
 286                                <&sdma 38>,
 287                                <&sdma 39>,
 288                                <&sdma 40>,
 289                                <&sdma 41>,
 290                                <&sdma 42>;
 291                         dma-names = "tx0", "rx0", "tx1", "rx1",
 292                                     "tx2", "rx2", "tx3", "rx3";
 293                 };
 294
 295                 mcspi2: spi@4809a000 {
 296                         compatible = "ti,omap4-mcspi";
 297                         reg = <0x4809a000 0x200>;
 298                         interrupts = <0 66 0x4>;
 299                         #address-cells = <1>;
 300                         #size-cells = <0>;
 301                         ti,hwmods = "mcspi2";
 302                         ti,spi-num-cs = <2>;
 303                         dmas = <&sdma 43>,
 304                                <&sdma 44>,
 305                                <&sdma 45>,
 306                                <&sdma 46>;
 307                         dma-names = "tx0", "rx0", "tx1", "rx1";
 308                 };
 309
 310                 mcspi3: spi@480b8000 {
 311                         compatible = "ti,omap4-mcspi";
 312                         reg = <0x480b8000 0x200>;
 313                         interrupts = <0 91 0x4>;
 314                         #address-cells = <1>;
 315                         #size-cells = <0>;
 316                         ti,hwmods = "mcspi3";
 317                         ti,spi-num-cs = <2>;
 318                         dmas = <&sdma 15>, <&sdma 16>;
 319                         dma-names = "tx0", "rx0";
 320                 };
 321
 322                 mcspi4: spi@480ba000 {
 323                         compatible = "ti,omap4-mcspi";
 324                         reg = <0x480ba000 0x200>;
 325                         interrupts = <0 48 0x4>;
 326                         #address-cells = <1>;
 327                         #size-cells = <0>;
 328                         ti,hwmods = "mcspi4";
 329                         ti,spi-num-cs = <1>;
 330                         dmas = <&sdma 70>, <&sdma 71>;
 331                         dma-names = "tx0", "rx0";
 332                 };
 333
 334                 uart1: serial@4806a000 {
 335                         compatible = "ti,omap4-uart";
 336                         reg = <0x4806a000 0x100>;
 337                         interrupts = <0 72 0x4>;
 338                         ti,hwmods = "uart1";
 339                         clock-frequency = <48000000>;
 340                 };
 341
 342                 uart2: serial@4806c000 {
 343                         compatible = "ti,omap4-uart";
 344                         reg = <0x4806c000 0x100>;
 345                         interrupts = <0 73 0x4>;
 346                         ti,hwmods = "uart2";
 347                         clock-frequency = <48000000>;
 348                 };
 349
 350                 uart3: serial@48020000 {
 351                         compatible = "ti,omap4-uart";
 352                         reg = <0x48020000 0x100>;
 353                         interrupts = <0 74 0x4>;
 354                         ti,hwmods = "uart3";
 355                         clock-frequency = <48000000>;
 356                 };
 357
 358                 uart4: serial@4806e000 {
 359                         compatible = "ti,omap4-uart";
 360                         reg = <0x4806e000 0x100>;
 361                         interrupts = <0 70 0x4>;
 362                         ti,hwmods = "uart4";
 363                         clock-frequency = <48000000>;
 364                 };
 365
 366                 uart5: serial@48066000 {
 367                         compatible = "ti,omap4-uart";
 368                         reg = <0x48066000 0x100>;
 369                         interrupts = <0 105 0x4>;
 370                         ti,hwmods = "uart5";
 371                         clock-frequency = <48000000>;
 372                 };
 373
 374                 uart6: serial@48068000 {
 375                         compatible = "ti,omap4-uart";
 376                         reg = <0x48068000 0x100>;
 377                         interrupts = <0 106 0x4>;
 378                         ti,hwmods = "uart6";
 379                         clock-frequency = <48000000>;
 380                 };
 381
 382                 mmc1: mmc@4809c000 {
 383                         compatible = "ti,omap4-hsmmc";
 384                         reg = <0x4809c000 0x400>;
 385                         interrupts = <0 83 0x4>;
 386                         ti,hwmods = "mmc1";
 387                         ti,dual-volt;
 388                         ti,needs-special-reset;
 389                         dmas = <&sdma 61>, <&sdma 62>;
 390                         dma-names = "tx", "rx";
 391                 };
 392
 393                 mmc2: mmc@480b4000 {
 394                         compatible = "ti,omap4-hsmmc";
 395                         reg = <0x480b4000 0x400>;
 396                         interrupts = <0 86 0x4>;
 397                         ti,hwmods = "mmc2";
 398                         ti,needs-special-reset;
 399                         dmas = <&sdma 47>, <&sdma 48>;
 400                         dma-names = "tx", "rx";
 401                 };
 402
 403                 mmc3: mmc@480ad000 {
 404                         compatible = "ti,omap4-hsmmc";
 405                         reg = <0x480ad000 0x400>;
 406                         interrupts = <0 94 0x4>;
 407                         ti,hwmods = "mmc3";
 408                         ti,needs-special-reset;
 409                         dmas = <&sdma 77>, <&sdma 78>;
 410                         dma-names = "tx", "rx";
 411                 };
 412
 413                 mmc4: mmc@480d1000 {
 414                         compatible = "ti,omap4-hsmmc";
 415                         reg = <0x480d1000 0x400>;
 416                         interrupts = <0 96 0x4>;
 417                         ti,hwmods = "mmc4";
 418                         ti,needs-special-reset;
 419                         dmas = <&sdma 57>, <&sdma 58>;
 420                         dma-names = "tx", "rx";
 421                 };
 422
 423                 mmc5: mmc@480d5000 {
 424                         compatible = "ti,omap4-hsmmc";
 425                         reg = <0x480d5000 0x400>;
 426                         interrupts = <0 59 0x4>;
 427                         ti,hwmods = "mmc5";
 428                         ti,needs-special-reset;
 429                         dmas = <&sdma 59>, <&sdma 60>;
 430                         dma-names = "tx", "rx";
 431                 };
 432
 433                 keypad: keypad@4ae1c000 {
 434                         compatible = "ti,omap4-keypad";
 435                         reg = <0x4ae1c000 0x400>;
 436                         ti,hwmods = "kbd";
 437                 };
 438
 439                 mcpdm: mcpdm@40132000 {
 440                         compatible = "ti,omap4-mcpdm";
 441                         reg = <0x40132000 0x7f>, /* MPU private access */
 442                               <0x49032000 0x7f>; /* L3 Interconnect */
 443                         reg-names = "mpu", "dma";
 444                         interrupts = <0 112 0x4>;
 445                         ti,hwmods = "mcpdm";
 446                         dmas = <&sdma 65>,
 447                                <&sdma 66>;
 448                         dma-names = "up_link", "dn_link";
 449                 };
 450
 451                 dmic: dmic@4012e000 {
 452                         compatible = "ti,omap4-dmic";
 453                         reg = <0x4012e000 0x7f>, /* MPU private access */
 454                               <0x4902e000 0x7f>; /* L3 Interconnect */
 455                         reg-names = "mpu", "dma";
 456                         interrupts = <0 114 0x4>;
 457                         ti,hwmods = "dmic";
 458                         dmas = <&sdma 67>;
 459                         dma-names = "up_link";
 460                 };
 461
 462                 mcbsp1: mcbsp@40122000 {
 463                         compatible = "ti,omap4-mcbsp";
 464                         reg = <0x40122000 0xff>, /* MPU private access */
 465                               <0x49022000 0xff>; /* L3 Interconnect */
 466                         reg-names = "mpu", "dma";
 467                         interrupts = <0 17 0x4>;
 468                         interrupt-names = "common";
 469                         ti,buffer-size = <128>;
 470                         ti,hwmods = "mcbsp1";
 471                         dmas = <&sdma 33>,
 472                                <&sdma 34>;
 473                         dma-names = "tx", "rx";
 474                 };
 475
 476                 mcbsp2: mcbsp@40124000 {
 477                         compatible = "ti,omap4-mcbsp";
 478                         reg = <0x40124000 0xff>, /* MPU private access */
 479                               <0x49024000 0xff>; /* L3 Interconnect */
 480                         reg-names = "mpu", "dma";
 481                         interrupts = <0 22 0x4>;
 482                         interrupt-names = "common";
 483                         ti,buffer-size = <128>;
 484                         ti,hwmods = "mcbsp2";
 485                         dmas = <&sdma 17>,
 486                                <&sdma 18>;
 487                         dma-names = "tx", "rx";
 488                 };
 489
 490                 mcbsp3: mcbsp@40126000 {
 491                         compatible = "ti,omap4-mcbsp";
 492                         reg = <0x40126000 0xff>, /* MPU private access */
 493                               <0x49026000 0xff>; /* L3 Interconnect */
 494                         reg-names = "mpu", "dma";
 495                         interrupts = <0 23 0x4>;
 496                         interrupt-names = "common";
 497                         ti,buffer-size = <128>;
 498                         ti,hwmods = "mcbsp3";
 499                         dmas = <&sdma 19>,
 500                                <&sdma 20>;
 501                         dma-names = "tx", "rx";
 502                 };
 503
 504                 timer1: timer@4ae18000 {
 505                         compatible = "ti,omap2-timer";
 506                         reg = <0x4ae18000 0x80>;
 507                         interrupts = <0 37 0x4>;
 508                         ti,hwmods = "timer1";
 509                         ti,timer-alwon;
 510                 };
 511
 512                 timer2: timer@48032000 {
 513                         compatible = "ti,omap2-timer";
 514                         reg = <0x48032000 0x80>;
 515                         interrupts = <0 38 0x4>;
 516                         ti,hwmods = "timer2";
 517                 };
 518
 519                 timer3: timer@48034000 {
 520                         compatible = "ti,omap2-timer";
 521                         reg = <0x48034000 0x80>;
 522                         interrupts = <0 39 0x4>;
 523                         ti,hwmods = "timer3";
 524                 };
 525
 526                 timer4: timer@48036000 {
 527                         compatible = "ti,omap2-timer";
 528                         reg = <0x48036000 0x80>;
 529                         interrupts = <0 40 0x4>;
 530                         ti,hwmods = "timer4";
 531                 };
 532
 533                 timer5: timer@40138000 {
 534                         compatible = "ti,omap2-timer";
 535                         reg = <0x40138000 0x80>,
 536                               <0x49038000 0x80>;
 537                         interrupts = <0 41 0x4>;
 538                         ti,hwmods = "timer5";
 539                         ti,timer-dsp;
 540                 };
 541
 542                 timer6: timer@4013a000 {
 543                         compatible = "ti,omap2-timer";
 544                         reg = <0x4013a000 0x80>,
 545                               <0x4903a000 0x80>;
 546                         interrupts = <0 42 0x4>;
 547                         ti,hwmods = "timer6";
 548                         ti,timer-dsp;
 549                         ti,timer-pwm;
 550                 };
 551
 552                 timer7: timer@4013c000 {
 553                         compatible = "ti,omap2-timer";
 554                         reg = <0x4013c000 0x80>,
 555                               <0x4903c000 0x80>;
 556                         interrupts = <0 43 0x4>;
 557                         ti,hwmods = "timer7";
 558                         ti,timer-dsp;
 559                 };
 560
 561                 timer8: timer@4013e000 {
 562                         compatible = "ti,omap2-timer";
 563                         reg = <0x4013e000 0x80>,
 564                               <0x4903e000 0x80>;
 565                         interrupts = <0 44 0x4>;
 566                         ti,hwmods = "timer8";
 567                         ti,timer-dsp;
 568                         ti,timer-pwm;
 569                 };
 570
 571                 timer9: timer@4803e000 {
 572                         compatible = "ti,omap2-timer";
 573                         reg = <0x4803e000 0x80>;
 574                         interrupts = <0 45 0x4>;
 575                         ti,hwmods = "timer9";
 576                 };
 577
 578                 timer10: timer@48086000 {
 579                         compatible = "ti,omap2-timer";
 580                         reg = <0x48086000 0x80>;
 581                         interrupts = <0 46 0x4>;
 582                         ti,hwmods = "timer10";
 583                 };
 584
 585                 timer11: timer@48088000 {
 586                         compatible = "ti,omap2-timer";
 587                         reg = <0x48088000 0x80>;
 588                         interrupts = <0 47 0x4>;
 589                         ti,hwmods = "timer11";
 590                         ti,timer-pwm;
 591                 };
 592
 593                 emif1: emif@0x4c000000 {
 594                         compatible      = "ti,emif-4d5";
 595                         ti,hwmods       = "emif1";
 596                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 597                         reg = <0x4c000000 0x400>;
 598                         interrupts = <0 110 0x4>;
 599                         hw-caps-read-idle-ctrl;
 600                         hw-caps-ll-interface;
 601                         hw-caps-temp-alert;
 602                 };
 603
 604                 emif2: emif@0x4d000000 {
 605                         compatible      = "ti,emif-4d5";
 606                         ti,hwmods       = "emif2";
 607                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 608                         reg = <0x4d000000 0x400>;
 609                         interrupts = <0 111 0x4>;
 610                         hw-caps-read-idle-ctrl;
 611                         hw-caps-ll-interface;
 612                         hw-caps-temp-alert;
 613                 };
 614
 615                 omap_control_usb: omap-control-usb@4a002300 {
 616                         compatible = "ti,omap-control-usb";
 617                         reg = <0x4a002300 0x4>,
 618                               <0x4a002370 0x4>;
 619                         reg-names = "control_dev_conf", "phy_power_usb";
 620                         ti,type = <2>;
 621                 };
 622
 623                 omap_dwc3@4a020000 {
 624                         compatible = "ti,dwc3";
 625                         ti,hwmods = "usb_otg_ss";
 626                         reg = <0x4a020000 0x1000>;
 627                         interrupts = <0 93 4>;
 628                         #address-cells = <1>;
 629                         #size-cells = <1>;
 630                         utmi-mode = <2>;
 631                         ranges;
 632                         dwc3@4a030000 {
 633                                 compatible = "synopsys,dwc3";
 634                                 reg = <0x4a030000 0x1000>;
 635                                 interrupts = <0 92 4>;
 636                                 usb-phy = <&usb2_phy>, <&usb3_phy>;
 637                                 tx-fifo-resize;
 638                         };
 639                 };
 640
 641                 ocp2scp {
 642                         compatible = "ti,omap-ocp2scp";
 643                         #address-cells = <1>;
 644                         #size-cells = <1>;
 645                         ranges;
 646                         ti,hwmods = "ocp2scp1";
 647                         usb2_phy: usb2phy@4a084000 {
 648                                 compatible = "ti,omap-usb2";
 649                                 reg = <0x4a084000 0x7c>;
 650                                 ctrl-module = <&omap_control_usb>;
 651                         };
 652
 653                         usb3_phy: usb3phy@4a084400 {
 654                                 compatible = "ti,omap-usb3";
 655                                 reg = <0x4a084400 0x80>,
 656                                       <0x4a084800 0x64>,
 657                                       <0x4a084c00 0x40>;
 658                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 659                                 ctrl-module = <&omap_control_usb>;
 660                         };
 661                 };
 662         };
 663 };