arch/arm/boot/dts/exynos5420.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
   8  * EXYNOS5420 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <dt-bindings/clock/exynos5420.h>
  17 #include "exynos5.dtsi"
  18 #include "exynos5420-pinctrl.dtsi"
  19
  20 #include <dt-bindings/clk/exynos-audss-clk.h>
  21
  22 / {
  23         compatible = "samsung,exynos5420";
  24
  25         aliases {
  26                 mshc0 = &mmc_0;
  27                 mshc1 = &mmc_1;
  28                 mshc2 = &mmc_2;
  29                 pinctrl0 = &pinctrl_0;
  30                 pinctrl1 = &pinctrl_1;
  31                 pinctrl2 = &pinctrl_2;
  32                 pinctrl3 = &pinctrl_3;
  33                 pinctrl4 = &pinctrl_4;
  34                 i2c0 = &i2c_0;
  35                 i2c1 = &i2c_1;
  36                 i2c2 = &i2c_2;
  37                 i2c3 = &i2c_3;
  38                 i2c4 = &hsi2c_4;
  39                 i2c5 = &hsi2c_5;
  40                 i2c6 = &hsi2c_6;
  41                 i2c7 = &hsi2c_7;
  42                 i2c8 = &hsi2c_8;
  43                 i2c9 = &hsi2c_9;
  44                 i2c10 = &hsi2c_10;
  45                 gsc0 = &gsc_0;
  46                 gsc1 = &gsc_1;
  47                 spi0 = &spi_0;
  48                 spi1 = &spi_1;
  49                 spi2 = &spi_2;
  50         };
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55
  56                 cpu0: cpu@0 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a15";
  59                         reg = <0x0>;
  60                         clock-frequency = <1800000000>;
  61                 };
  62
  63                 cpu1: cpu@1 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a15";
  66                         reg = <0x1>;
  67                         clock-frequency = <1800000000>;
  68                 };
  69
  70                 cpu2: cpu@2 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a15";
  73                         reg = <0x2>;
  74                         clock-frequency = <1800000000>;
  75                 };
  76
  77                 cpu3: cpu@3 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a15";
  80                         reg = <0x3>;
  81                         clock-frequency = <1800000000>;
  82                 };
  83
  84                 cpu4: cpu@100 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a7";
  87                         reg = <0x100>;
  88                         clock-frequency = <1000000000>;
  89                 };
  90
  91                 cpu5: cpu@101 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a7";
  94                         reg = <0x101>;
  95                         clock-frequency = <1000000000>;
  96                 };
  97
  98                 cpu6: cpu@102 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a7";
 101                         reg = <0x102>;
 102                         clock-frequency = <1000000000>;
 103                 };
 104
 105                 cpu7: cpu@103 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a7";
 108                         reg = <0x103>;
 109                         clock-frequency = <1000000000>;
 110                 };
 111         };
 112
 113         clock: clock-controller@10010000 {
 114                 compatible = "samsung,exynos5420-clock";
 115                 reg = <0x10010000 0x30000>;
 116                 #clock-cells = <1>;
 117         };
 118
 119         clock_audss: audss-clock-controller@3810000 {
 120                 compatible = "samsung,exynos5420-audss-clock";
 121                 reg = <0x03810000 0x0C>;
 122                 #clock-cells = <1>;
 123                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
 124                          <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
 125                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 126         };
 127
 128         codec@11000000 {
 129                 compatible = "samsung,mfc-v7";
 130                 reg = <0x11000000 0x10000>;
 131                 interrupts = <0 96 0>;
 132                 clocks = <&clock CLK_MFC>;
 133                 clock-names = "mfc";
 134         };
 135
 136         mmc_0: mmc@12200000 {
 137                 compatible = "samsung,exynos5420-dw-mshc-smu";
 138                 interrupts = <0 75 0>;
 139                 #address-cells = <1>;
 140                 #size-cells = <0>;
 141                 reg = <0x12200000 0x2000>;
 142                 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 143                 clock-names = "biu", "ciu";
 144                 fifo-depth = <0x40>;
 145                 status = "disabled";
 146         };
 147
 148         mmc_1: mmc@12210000 {
 149                 compatible = "samsung,exynos5420-dw-mshc-smu";
 150                 interrupts = <0 76 0>;
 151                 #address-cells = <1>;
 152                 #size-cells = <0>;
 153                 reg = <0x12210000 0x2000>;
 154                 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 155                 clock-names = "biu", "ciu";
 156                 fifo-depth = <0x40>;
 157                 status = "disabled";
 158         };
 159
 160         mmc_2: mmc@12220000 {
 161                 compatible = "samsung,exynos5420-dw-mshc";
 162                 interrupts = <0 77 0>;
 163                 #address-cells = <1>;
 164                 #size-cells = <0>;
 165                 reg = <0x12220000 0x1000>;
 166                 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 167                 clock-names = "biu", "ciu";
 168                 fifo-depth = <0x40>;
 169                 status = "disabled";
 170         };
 171
 172         mct@101C0000 {
 173                 compatible = "samsung,exynos4210-mct";
 174                 reg = <0x101C0000 0x800>;
 175                 interrupt-controller;
 176                 #interrups-cells = <1>;
 177                 interrupt-parent = <&mct_map>;
 178                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
 179                                 <8>, <9>, <10>, <11>;
 180                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 181                 clock-names = "fin_pll", "mct";
 182
 183                 mct_map: mct-map {
 184                         #interrupt-cells = <1>;
 185                         #address-cells = <0>;
 186                         #size-cells = <0>;
 187                         interrupt-map = <0 &combiner 23 3>,
 188                                         <1 &combiner 23 4>,
 189                                         <2 &combiner 25 2>,
 190                                         <3 &combiner 25 3>,
 191                                         <4 &gic 0 120 0>,
 192                                         <5 &gic 0 121 0>,
 193                                         <6 &gic 0 122 0>,
 194                                         <7 &gic 0 123 0>,
 195                                         <8 &gic 0 128 0>,
 196                                         <9 &gic 0 129 0>,
 197                                         <10 &gic 0 130 0>,
 198                                         <11 &gic 0 131 0>;
 199                 };
 200         };
 201
 202         gsc_pd: power-domain@10044000 {
 203                 compatible = "samsung,exynos4210-pd";
 204                 reg = <0x10044000 0x20>;
 205         };
 206
 207         isp_pd: power-domain@10044020 {
 208                 compatible = "samsung,exynos4210-pd";
 209                 reg = <0x10044020 0x20>;
 210         };
 211
 212         mfc_pd: power-domain@10044060 {
 213                 compatible = "samsung,exynos4210-pd";
 214                 reg = <0x10044060 0x20>;
 215         };
 216
 217         disp_pd: power-domain@100440C0 {
 218                 compatible = "samsung,exynos4210-pd";
 219                 reg = <0x100440C0 0x20>;
 220         };
 221
 222         mau_pd: power-domain@100440E0 {
 223                 compatible = "samsung,exynos4210-pd";
 224                 reg = <0x100440E0 0x20>;
 225         };
 226
 227         g2d_pd: power-domain@10044100 {
 228                 compatible = "samsung,exynos4210-pd";
 229                 reg = <0x10044100 0x20>;
 230         };
 231
 232         msc_pd: power-domain@10044120 {
 233                 compatible = "samsung,exynos4210-pd";
 234                 reg = <0x10044120 0x20>;
 235         };
 236
 237         pinctrl_0: pinctrl@13400000 {
 238                 compatible = "samsung,exynos5420-pinctrl";
 239                 reg = <0x13400000 0x1000>;
 240                 interrupts = <0 45 0>;
 241
 242                 wakeup-interrupt-controller {
 243                         compatible = "samsung,exynos4210-wakeup-eint";
 244                         interrupt-parent = <&gic>;
 245                         interrupts = <0 32 0>;
 246                 };
 247         };
 248
 249         pinctrl_1: pinctrl@13410000 {
 250                 compatible = "samsung,exynos5420-pinctrl";
 251                 reg = <0x13410000 0x1000>;
 252                 interrupts = <0 78 0>;
 253         };
 254
 255         pinctrl_2: pinctrl@14000000 {
 256                 compatible = "samsung,exynos5420-pinctrl";
 257                 reg = <0x14000000 0x1000>;
 258                 interrupts = <0 46 0>;
 259         };
 260
 261         pinctrl_3: pinctrl@14010000 {
 262                 compatible = "samsung,exynos5420-pinctrl";
 263                 reg = <0x14010000 0x1000>;
 264                 interrupts = <0 50 0>;
 265         };
 266
 267         pinctrl_4: pinctrl@03860000 {
 268                 compatible = "samsung,exynos5420-pinctrl";
 269                 reg = <0x03860000 0x1000>;
 270                 interrupts = <0 47 0>;
 271         };
 272
 273         rtc@101E0000 {
 274                 clocks = <&clock CLK_RTC>;
 275                 clock-names = "rtc";
 276                 status = "disabled";
 277         };
 278
 279         amba {
 280                 #address-cells = <1>;
 281                 #size-cells = <1>;
 282                 compatible = "arm,amba-bus";
 283                 interrupt-parent = <&gic>;
 284                 ranges;
 285
 286                 adma: adma@03880000 {
 287                         compatible = "arm,pl330", "arm,primecell";
 288                         reg = <0x03880000 0x1000>;
 289                         interrupts = <0 110 0>;
 290                         clocks = <&clock_audss EXYNOS_ADMA>;
 291                         clock-names = "apb_pclk";
 292                         #dma-cells = <1>;
 293                         #dma-channels = <6>;
 294                         #dma-requests = <16>;
 295                 };
 296
 297                 pdma0: pdma@121A0000 {
 298                         compatible = "arm,pl330", "arm,primecell";
 299                         reg = <0x121A0000 0x1000>;
 300                         interrupts = <0 34 0>;
 301                         clocks = <&clock CLK_PDMA0>;
 302                         clock-names = "apb_pclk";
 303                         #dma-cells = <1>;
 304                         #dma-channels = <8>;
 305                         #dma-requests = <32>;
 306                 };
 307
 308                 pdma1: pdma@121B0000 {
 309                         compatible = "arm,pl330", "arm,primecell";
 310                         reg = <0x121B0000 0x1000>;
 311                         interrupts = <0 35 0>;
 312                         clocks = <&clock CLK_PDMA1>;
 313                         clock-names = "apb_pclk";
 314                         #dma-cells = <1>;
 315                         #dma-channels = <8>;
 316                         #dma-requests = <32>;
 317                 };
 318
 319                 mdma0: mdma@10800000 {
 320                         compatible = "arm,pl330", "arm,primecell";
 321                         reg = <0x10800000 0x1000>;
 322                         interrupts = <0 33 0>;
 323                         clocks = <&clock CLK_MDMA0>;
 324                         clock-names = "apb_pclk";
 325                         #dma-cells = <1>;
 326                         #dma-channels = <8>;
 327                         #dma-requests = <1>;
 328                 };
 329
 330                 mdma1: mdma@11C10000 {
 331                         compatible = "arm,pl330", "arm,primecell";
 332                         reg = <0x11C10000 0x1000>;
 333                         interrupts = <0 124 0>;
 334                         clocks = <&clock CLK_MDMA1>;
 335                         clock-names = "apb_pclk";
 336                         #dma-cells = <1>;
 337                         #dma-channels = <8>;
 338                         #dma-requests = <1>;
 339                 };
 340         };
 341
 342         i2s0: i2s@03830000 {
 343                 compatible = "samsung,exynos5420-i2s";
 344                 reg = <0x03830000 0x100>;
 345                 dmas = <&adma 0
 346                         &adma 2
 347                         &adma 1>;
 348                 dma-names = "tx", "rx", "tx-sec";
 349                 clocks = <&clock_audss EXYNOS_I2S_BUS>,
 350                         <&clock_audss EXYNOS_I2S_BUS>,
 351                         <&clock_audss EXYNOS_SCLK_I2S>;
 352                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 353                 samsung,idma-addr = <0x03000000>;
 354                 pinctrl-names = "default";
 355                 pinctrl-0 = <&i2s0_bus>;
 356                 status = "disabled";
 357         };
 358
 359         i2s1: i2s@12D60000 {
 360                 compatible = "samsung,exynos5420-i2s";
 361                 reg = <0x12D60000 0x100>;
 362                 dmas = <&pdma1 12
 363                         &pdma1 11>;
 364                 dma-names = "tx", "rx";
 365                 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
 366                 clock-names = "iis", "i2s_opclk0";
 367                 pinctrl-names = "default";
 368                 pinctrl-0 = <&i2s1_bus>;
 369                 status = "disabled";
 370         };
 371
 372         i2s2: i2s@12D70000 {
 373                 compatible = "samsung,exynos5420-i2s";
 374                 reg = <0x12D70000 0x100>;
 375                 dmas = <&pdma0 12
 376                         &pdma0 11>;
 377                 dma-names = "tx", "rx";
 378                 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
 379                 clock-names = "iis", "i2s_opclk0";
 380                 pinctrl-names = "default";
 381                 pinctrl-0 = <&i2s2_bus>;
 382                 status = "disabled";
 383         };
 384
 385         spi_0: spi@12d20000 {
 386                 compatible = "samsung,exynos4210-spi";
 387                 reg = <0x12d20000 0x100>;
 388                 interrupts = <0 66 0>;
 389                 dmas = <&pdma0 5
 390                         &pdma0 4>;
 391                 dma-names = "tx", "rx";
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394                 pinctrl-names = "default";
 395                 pinctrl-0 = <&spi0_bus>;
 396                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 397                 clock-names = "spi", "spi_busclk0";
 398                 status = "disabled";
 399         };
 400
 401         spi_1: spi@12d30000 {
 402                 compatible = "samsung,exynos4210-spi";
 403                 reg = <0x12d30000 0x100>;
 404                 interrupts = <0 67 0>;
 405                 dmas = <&pdma1 5
 406                         &pdma1 4>;
 407                 dma-names = "tx", "rx";
 408                 #address-cells = <1>;
 409                 #size-cells = <0>;
 410                 pinctrl-names = "default";
 411                 pinctrl-0 = <&spi1_bus>;
 412                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 413                 clock-names = "spi", "spi_busclk0";
 414                 status = "disabled";
 415         };
 416
 417         spi_2: spi@12d40000 {
 418                 compatible = "samsung,exynos4210-spi";
 419                 reg = <0x12d40000 0x100>;
 420                 interrupts = <0 68 0>;
 421                 dmas = <&pdma0 7
 422                         &pdma0 6>;
 423                 dma-names = "tx", "rx";
 424                 #address-cells = <1>;
 425                 #size-cells = <0>;
 426                 pinctrl-names = "default";
 427                 pinctrl-0 = <&spi2_bus>;
 428                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 429                 clock-names = "spi", "spi_busclk0";
 430                 status = "disabled";
 431         };
 432
 433         serial@12C00000 {
 434                 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 435                 clock-names = "uart", "clk_uart_baud0";
 436         };
 437
 438         serial@12C10000 {
 439                 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 440                 clock-names = "uart", "clk_uart_baud0";
 441         };
 442
 443         serial@12C20000 {
 444                 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 445                 clock-names = "uart", "clk_uart_baud0";
 446         };
 447
 448         serial@12C30000 {
 449                 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 450                 clock-names = "uart", "clk_uart_baud0";
 451         };
 452
 453         pwm: pwm@12dd0000 {
 454                 compatible = "samsung,exynos4210-pwm";
 455                 reg = <0x12dd0000 0x100>;
 456                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 457                 #pwm-cells = <3>;
 458                 clocks = <&clock CLK_PWM>;
 459                 clock-names = "timers";
 460         };
 461
 462         dp_phy: video-phy@10040728 {
 463                 compatible = "samsung,exynos5250-dp-video-phy";
 464                 reg = <0x10040728 4>;
 465                 #phy-cells = <0>;
 466         };
 467
 468         dp-controller@145B0000 {
 469                 clocks = <&clock CLK_DP1>;
 470                 clock-names = "dp";
 471                 phys = <&dp_phy>;
 472                 phy-names = "dp";
 473         };
 474
 475         fimd@14400000 {
 476                 samsung,power-domain = <&disp_pd>;
 477                 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
 478                 clock-names = "sclk_fimd", "fimd";
 479         };
 480
 481         adc: adc@12D10000 {
 482                 compatible = "samsung,exynos-adc-v2";
 483                 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
 484                 interrupts = <0 106 0>;
 485                 clocks = <&clock CLK_TSADC>;
 486                 clock-names = "adc";
 487                 #io-channel-cells = <1>;
 488                 io-channel-ranges;
 489                 status = "disabled";
 490         };
 491
 492         i2c_0: i2c@12C60000 {
 493                 compatible = "samsung,s3c2440-i2c";
 494                 reg = <0x12C60000 0x100>;
 495                 interrupts = <0 56 0>;
 496                 #address-cells = <1>;
 497                 #size-cells = <0>;
 498                 clocks = <&clock CLK_I2C0>;
 499                 clock-names = "i2c";
 500                 pinctrl-names = "default";
 501                 pinctrl-0 = <&i2c0_bus>;
 502                 status = "disabled";
 503         };
 504
 505         i2c_1: i2c@12C70000 {
 506                 compatible = "samsung,s3c2440-i2c";
 507                 reg = <0x12C70000 0x100>;
 508                 interrupts = <0 57 0>;
 509                 #address-cells = <1>;
 510                 #size-cells = <0>;
 511                 clocks = <&clock CLK_I2C1>;
 512                 clock-names = "i2c";
 513                 pinctrl-names = "default";
 514                 pinctrl-0 = <&i2c1_bus>;
 515                 status = "disabled";
 516         };
 517
 518         i2c_2: i2c@12C80000 {
 519                 compatible = "samsung,s3c2440-i2c";
 520                 reg = <0x12C80000 0x100>;
 521                 interrupts = <0 58 0>;
 522                 #address-cells = <1>;
 523                 #size-cells = <0>;
 524                 clocks = <&clock CLK_I2C2>;
 525                 clock-names = "i2c";
 526                 pinctrl-names = "default";
 527                 pinctrl-0 = <&i2c2_bus>;
 528                 status = "disabled";
 529         };
 530
 531         i2c_3: i2c@12C90000 {
 532                 compatible = "samsung,s3c2440-i2c";
 533                 reg = <0x12C90000 0x100>;
 534                 interrupts = <0 59 0>;
 535                 #address-cells = <1>;
 536                 #size-cells = <0>;
 537                 clocks = <&clock CLK_I2C3>;
 538                 clock-names = "i2c";
 539                 pinctrl-names = "default";
 540                 pinctrl-0 = <&i2c3_bus>;
 541                 status = "disabled";
 542         };
 543
 544         hsi2c_4: i2c@12CA0000 {
 545                 compatible = "samsung,exynos5-hsi2c";
 546                 reg = <0x12CA0000 0x1000>;
 547                 interrupts = <0 60 0>;
 548                 #address-cells = <1>;
 549                 #size-cells = <0>;
 550                 pinctrl-names = "default";
 551                 pinctrl-0 = <&i2c4_hs_bus>;
 552                 clocks = <&clock CLK_I2C4>;
 553                 clock-names = "hsi2c";
 554                 status = "disabled";
 555         };
 556
 557         hsi2c_5: i2c@12CB0000 {
 558                 compatible = "samsung,exynos5-hsi2c";
 559                 reg = <0x12CB0000 0x1000>;
 560                 interrupts = <0 61 0>;
 561                 #address-cells = <1>;
 562                 #size-cells = <0>;
 563                 pinctrl-names = "default";
 564                 pinctrl-0 = <&i2c5_hs_bus>;
 565                 clocks = <&clock CLK_I2C5>;
 566                 clock-names = "hsi2c";
 567                 status = "disabled";
 568         };
 569
 570         hsi2c_6: i2c@12CC0000 {
 571                 compatible = "samsung,exynos5-hsi2c";
 572                 reg = <0x12CC0000 0x1000>;
 573                 interrupts = <0 62 0>;
 574                 #address-cells = <1>;
 575                 #size-cells = <0>;
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&i2c6_hs_bus>;
 578                 clocks = <&clock CLK_I2C6>;
 579                 clock-names = "hsi2c";
 580                 status = "disabled";
 581         };
 582
 583         hsi2c_7: i2c@12CD0000 {
 584                 compatible = "samsung,exynos5-hsi2c";
 585                 reg = <0x12CD0000 0x1000>;
 586                 interrupts = <0 63 0>;
 587                 #address-cells = <1>;
 588                 #size-cells = <0>;
 589                 pinctrl-names = "default";
 590                 pinctrl-0 = <&i2c7_hs_bus>;
 591                 clocks = <&clock CLK_I2C7>;
 592                 clock-names = "hsi2c";
 593                 status = "disabled";
 594         };
 595
 596         hsi2c_8: i2c@12E00000 {
 597                 compatible = "samsung,exynos5-hsi2c";
 598                 reg = <0x12E00000 0x1000>;
 599                 interrupts = <0 87 0>;
 600                 #address-cells = <1>;
 601                 #size-cells = <0>;
 602                 pinctrl-names = "default";
 603                 pinctrl-0 = <&i2c8_hs_bus>;
 604                 clocks = <&clock CLK_I2C8>;
 605                 clock-names = "hsi2c";
 606                 status = "disabled";
 607         };
 608
 609         hsi2c_9: i2c@12E10000 {
 610                 compatible = "samsung,exynos5-hsi2c";
 611                 reg = <0x12E10000 0x1000>;
 612                 interrupts = <0 88 0>;
 613                 #address-cells = <1>;
 614                 #size-cells = <0>;
 615                 pinctrl-names = "default";
 616                 pinctrl-0 = <&i2c9_hs_bus>;
 617                 clocks = <&clock CLK_I2C9>;
 618                 clock-names = "hsi2c";
 619                 status = "disabled";
 620         };
 621
 622         hsi2c_10: i2c@12E20000 {
 623                 compatible = "samsung,exynos5-hsi2c";
 624                 reg = <0x12E20000 0x1000>;
 625                 interrupts = <0 203 0>;
 626                 #address-cells = <1>;
 627                 #size-cells = <0>;
 628                 pinctrl-names = "default";
 629                 pinctrl-0 = <&i2c10_hs_bus>;
 630                 clocks = <&clock CLK_I2C10>;
 631                 clock-names = "hsi2c";
 632                 status = "disabled";
 633         };
 634
 635         hdmi@14530000 {
 636                 compatible = "samsung,exynos4212-hdmi";
 637                 reg = <0x14530000 0x70000>;
 638                 interrupts = <0 95 0>;
 639                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 640                          <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 641                          <&clock CLK_MOUT_HDMI>;
 642                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 643                         "sclk_hdmiphy", "mout_hdmi";
 644                 status = "disabled";
 645         };
 646
 647         mixer@14450000 {
 648                 compatible = "samsung,exynos5420-mixer";
 649                 reg = <0x14450000 0x10000>;
 650                 interrupts = <0 94 0>;
 651                 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
 652                 clock-names = "mixer", "sclk_hdmi";
 653         };
 654
 655         gsc_0: video-scaler@13e00000 {
 656                 compatible = "samsung,exynos5-gsc";
 657                 reg = <0x13e00000 0x1000>;
 658                 interrupts = <0 85 0>;
 659                 clocks = <&clock CLK_GSCL0>;
 660                 clock-names = "gscl";
 661                 samsung,power-domain = <&gsc_pd>;
 662         };
 663
 664         gsc_1: video-scaler@13e10000 {
 665                 compatible = "samsung,exynos5-gsc";
 666                 reg = <0x13e10000 0x1000>;
 667                 interrupts = <0 86 0>;
 668                 clocks = <&clock CLK_GSCL1>;
 669                 clock-names = "gscl";
 670                 samsung,power-domain = <&gsc_pd>;
 671         };
 672
 673         pmu_system_controller: system-controller@10040000 {
 674                 compatible = "samsung,exynos5420-pmu", "syscon";
 675                 reg = <0x10040000 0x5000>;
 676         };
 677
 678         tmu_cpu0: tmu@10060000 {
 679                 compatible = "samsung,exynos5420-tmu";
 680                 reg = <0x10060000 0x100>;
 681                 interrupts = <0 65 0>;
 682                 clocks = <&clock CLK_TMU>;
 683                 clock-names = "tmu_apbif";
 684         };
 685
 686         tmu_cpu1: tmu@10064000 {
 687                 compatible = "samsung,exynos5420-tmu";
 688                 reg = <0x10064000 0x100>;
 689                 interrupts = <0 183 0>;
 690                 clocks = <&clock CLK_TMU>;
 691                 clock-names = "tmu_apbif";
 692         };
 693
 694         tmu_cpu2: tmu@10068000 {
 695                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 696                 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 697                 interrupts = <0 184 0>;
 698                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
 699                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 700         };
 701
 702         tmu_cpu3: tmu@1006c000 {
 703                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 704                 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 705                 interrupts = <0 185 0>;
 706                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
 707                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 708         };
 709
 710         tmu_gpu: tmu@100a0000 {
 711                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 712                 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 713                 interrupts = <0 215 0>;
 714                 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
 715                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 716         };
 717
 718         watchdog@101D0000 {
 719                 compatible = "samsung,exynos5420-wdt";
 720                 reg = <0x101D0000 0x100>;
 721                 interrupts = <0 42 0>;
 722                 clocks = <&clock CLK_WDT>;
 723                 clock-names = "watchdog";
 724                 samsung,syscon-phandle = <&pmu_system_controller>;
 725         };
 726 };