2 * Device Tree Include file for Marvell Armada 370 family SoC
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
14 * Contains definitions specific to the Armada 370 SoC that are not
15 * common to all Armada SoCs.
18 /include/ "armada-370-xp.dtsi"
19 /include/ "skeleton.dtsi"
22 model = "Marvell Armada 370 family SoC";
23 compatible = "marvell,armada370", "marvell,armada-370-xp";
32 ranges = <0 0xd0000000 0x100000>;
34 system-controller@18200 {
35 compatible = "marvell,armada-370-xp-system-controller";
36 reg = <0x18200 0x100>;
40 compatible = "marvell,aurora-outer-cache";
41 reg = <0xd0008000 0x1000>;
42 cache-id-part = <0x100>;
46 mpic: interrupt-controller@20000 {
47 reg = <0x20a00 0x1d0>, <0x21870 0x58>;
51 compatible = "marvell,mv88f6710-pinctrl";
54 sdio_pins1: sdio-pins1 {
55 marvell,pins = "mpp9", "mpp11", "mpp12",
56 "mpp13", "mpp14", "mpp15";
57 marvell,function = "sd0";
60 sdio_pins2: sdio-pins2 {
61 marvell,pins = "mpp47", "mpp48", "mpp49",
62 "mpp50", "mpp51", "mpp52";
63 marvell,function = "sd0";
66 sdio_pins3: sdio-pins3 {
67 marvell,pins = "mpp48", "mpp49", "mpp50",
68 "mpp51", "mpp52", "mpp53";
69 marvell,function = "sd0";
74 compatible = "marvell,orion-gpio";
80 #interrupts-cells = <2>;
81 interrupts = <82>, <83>, <84>, <85>;
85 compatible = "marvell,orion-gpio";
91 #interrupts-cells = <2>;
92 interrupts = <87>, <88>, <89>, <90>;
96 compatible = "marvell,orion-gpio";
101 interrupt-controller;
102 #interrupts-cells = <2>;
106 coreclk: mvebu-sar@18230 {
107 compatible = "marvell,armada-370-core-clock";
108 reg = <0x18230 0x08>;
112 gateclk: clock-gating-control@18220 {
113 compatible = "marvell,armada-370-gating-clock";
115 clocks = <&coreclk 0>;
120 compatible = "marvell,orion-xor";
139 compatible = "marvell,orion-xor";
158 clocks = <&coreclk 0>;
162 clocks = <&coreclk 0>;
166 compatible = "marvell,armada370-thermal";
173 compatible = "marvell,armada-370-pcie";
177 #address-cells = <3>;
180 bus-range = <0x00 0xff>;
182 reg = <0x40000 0x2000>, <0x80000 0x2000>;
184 reg-names = "pcie0.0", "pcie1.0";
186 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
187 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
188 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
189 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
193 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
194 reg = <0x0800 0 0 0 0>;
195 #address-cells = <3>;
197 #interrupt-cells = <1>;
199 interrupt-map-mask = <0 0 0 0>;
200 interrupt-map = <0 0 0 0 &mpic 58>;
201 marvell,pcie-port = <0>;
202 marvell,pcie-lane = <0>;
203 clocks = <&gateclk 5>;
209 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
210 reg = <0x1000 0 0 0 0>;
211 #address-cells = <3>;
213 #interrupt-cells = <1>;
215 interrupt-map-mask = <0 0 0 0>;
216 interrupt-map = <0 0 0 0 &mpic 62>;
217 marvell,pcie-port = <1>;
218 marvell,pcie-lane = <0>;
219 clocks = <&gateclk 9>;