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Merge branch 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelv...
[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / arch / arm / boot / dts / am335x-evm.dts
1 /*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 /dts-v1/;
9
10 #include "am33xx.dtsi"
11
12 / {
13 model = "TI AM335x EVM";
14 compatible = "ti,am335x-evm", "ti,am33xx";
15
16 cpus {
17 cpu@0 {
18 cpu0-supply = <&vdd1_reg>;
19 };
20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x80000000 0x10000000>; /* 256 MB */
25 };
26
27 am33xx_pinmux: pinmux@44e10800 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
30
31 matrix_keypad_s0: matrix_keypad_s0 {
32 pinctrl-single,pins = <
33 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
34 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
35 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
36 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
37 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
38 >;
39 };
40
41 volume_keys_s0: volume_keys_s0 {
42 pinctrl-single,pins = <
43 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
44 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
45 >;
46 };
47
48 i2c0_pins: pinmux_i2c0_pins {
49 pinctrl-single,pins = <
50 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
51 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
52 >;
53 };
54
55 i2c1_pins: pinmux_i2c1_pins {
56 pinctrl-single,pins = <
57 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
58 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
59 >;
60 };
61
62 uart0_pins: pinmux_uart0_pins {
63 pinctrl-single,pins = <
64 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
65 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
66 >;
67 };
68
69 clkout2_pin: pinmux_clkout2_pin {
70 pinctrl-single,pins = <
71 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
72 >;
73 };
74
75 nandflash_pins_s0: nandflash_pins_s0 {
76 pinctrl-single,pins = <
77 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
78 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
79 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
80 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
81 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
82 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
83 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
84 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
85 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
86 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
87 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
88 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
89 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
90 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
91 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
92 >;
93 };
94
95 ecap0_pins: backlight_pins {
96 pinctrl-single,pins = <
97 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
98 >;
99 };
100
101 cpsw_default: cpsw_default {
102 pinctrl-single,pins = <
103 /* Slave 1 */
104 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
105 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
106 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
107 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
108 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
109 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
110 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
111 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
112 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
113 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
114 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
115 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
116 >;
117 };
118
119 cpsw_sleep: cpsw_sleep {
120 pinctrl-single,pins = <
121 /* Slave 1 reset value */
122 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
123 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
124 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
125 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
126 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
127 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
128 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
129 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
130 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
131 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
132 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
133 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
134 >;
135 };
136
137 davinci_mdio_default: davinci_mdio_default {
138 pinctrl-single,pins = <
139 /* MDIO */
140 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
141 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
142 >;
143 };
144
145 davinci_mdio_sleep: davinci_mdio_sleep {
146 pinctrl-single,pins = <
147 /* MDIO reset value */
148 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
149 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
150 >;
151 };
152 };
153
154 ocp {
155 uart0: serial@44e09000 {
156 pinctrl-names = "default";
157 pinctrl-0 = <&uart0_pins>;
158
159 status = "okay";
160 };
161
162 i2c0: i2c@44e0b000 {
163 pinctrl-names = "default";
164 pinctrl-0 = <&i2c0_pins>;
165
166 status = "okay";
167 clock-frequency = <400000>;
168
169 tps: tps@2d {
170 reg = <0x2d>;
171 };
172 };
173
174 i2c1: i2c@4802a000 {
175 pinctrl-names = "default";
176 pinctrl-0 = <&i2c1_pins>;
177
178 status = "okay";
179 clock-frequency = <100000>;
180
181 lis331dlh: lis331dlh@18 {
182 compatible = "st,lis331dlh", "st,lis3lv02d";
183 reg = <0x18>;
184 Vdd-supply = <&lis3_reg>;
185 Vdd_IO-supply = <&lis3_reg>;
186
187 st,click-single-x;
188 st,click-single-y;
189 st,click-single-z;
190 st,click-thresh-x = <10>;
191 st,click-thresh-y = <10>;
192 st,click-thresh-z = <10>;
193 st,irq1-click;
194 st,irq2-click;
195 st,wakeup-x-lo;
196 st,wakeup-x-hi;
197 st,wakeup-y-lo;
198 st,wakeup-y-hi;
199 st,wakeup-z-lo;
200 st,wakeup-z-hi;
201 st,min-limit-x = <120>;
202 st,min-limit-y = <120>;
203 st,min-limit-z = <140>;
204 st,max-limit-x = <550>;
205 st,max-limit-y = <550>;
206 st,max-limit-z = <750>;
207 };
208
209 tsl2550: tsl2550@39 {
210 compatible = "taos,tsl2550";
211 reg = <0x39>;
212 };
213
214 tmp275: tmp275@48 {
215 compatible = "ti,tmp275";
216 reg = <0x48>;
217 };
218 };
219
220 elm: elm@48080000 {
221 status = "okay";
222 };
223
224 epwmss0: epwmss@48300000 {
225 status = "okay";
226
227 ecap0: ecap@48300100 {
228 status = "okay";
229 pinctrl-names = "default";
230 pinctrl-0 = <&ecap0_pins>;
231 };
232 };
233
234 gpmc: gpmc@50000000 {
235 status = "okay";
236 pinctrl-names = "default";
237 pinctrl-0 = <&nandflash_pins_s0>;
238 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
239 nand@0,0 {
240 reg = <0 0 0>; /* CS0, offset 0 */
241 nand-bus-width = <8>;
242 ti,nand-ecc-opt = "bch8";
243 gpmc,device-nand = "true";
244 gpmc,device-width = <1>;
245 gpmc,sync-clk-ps = <0>;
246 gpmc,cs-on-ns = <0>;
247 gpmc,cs-rd-off-ns = <44>;
248 gpmc,cs-wr-off-ns = <44>;
249 gpmc,adv-on-ns = <6>;
250 gpmc,adv-rd-off-ns = <34>;
251 gpmc,adv-wr-off-ns = <44>;
252 gpmc,we-on-ns = <0>;
253 gpmc,we-off-ns = <40>;
254 gpmc,oe-on-ns = <0>;
255 gpmc,oe-off-ns = <54>;
256 gpmc,access-ns = <64>;
257 gpmc,rd-cycle-ns = <82>;
258 gpmc,wr-cycle-ns = <82>;
259 gpmc,wait-on-read = "true";
260 gpmc,wait-on-write = "true";
261 gpmc,bus-turnaround-ns = <0>;
262 gpmc,cycle2cycle-delay-ns = <0>;
263 gpmc,clk-activation-ns = <0>;
264 gpmc,wait-monitoring-ns = <0>;
265 gpmc,wr-access-ns = <40>;
266 gpmc,wr-data-mux-bus-ns = <0>;
267
268 #address-cells = <1>;
269 #size-cells = <1>;
270 elm_id = <&elm>;
271
272 /* MTD partition table */
273 partition@0 {
274 label = "SPL1";
275 reg = <0x00000000 0x000020000>;
276 };
277
278 partition@1 {
279 label = "SPL2";
280 reg = <0x00020000 0x00020000>;
281 };
282
283 partition@2 {
284 label = "SPL3";
285 reg = <0x00040000 0x00020000>;
286 };
287
288 partition@3 {
289 label = "SPL4";
290 reg = <0x00060000 0x00020000>;
291 };
292
293 partition@4 {
294 label = "U-boot";
295 reg = <0x00080000 0x001e0000>;
296 };
297
298 partition@5 {
299 label = "environment";
300 reg = <0x00260000 0x00020000>;
301 };
302
303 partition@6 {
304 label = "Kernel";
305 reg = <0x00280000 0x00500000>;
306 };
307
308 partition@7 {
309 label = "File-System";
310 reg = <0x00780000 0x0F880000>;
311 };
312 };
313 };
314 };
315
316 vbat: fixedregulator@0 {
317 compatible = "regulator-fixed";
318 regulator-name = "vbat";
319 regulator-min-microvolt = <5000000>;
320 regulator-max-microvolt = <5000000>;
321 regulator-boot-on;
322 };
323
324 lis3_reg: fixedregulator@1 {
325 compatible = "regulator-fixed";
326 regulator-name = "lis3_reg";
327 regulator-boot-on;
328 };
329
330 matrix_keypad: matrix_keypad@0 {
331 compatible = "gpio-matrix-keypad";
332 debounce-delay-ms = <5>;
333 col-scan-delay-us = <2>;
334
335 row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
336 &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
337 &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
338
339 col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
340 &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
341
342 linux,keymap = <0x0000008b /* MENU */
343 0x0100009e /* BACK */
344 0x02000069 /* LEFT */
345 0x0001006a /* RIGHT */
346 0x0101001c /* ENTER */
347 0x0201006c>; /* DOWN */
348 };
349
350 gpio_keys: volume_keys@0 {
351 compatible = "gpio-keys";
352 #address-cells = <1>;
353 #size-cells = <0>;
354 autorepeat;
355
356 switch@9 {
357 label = "volume-up";
358 linux,code = <115>;
359 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
360 gpio-key,wakeup;
361 };
362
363 switch@10 {
364 label = "volume-down";
365 linux,code = <114>;
366 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
367 gpio-key,wakeup;
368 };
369 };
370
371 backlight {
372 compatible = "pwm-backlight";
373 pwms = <&ecap0 0 50000 0>;
374 brightness-levels = <0 51 53 56 62 75 101 152 255>;
375 default-brightness-level = <8>;
376 };
377 };
378
379 #include "tps65910.dtsi"
380
381 &tps {
382 vcc1-supply = <&vbat>;
383 vcc2-supply = <&vbat>;
384 vcc3-supply = <&vbat>;
385 vcc4-supply = <&vbat>;
386 vcc5-supply = <&vbat>;
387 vcc6-supply = <&vbat>;
388 vcc7-supply = <&vbat>;
389 vccio-supply = <&vbat>;
390
391 regulators {
392 vrtc_reg: regulator@0 {
393 regulator-always-on;
394 };
395
396 vio_reg: regulator@1 {
397 regulator-always-on;
398 };
399
400 vdd1_reg: regulator@2 {
401 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
402 regulator-name = "vdd_mpu";
403 regulator-min-microvolt = <912500>;
404 regulator-max-microvolt = <1312500>;
405 regulator-boot-on;
406 regulator-always-on;
407 };
408
409 vdd2_reg: regulator@3 {
410 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
411 regulator-name = "vdd_core";
412 regulator-min-microvolt = <912500>;
413 regulator-max-microvolt = <1150000>;
414 regulator-boot-on;
415 regulator-always-on;
416 };
417
418 vdd3_reg: regulator@4 {
419 regulator-always-on;
420 };
421
422 vdig1_reg: regulator@5 {
423 regulator-always-on;
424 };
425
426 vdig2_reg: regulator@6 {
427 regulator-always-on;
428 };
429
430 vpll_reg: regulator@7 {
431 regulator-always-on;
432 };
433
434 vdac_reg: regulator@8 {
435 regulator-always-on;
436 };
437
438 vaux1_reg: regulator@9 {
439 regulator-always-on;
440 };
441
442 vaux2_reg: regulator@10 {
443 regulator-always-on;
444 };
445
446 vaux33_reg: regulator@11 {
447 regulator-always-on;
448 };
449
450 vmmc_reg: regulator@12 {
451 regulator-always-on;
452 };
453 };
454 };
455
456 &mac {
457 pinctrl-names = "default", "sleep";
458 pinctrl-0 = <&cpsw_default>;
459 pinctrl-1 = <&cpsw_sleep>;
460 };
461
462 &davinci_mdio {
463 pinctrl-names = "default", "sleep";
464 pinctrl-0 = <&davinci_mdio_default>;
465 pinctrl-1 = <&davinci_mdio_sleep>;
466 };
467
468 &cpsw_emac0 {
469 phy_id = <&davinci_mdio>, <0>;
470 phy-mode = "rgmii-txid";
471 };
472
473 &cpsw_emac1 {
474 phy_id = <&davinci_mdio>, <1>;
475 phy-mode = "rgmii-txid";
476 };