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Merge branch 'tip/tracing/core' of git://git.kernel.org/pub/scm/linux/kernel/git...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / boot / compressed / head.S
1 /*
2 * linux/arch/arm/boot/compressed/head.S
3 *
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/linkage.h>
12
13 /*
14 * Debugging stuff
15 *
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
19 */
20 #ifdef DEBUG
21
22 #if defined(CONFIG_DEBUG_ICEDCC)
23
24 #ifdef CONFIG_CPU_V6
25 .macro loadsp, rb, tmp
26 .endm
27 .macro writeb, ch, rb
28 mcr p14, 0, \ch, c0, c5, 0
29 .endm
30 #elif defined(CONFIG_CPU_V7)
31 .macro loadsp, rb, tmp
32 .endm
33 .macro writeb, ch, rb
34 wait: mrc p14, 0, pc, c0, c1, 0
35 bcs wait
36 mcr p14, 0, \ch, c0, c5, 0
37 .endm
38 #elif defined(CONFIG_CPU_XSCALE)
39 .macro loadsp, rb, tmp
40 .endm
41 .macro writeb, ch, rb
42 mcr p14, 0, \ch, c8, c0, 0
43 .endm
44 #else
45 .macro loadsp, rb, tmp
46 .endm
47 .macro writeb, ch, rb
48 mcr p14, 0, \ch, c1, c0, 0
49 .endm
50 #endif
51
52 #else
53
54 #include <mach/debug-macro.S>
55
56 .macro writeb, ch, rb
57 senduart \ch, \rb
58 .endm
59
60 #if defined(CONFIG_ARCH_SA1100)
61 .macro loadsp, rb, tmp
62 mov \rb, #0x80000000 @ physical base address
63 #ifdef CONFIG_DEBUG_LL_SER3
64 add \rb, \rb, #0x00050000 @ Ser3
65 #else
66 add \rb, \rb, #0x00010000 @ Ser1
67 #endif
68 .endm
69 #elif defined(CONFIG_ARCH_S3C2410)
70 .macro loadsp, rb, tmp
71 mov \rb, #0x50000000
72 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
73 .endm
74 #else
75 .macro loadsp, rb, tmp
76 addruart \rb, \tmp
77 .endm
78 #endif
79 #endif
80 #endif
81
82 .macro kputc,val
83 mov r0, \val
84 bl putc
85 .endm
86
87 .macro kphex,val,len
88 mov r0, \val
89 mov r1, #\len
90 bl phex
91 .endm
92
93 .macro debug_reloc_start
94 #ifdef DEBUG
95 kputc #'\n'
96 kphex r6, 8 /* processor id */
97 kputc #':'
98 kphex r7, 8 /* architecture id */
99 #ifdef CONFIG_CPU_CP15
100 kputc #':'
101 mrc p15, 0, r0, c1, c0
102 kphex r0, 8 /* control reg */
103 #endif
104 kputc #'\n'
105 kphex r5, 8 /* decompressed kernel start */
106 kputc #'-'
107 kphex r9, 8 /* decompressed kernel end */
108 kputc #'>'
109 kphex r4, 8 /* kernel execution address */
110 kputc #'\n'
111 #endif
112 .endm
113
114 .macro debug_reloc_end
115 #ifdef DEBUG
116 kphex r5, 8 /* end of kernel */
117 kputc #'\n'
118 mov r0, r4
119 bl memdump /* dump 256 bytes at start of kernel */
120 #endif
121 .endm
122
123 .section ".start", #alloc, #execinstr
124 /*
125 * sort out different calling conventions
126 */
127 .align
128 start:
129 .type start,#function
130 .rept 8
131 mov r0, r0
132 .endr
133
134 b 1f
135 .word 0x016f2818 @ Magic numbers to help the loader
136 .word start @ absolute load/run zImage address
137 .word _edata @ zImage end address
138 1: mov r7, r1 @ save architecture ID
139 mov r8, r2 @ save atags pointer
140
141 #ifndef __ARM_ARCH_2__
142 /*
143 * Booting from Angel - need to enter SVC mode and disable
144 * FIQs/IRQs (numeric definitions from angel arm.h source).
145 * We only do this if we were in user mode on entry.
146 */
147 mrs r2, cpsr @ get current mode
148 tst r2, #3 @ not user?
149 bne not_angel
150 mov r0, #0x17 @ angel_SWIreason_EnterSVC
151 ARM( swi 0x123456 ) @ angel_SWI_ARM
152 THUMB( svc 0xab ) @ angel_SWI_THUMB
153 not_angel:
154 mrs r2, cpsr @ turn off interrupts to
155 orr r2, r2, #0xc0 @ prevent angel from running
156 msr cpsr_c, r2
157 #else
158 teqp pc, #0x0c000003 @ turn off interrupts
159 #endif
160
161 /*
162 * Note that some cache flushing and other stuff may
163 * be needed here - is there an Angel SWI call for this?
164 */
165
166 /*
167 * some architecture specific code can be inserted
168 * by the linker here, but it should preserve r7, r8, and r9.
169 */
170
171 .text
172 adr r0, LC0
173 ARM( ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp} )
174 THUMB( ldmia r0, {r1, r2, r3, r4, r5, r6, ip} )
175 THUMB( ldr sp, [r0, #28] )
176 subs r0, r0, r1 @ calculate the delta offset
177
178 @ if delta is zero, we are
179 beq not_relocated @ running at the address we
180 @ were linked at.
181
182 /*
183 * We're running at a different address. We need to fix
184 * up various pointers:
185 * r5 - zImage base address
186 * r6 - GOT start
187 * ip - GOT end
188 */
189 add r5, r5, r0
190 add r6, r6, r0
191 add ip, ip, r0
192
193 #ifndef CONFIG_ZBOOT_ROM
194 /*
195 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
196 * we need to fix up pointers into the BSS region.
197 * r2 - BSS start
198 * r3 - BSS end
199 * sp - stack pointer
200 */
201 add r2, r2, r0
202 add r3, r3, r0
203 add sp, sp, r0
204
205 /*
206 * Relocate all entries in the GOT table.
207 */
208 1: ldr r1, [r6, #0] @ relocate entries in the GOT
209 add r1, r1, r0 @ table. This fixes up the
210 str r1, [r6], #4 @ C references.
211 cmp r6, ip
212 blo 1b
213 #else
214
215 /*
216 * Relocate entries in the GOT table. We only relocate
217 * the entries that are outside the (relocated) BSS region.
218 */
219 1: ldr r1, [r6, #0] @ relocate entries in the GOT
220 cmp r1, r2 @ entry < bss_start ||
221 cmphs r3, r1 @ _end < entry
222 addlo r1, r1, r0 @ table. This fixes up the
223 str r1, [r6], #4 @ C references.
224 cmp r6, ip
225 blo 1b
226 #endif
227
228 not_relocated: mov r0, #0
229 1: str r0, [r2], #4 @ clear bss
230 str r0, [r2], #4
231 str r0, [r2], #4
232 str r0, [r2], #4
233 cmp r2, r3
234 blo 1b
235
236 /*
237 * The C runtime environment should now be setup
238 * sufficiently. Turn the cache on, set up some
239 * pointers, and start decompressing.
240 */
241 bl cache_on
242
243 mov r1, sp @ malloc space above stack
244 add r2, sp, #0x10000 @ 64k max
245
246 /*
247 * Check to see if we will overwrite ourselves.
248 * r4 = final kernel address
249 * r5 = start of this image
250 * r2 = end of malloc space (and therefore this image)
251 * We basically want:
252 * r4 >= r2 -> OK
253 * r4 + image length <= r5 -> OK
254 */
255 cmp r4, r2
256 bhs wont_overwrite
257 sub r3, sp, r5 @ > compressed kernel size
258 add r0, r4, r3, lsl #2 @ allow for 4x expansion
259 cmp r0, r5
260 bls wont_overwrite
261
262 mov r5, r2 @ decompress after malloc space
263 mov r0, r5
264 mov r3, r7
265 bl decompress_kernel
266
267 add r0, r0, #127 + 128 @ alignment + stack
268 bic r0, r0, #127 @ align the kernel length
269 /*
270 * r0 = decompressed kernel length
271 * r1-r3 = unused
272 * r4 = kernel execution address
273 * r5 = decompressed kernel start
274 * r6 = processor ID
275 * r7 = architecture ID
276 * r8 = atags pointer
277 * r9-r12,r14 = corrupted
278 */
279 add r1, r5, r0 @ end of decompressed kernel
280 adr r2, reloc_start
281 ldr r3, LC1
282 add r3, r2, r3
283 1: ldmia r2!, {r9 - r12, r14} @ copy relocation code
284 stmia r1!, {r9 - r12, r14}
285 ldmia r2!, {r9 - r12, r14}
286 stmia r1!, {r9 - r12, r14}
287 cmp r2, r3
288 blo 1b
289 mov sp, r1
290 add sp, sp, #128 @ relocate the stack
291
292 bl cache_clean_flush
293 ARM( add pc, r5, r0 ) @ call relocation code
294 THUMB( add r12, r5, r0 )
295 THUMB( mov pc, r12 ) @ call relocation code
296
297 /*
298 * We're not in danger of overwriting ourselves. Do this the simple way.
299 *
300 * r4 = kernel execution address
301 * r7 = architecture ID
302 */
303 wont_overwrite: mov r0, r4
304 mov r3, r7
305 bl decompress_kernel
306 b call_kernel
307
308 .align 2
309 .type LC0, #object
310 LC0: .word LC0 @ r1
311 .word __bss_start @ r2
312 .word _end @ r3
313 .word zreladdr @ r4
314 .word _start @ r5
315 .word _got_start @ r6
316 .word _got_end @ ip
317 .word user_stack+4096 @ sp
318 LC1: .word reloc_end - reloc_start
319 .size LC0, . - LC0
320
321 #ifdef CONFIG_ARCH_RPC
322 .globl params
323 params: ldr r0, =params_phys
324 mov pc, lr
325 .ltorg
326 .align
327 #endif
328
329 /*
330 * Turn on the cache. We need to setup some page tables so that we
331 * can have both the I and D caches on.
332 *
333 * We place the page tables 16k down from the kernel execution address,
334 * and we hope that nothing else is using it. If we're using it, we
335 * will go pop!
336 *
337 * On entry,
338 * r4 = kernel execution address
339 * r6 = processor ID
340 * r7 = architecture number
341 * r8 = atags pointer
342 * r9 = run-time address of "start" (???)
343 * On exit,
344 * r1, r2, r3, r9, r10, r12 corrupted
345 * This routine must preserve:
346 * r4, r5, r6, r7, r8
347 */
348 .align 5
349 cache_on: mov r3, #8 @ cache_on function
350 b call_cache_fn
351
352 /*
353 * Initialize the highest priority protection region, PR7
354 * to cover all 32bit address and cacheable and bufferable.
355 */
356 __armv4_mpu_cache_on:
357 mov r0, #0x3f @ 4G, the whole
358 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
359 mcr p15, 0, r0, c6, c7, 1
360
361 mov r0, #0x80 @ PR7
362 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
363 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
364 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
365
366 mov r0, #0xc000
367 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
368 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
369
370 mov r0, #0
371 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
372 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
373 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
374 mrc p15, 0, r0, c1, c0, 0 @ read control reg
375 @ ...I .... ..D. WC.M
376 orr r0, r0, #0x002d @ .... .... ..1. 11.1
377 orr r0, r0, #0x1000 @ ...1 .... .... ....
378
379 mcr p15, 0, r0, c1, c0, 0 @ write control reg
380
381 mov r0, #0
382 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
383 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
384 mov pc, lr
385
386 __armv3_mpu_cache_on:
387 mov r0, #0x3f @ 4G, the whole
388 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
389
390 mov r0, #0x80 @ PR7
391 mcr p15, 0, r0, c2, c0, 0 @ cache on
392 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
393
394 mov r0, #0xc000
395 mcr p15, 0, r0, c5, c0, 0 @ access permission
396
397 mov r0, #0
398 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
399 mrc p15, 0, r0, c1, c0, 0 @ read control reg
400 @ .... .... .... WC.M
401 orr r0, r0, #0x000d @ .... .... .... 11.1
402 mov r0, #0
403 mcr p15, 0, r0, c1, c0, 0 @ write control reg
404
405 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
406 mov pc, lr
407
408 __setup_mmu: sub r3, r4, #16384 @ Page directory size
409 bic r3, r3, #0xff @ Align the pointer
410 bic r3, r3, #0x3f00
411 /*
412 * Initialise the page tables, turning on the cacheable and bufferable
413 * bits for the RAM area only.
414 */
415 mov r0, r3
416 mov r9, r0, lsr #18
417 mov r9, r9, lsl #18 @ start of RAM
418 add r10, r9, #0x10000000 @ a reasonable RAM size
419 mov r1, #0x12
420 orr r1, r1, #3 << 10
421 add r2, r3, #16384
422 1: cmp r1, r9 @ if virt > start of RAM
423 orrhs r1, r1, #0x0c @ set cacheable, bufferable
424 cmp r1, r10 @ if virt > end of RAM
425 bichs r1, r1, #0x0c @ clear cacheable, bufferable
426 str r1, [r0], #4 @ 1:1 mapping
427 add r1, r1, #1048576
428 teq r0, r2
429 bne 1b
430 /*
431 * If ever we are running from Flash, then we surely want the cache
432 * to be enabled also for our execution instance... We map 2MB of it
433 * so there is no map overlap problem for up to 1 MB compressed kernel.
434 * If the execution is in RAM then we would only be duplicating the above.
435 */
436 mov r1, #0x1e
437 orr r1, r1, #3 << 10
438 mov r2, pc, lsr #20
439 orr r1, r1, r2, lsl #20
440 add r0, r3, r2, lsl #2
441 str r1, [r0], #4
442 add r1, r1, #1048576
443 str r1, [r0]
444 mov pc, lr
445 ENDPROC(__setup_mmu)
446
447 __armv4_mmu_cache_on:
448 mov r12, lr
449 #ifdef CONFIG_MMU
450 bl __setup_mmu
451 mov r0, #0
452 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
453 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
454 mrc p15, 0, r0, c1, c0, 0 @ read control reg
455 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
456 orr r0, r0, #0x0030
457 #ifdef CONFIG_CPU_ENDIAN_BE8
458 orr r0, r0, #1 << 25 @ big-endian page tables
459 #endif
460 bl __common_mmu_cache_on
461 mov r0, #0
462 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
463 #endif
464 mov pc, r12
465
466 __armv7_mmu_cache_on:
467 mov r12, lr
468 #ifdef CONFIG_MMU
469 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
470 tst r11, #0xf @ VMSA
471 blne __setup_mmu
472 mov r0, #0
473 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
474 tst r11, #0xf @ VMSA
475 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
476 #endif
477 mrc p15, 0, r0, c1, c0, 0 @ read control reg
478 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
479 orr r0, r0, #0x003c @ write buffer
480 #ifdef CONFIG_MMU
481 #ifdef CONFIG_CPU_ENDIAN_BE8
482 orr r0, r0, #1 << 25 @ big-endian page tables
483 #endif
484 orrne r0, r0, #1 @ MMU enabled
485 movne r1, #-1
486 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
487 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
488 #endif
489 mcr p15, 0, r0, c1, c0, 0 @ load control register
490 mrc p15, 0, r0, c1, c0, 0 @ and read it back
491 mov r0, #0
492 mcr p15, 0, r0, c7, c5, 4 @ ISB
493 mov pc, r12
494
495 __fa526_cache_on:
496 mov r12, lr
497 bl __setup_mmu
498 mov r0, #0
499 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
500 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
501 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
502 mrc p15, 0, r0, c1, c0, 0 @ read control reg
503 orr r0, r0, #0x1000 @ I-cache enable
504 bl __common_mmu_cache_on
505 mov r0, #0
506 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
507 mov pc, r12
508
509 __arm6_mmu_cache_on:
510 mov r12, lr
511 bl __setup_mmu
512 mov r0, #0
513 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
514 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
515 mov r0, #0x30
516 bl __common_mmu_cache_on
517 mov r0, #0
518 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
519 mov pc, r12
520
521 __common_mmu_cache_on:
522 #ifndef CONFIG_THUMB2_KERNEL
523 #ifndef DEBUG
524 orr r0, r0, #0x000d @ Write buffer, mmu
525 #endif
526 mov r1, #-1
527 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
528 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
529 b 1f
530 .align 5 @ cache line aligned
531 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
532 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
533 sub pc, lr, r0, lsr #32 @ properly flush pipeline
534 #endif
535
536 /*
537 * All code following this line is relocatable. It is relocated by
538 * the above code to the end of the decompressed kernel image and
539 * executed there. During this time, we have no stacks.
540 *
541 * r0 = decompressed kernel length
542 * r1-r3 = unused
543 * r4 = kernel execution address
544 * r5 = decompressed kernel start
545 * r6 = processor ID
546 * r7 = architecture ID
547 * r8 = atags pointer
548 * r9-r12,r14 = corrupted
549 */
550 .align 5
551 reloc_start: add r9, r5, r0
552 sub r9, r9, #128 @ do not copy the stack
553 debug_reloc_start
554 mov r1, r4
555 1:
556 .rept 4
557 ldmia r5!, {r0, r2, r3, r10 - r12, r14} @ relocate kernel
558 stmia r1!, {r0, r2, r3, r10 - r12, r14}
559 .endr
560
561 cmp r5, r9
562 blo 1b
563 mov sp, r1
564 add sp, sp, #128 @ relocate the stack
565 debug_reloc_end
566
567 call_kernel: bl cache_clean_flush
568 bl cache_off
569 mov r0, #0 @ must be zero
570 mov r1, r7 @ restore architecture number
571 mov r2, r8 @ restore atags pointer
572 mov pc, r4 @ call kernel
573
574 /*
575 * Here follow the relocatable cache support functions for the
576 * various processors. This is a generic hook for locating an
577 * entry and jumping to an instruction at the specified offset
578 * from the start of the block. Please note this is all position
579 * independent code.
580 *
581 * r1 = corrupted
582 * r2 = corrupted
583 * r3 = block offset
584 * r6 = corrupted
585 * r12 = corrupted
586 */
587
588 call_cache_fn: adr r12, proc_types
589 #ifdef CONFIG_CPU_CP15
590 mrc p15, 0, r6, c0, c0 @ get processor ID
591 #else
592 ldr r6, =CONFIG_PROCESSOR_ID
593 #endif
594 1: ldr r1, [r12, #0] @ get value
595 ldr r2, [r12, #4] @ get mask
596 eor r1, r1, r6 @ (real ^ match)
597 tst r1, r2 @ & mask
598 ARM( addeq pc, r12, r3 ) @ call cache function
599 THUMB( addeq r12, r3 )
600 THUMB( moveq pc, r12 ) @ call cache function
601 add r12, r12, #4*5
602 b 1b
603
604 /*
605 * Table for cache operations. This is basically:
606 * - CPU ID match
607 * - CPU ID mask
608 * - 'cache on' method instruction
609 * - 'cache off' method instruction
610 * - 'cache flush' method instruction
611 *
612 * We match an entry using: ((real_id ^ match) & mask) == 0
613 *
614 * Writethrough caches generally only need 'on' and 'off'
615 * methods. Writeback caches _must_ have the flush method
616 * defined.
617 */
618 .align 2
619 .type proc_types,#object
620 proc_types:
621 .word 0x41560600 @ ARM6/610
622 .word 0xffffffe0
623 W(b) __arm6_mmu_cache_off @ works, but slow
624 W(b) __arm6_mmu_cache_off
625 mov pc, lr
626 THUMB( nop )
627 @ b __arm6_mmu_cache_on @ untested
628 @ b __arm6_mmu_cache_off
629 @ b __armv3_mmu_cache_flush
630
631 .word 0x00000000 @ old ARM ID
632 .word 0x0000f000
633 mov pc, lr
634 THUMB( nop )
635 mov pc, lr
636 THUMB( nop )
637 mov pc, lr
638 THUMB( nop )
639
640 .word 0x41007000 @ ARM7/710
641 .word 0xfff8fe00
642 W(b) __arm7_mmu_cache_off
643 W(b) __arm7_mmu_cache_off
644 mov pc, lr
645 THUMB( nop )
646
647 .word 0x41807200 @ ARM720T (writethrough)
648 .word 0xffffff00
649 W(b) __armv4_mmu_cache_on
650 W(b) __armv4_mmu_cache_off
651 mov pc, lr
652 THUMB( nop )
653
654 .word 0x41007400 @ ARM74x
655 .word 0xff00ff00
656 W(b) __armv3_mpu_cache_on
657 W(b) __armv3_mpu_cache_off
658 W(b) __armv3_mpu_cache_flush
659
660 .word 0x41009400 @ ARM94x
661 .word 0xff00ff00
662 W(b) __armv4_mpu_cache_on
663 W(b) __armv4_mpu_cache_off
664 W(b) __armv4_mpu_cache_flush
665
666 .word 0x00007000 @ ARM7 IDs
667 .word 0x0000f000
668 mov pc, lr
669 THUMB( nop )
670 mov pc, lr
671 THUMB( nop )
672 mov pc, lr
673 THUMB( nop )
674
675 @ Everything from here on will be the new ID system.
676
677 .word 0x4401a100 @ sa110 / sa1100
678 .word 0xffffffe0
679 W(b) __armv4_mmu_cache_on
680 W(b) __armv4_mmu_cache_off
681 W(b) __armv4_mmu_cache_flush
682
683 .word 0x6901b110 @ sa1110
684 .word 0xfffffff0
685 W(b) __armv4_mmu_cache_on
686 W(b) __armv4_mmu_cache_off
687 W(b) __armv4_mmu_cache_flush
688
689 .word 0x56056930
690 .word 0xff0ffff0 @ PXA935
691 W(b) __armv4_mmu_cache_on
692 W(b) __armv4_mmu_cache_off
693 W(b) __armv4_mmu_cache_flush
694
695 .word 0x56158000 @ PXA168
696 .word 0xfffff000
697 W(b) __armv4_mmu_cache_on
698 W(b) __armv4_mmu_cache_off
699 W(b) __armv5tej_mmu_cache_flush
700
701 .word 0x56056930
702 .word 0xff0ffff0 @ PXA935
703 W(b) __armv4_mmu_cache_on
704 W(b) __armv4_mmu_cache_off
705 W(b) __armv4_mmu_cache_flush
706
707 .word 0x56050000 @ Feroceon
708 .word 0xff0f0000
709 W(b) __armv4_mmu_cache_on
710 W(b) __armv4_mmu_cache_off
711 W(b) __armv5tej_mmu_cache_flush
712
713 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
714 /* this conflicts with the standard ARMv5TE entry */
715 .long 0x41009260 @ Old Feroceon
716 .long 0xff00fff0
717 b __armv4_mmu_cache_on
718 b __armv4_mmu_cache_off
719 b __armv5tej_mmu_cache_flush
720 #endif
721
722 .word 0x66015261 @ FA526
723 .word 0xff01fff1
724 W(b) __fa526_cache_on
725 W(b) __armv4_mmu_cache_off
726 W(b) __fa526_cache_flush
727
728 @ These match on the architecture ID
729
730 .word 0x00020000 @ ARMv4T
731 .word 0x000f0000
732 W(b) __armv4_mmu_cache_on
733 W(b) __armv4_mmu_cache_off
734 W(b) __armv4_mmu_cache_flush
735
736 .word 0x00050000 @ ARMv5TE
737 .word 0x000f0000
738 W(b) __armv4_mmu_cache_on
739 W(b) __armv4_mmu_cache_off
740 W(b) __armv4_mmu_cache_flush
741
742 .word 0x00060000 @ ARMv5TEJ
743 .word 0x000f0000
744 W(b) __armv4_mmu_cache_on
745 W(b) __armv4_mmu_cache_off
746 W(b) __armv4_mmu_cache_flush
747
748 .word 0x0007b000 @ ARMv6
749 .word 0x000ff000
750 W(b) __armv4_mmu_cache_on
751 W(b) __armv4_mmu_cache_off
752 W(b) __armv6_mmu_cache_flush
753
754 .word 0x560f5810 @ Marvell PJ4 ARMv6
755 .word 0xff0ffff0
756 W(b) __armv4_mmu_cache_on
757 W(b) __armv4_mmu_cache_off
758 W(b) __armv6_mmu_cache_flush
759
760 .word 0x000f0000 @ new CPU Id
761 .word 0x000f0000
762 W(b) __armv7_mmu_cache_on
763 W(b) __armv7_mmu_cache_off
764 W(b) __armv7_mmu_cache_flush
765
766 .word 0 @ unrecognised type
767 .word 0
768 mov pc, lr
769 THUMB( nop )
770 mov pc, lr
771 THUMB( nop )
772 mov pc, lr
773 THUMB( nop )
774
775 .size proc_types, . - proc_types
776
777 /*
778 * Turn off the Cache and MMU. ARMv3 does not support
779 * reading the control register, but ARMv4 does.
780 *
781 * On entry, r6 = processor ID
782 * On exit, r0, r1, r2, r3, r12 corrupted
783 * This routine must preserve: r4, r6, r7
784 */
785 .align 5
786 cache_off: mov r3, #12 @ cache_off function
787 b call_cache_fn
788
789 __armv4_mpu_cache_off:
790 mrc p15, 0, r0, c1, c0
791 bic r0, r0, #0x000d
792 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
793 mov r0, #0
794 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
795 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
796 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
797 mov pc, lr
798
799 __armv3_mpu_cache_off:
800 mrc p15, 0, r0, c1, c0
801 bic r0, r0, #0x000d
802 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
803 mov r0, #0
804 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
805 mov pc, lr
806
807 __armv4_mmu_cache_off:
808 #ifdef CONFIG_MMU
809 mrc p15, 0, r0, c1, c0
810 bic r0, r0, #0x000d
811 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
812 mov r0, #0
813 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
814 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
815 #endif
816 mov pc, lr
817
818 __armv7_mmu_cache_off:
819 mrc p15, 0, r0, c1, c0
820 #ifdef CONFIG_MMU
821 bic r0, r0, #0x000d
822 #else
823 bic r0, r0, #0x000c
824 #endif
825 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
826 mov r12, lr
827 bl __armv7_mmu_cache_flush
828 mov r0, #0
829 #ifdef CONFIG_MMU
830 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
831 #endif
832 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
833 mcr p15, 0, r0, c7, c10, 4 @ DSB
834 mcr p15, 0, r0, c7, c5, 4 @ ISB
835 mov pc, r12
836
837 __arm6_mmu_cache_off:
838 mov r0, #0x00000030 @ ARM6 control reg.
839 b __armv3_mmu_cache_off
840
841 __arm7_mmu_cache_off:
842 mov r0, #0x00000070 @ ARM7 control reg.
843 b __armv3_mmu_cache_off
844
845 __armv3_mmu_cache_off:
846 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
847 mov r0, #0
848 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
849 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
850 mov pc, lr
851
852 /*
853 * Clean and flush the cache to maintain consistency.
854 *
855 * On entry,
856 * r6 = processor ID
857 * On exit,
858 * r1, r2, r3, r11, r12 corrupted
859 * This routine must preserve:
860 * r0, r4, r5, r6, r7
861 */
862 .align 5
863 cache_clean_flush:
864 mov r3, #16
865 b call_cache_fn
866
867 __armv4_mpu_cache_flush:
868 mov r2, #1
869 mov r3, #0
870 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
871 mov r1, #7 << 5 @ 8 segments
872 1: orr r3, r1, #63 << 26 @ 64 entries
873 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
874 subs r3, r3, #1 << 26
875 bcs 2b @ entries 63 to 0
876 subs r1, r1, #1 << 5
877 bcs 1b @ segments 7 to 0
878
879 teq r2, #0
880 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
881 mcr p15, 0, ip, c7, c10, 4 @ drain WB
882 mov pc, lr
883
884 __fa526_cache_flush:
885 mov r1, #0
886 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
887 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
888 mcr p15, 0, r1, c7, c10, 4 @ drain WB
889 mov pc, lr
890
891 __armv6_mmu_cache_flush:
892 mov r1, #0
893 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
894 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
895 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
896 mcr p15, 0, r1, c7, c10, 4 @ drain WB
897 mov pc, lr
898
899 __armv7_mmu_cache_flush:
900 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
901 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
902 mov r10, #0
903 beq hierarchical
904 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
905 b iflush
906 hierarchical:
907 mcr p15, 0, r10, c7, c10, 5 @ DMB
908 stmfd sp!, {r0-r7, r9-r11}
909 mrc p15, 1, r0, c0, c0, 1 @ read clidr
910 ands r3, r0, #0x7000000 @ extract loc from clidr
911 mov r3, r3, lsr #23 @ left align loc bit field
912 beq finished @ if loc is 0, then no need to clean
913 mov r10, #0 @ start clean at cache level 0
914 loop1:
915 add r2, r10, r10, lsr #1 @ work out 3x current cache level
916 mov r1, r0, lsr r2 @ extract cache type bits from clidr
917 and r1, r1, #7 @ mask of the bits for current cache only
918 cmp r1, #2 @ see what cache we have at this level
919 blt skip @ skip if no cache, or just i-cache
920 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
921 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
922 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
923 and r2, r1, #7 @ extract the length of the cache lines
924 add r2, r2, #4 @ add 4 (line length offset)
925 ldr r4, =0x3ff
926 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
927 clz r5, r4 @ find bit position of way size increment
928 ldr r7, =0x7fff
929 ands r7, r7, r1, lsr #13 @ extract max number of the index size
930 loop2:
931 mov r9, r4 @ create working copy of max way size
932 loop3:
933 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
934 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
935 THUMB( lsl r6, r9, r5 )
936 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
937 THUMB( lsl r6, r7, r2 )
938 THUMB( orr r11, r11, r6 ) @ factor index number into r11
939 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
940 subs r9, r9, #1 @ decrement the way
941 bge loop3
942 subs r7, r7, #1 @ decrement the index
943 bge loop2
944 skip:
945 add r10, r10, #2 @ increment cache number
946 cmp r3, r10
947 bgt loop1
948 finished:
949 ldmfd sp!, {r0-r7, r9-r11}
950 mov r10, #0 @ swith back to cache level 0
951 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
952 iflush:
953 mcr p15, 0, r10, c7, c10, 4 @ DSB
954 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
955 mcr p15, 0, r10, c7, c10, 4 @ DSB
956 mcr p15, 0, r10, c7, c5, 4 @ ISB
957 mov pc, lr
958
959 __armv5tej_mmu_cache_flush:
960 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
961 bne 1b
962 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
963 mcr p15, 0, r0, c7, c10, 4 @ drain WB
964 mov pc, lr
965
966 __armv4_mmu_cache_flush:
967 mov r2, #64*1024 @ default: 32K dcache size (*2)
968 mov r11, #32 @ default: 32 byte line size
969 mrc p15, 0, r3, c0, c0, 1 @ read cache type
970 teq r3, r6 @ cache ID register present?
971 beq no_cache_id
972 mov r1, r3, lsr #18
973 and r1, r1, #7
974 mov r2, #1024
975 mov r2, r2, lsl r1 @ base dcache size *2
976 tst r3, #1 << 14 @ test M bit
977 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
978 mov r3, r3, lsr #12
979 and r3, r3, #3
980 mov r11, #8
981 mov r11, r11, lsl r3 @ cache line size in bytes
982 no_cache_id:
983 mov r1, pc
984 bic r1, r1, #63 @ align to longest cache line
985 add r2, r1, r2
986 1:
987 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
988 THUMB( ldr r3, [r1] ) @ s/w flush D cache
989 THUMB( add r1, r1, r11 )
990 teq r1, r2
991 bne 1b
992
993 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
994 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
995 mcr p15, 0, r1, c7, c10, 4 @ drain WB
996 mov pc, lr
997
998 __armv3_mmu_cache_flush:
999 __armv3_mpu_cache_flush:
1000 mov r1, #0
1001 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1002 mov pc, lr
1003
1004 /*
1005 * Various debugging routines for printing hex characters and
1006 * memory, which again must be relocatable.
1007 */
1008 #ifdef DEBUG
1009 .align 2
1010 .type phexbuf,#object
1011 phexbuf: .space 12
1012 .size phexbuf, . - phexbuf
1013
1014 phex: adr r3, phexbuf
1015 mov r2, #0
1016 strb r2, [r3, r1]
1017 1: subs r1, r1, #1
1018 movmi r0, r3
1019 bmi puts
1020 and r2, r0, #15
1021 mov r0, r0, lsr #4
1022 cmp r2, #10
1023 addge r2, r2, #7
1024 add r2, r2, #'0'
1025 strb r2, [r3, r1]
1026 b 1b
1027
1028 puts: loadsp r3, r1
1029 1: ldrb r2, [r0], #1
1030 teq r2, #0
1031 moveq pc, lr
1032 2: writeb r2, r3
1033 mov r1, #0x00020000
1034 3: subs r1, r1, #1
1035 bne 3b
1036 teq r2, #'\n'
1037 moveq r2, #'\r'
1038 beq 2b
1039 teq r0, #0
1040 bne 1b
1041 mov pc, lr
1042 putc:
1043 mov r2, r0
1044 mov r0, #0
1045 loadsp r3, r1
1046 b 2b
1047
1048 memdump: mov r12, r0
1049 mov r10, lr
1050 mov r11, #0
1051 2: mov r0, r11, lsl #2
1052 add r0, r0, r12
1053 mov r1, #8
1054 bl phex
1055 mov r0, #':'
1056 bl putc
1057 1: mov r0, #' '
1058 bl putc
1059 ldr r0, [r12, r11, lsl #2]
1060 mov r1, #8
1061 bl phex
1062 and r0, r11, #7
1063 teq r0, #3
1064 moveq r0, #' '
1065 bleq putc
1066 and r0, r11, #7
1067 add r11, r11, #1
1068 teq r0, #7
1069 bne 1b
1070 mov r0, #'\n'
1071 bl putc
1072 cmp r11, #64
1073 blt 2b
1074 mov pc, r10
1075 #endif
1076
1077 .ltorg
1078 reloc_end:
1079
1080 .align
1081 .section ".stack", "w"
1082 user_stack: .space 4096
kernel source for telekom puls (alcatel/mediatek)