4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if MMU
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_KPROBES if !XIP_KERNEL
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
24 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
25 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
26 select HAVE_GENERIC_DMA_COHERENT
27 select HAVE_KERNEL_GZIP
28 select HAVE_KERNEL_LZO
29 select HAVE_KERNEL_LZMA
32 select HAVE_PERF_EVENTS
33 select PERF_USE_VMALLOC
34 select HAVE_REGS_AND_STACK_ACCESS_API
35 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_GENERIC_HARDIRQS
38 select HARDIRQS_SW_RESEND
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select ARCH_WANT_IPC_PARSE_VERSION
42 select HARDIRQS_SW_RESEND
43 select CPU_PM if (SUSPEND || CPU_IDLE)
44 select GENERIC_PCI_IOMAP
46 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 select GENERIC_STRNCPY_FROM_USER
50 select GENERIC_STRNLEN_USER
51 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
53 The ARM series is a line of low-power-consumption RISC chip designs
54 licensed by ARM Ltd and targeted at embedded applications and
55 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
56 manufactured, but legacy ARM-based PC hardware remains popular in
57 Europe. There is an ARM Linux project with a web page at
58 <http://www.arm.linux.org.uk/>.
60 config ARM_HAS_SG_CHAIN
63 config NEED_SG_DMA_LENGTH
66 config ARM_DMA_USE_IOMMU
67 select NEED_SG_DMA_LENGTH
68 select ARM_HAS_SG_CHAIN
77 config SYS_SUPPORTS_APM_EMULATION
85 select GENERIC_ALLOCATOR
96 The Extended Industry Standard Architecture (EISA) bus was
97 developed as an open alternative to the IBM MicroChannel bus.
99 The EISA bus provided some of the features of the IBM MicroChannel
100 bus while maintaining backward compatibility with cards made for
101 the older ISA bus. The EISA bus saw limited use between 1988 and
102 1995 when it was made obsolete by the PCI bus.
104 Say Y here if you are building a kernel for an EISA-based machine.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config RWSEM_GENERIC_SPINLOCK
132 config RWSEM_XCHGADD_ALGORITHM
135 config ARCH_HAS_ILOG2_U32
138 config ARCH_HAS_ILOG2_U64
141 config ARCH_HAS_CPUFREQ
144 Internal node to signify that the ARCH has CPUFREQ support
145 and that the relevant menu configurations are displayed for
148 config GENERIC_HWEIGHT
152 config GENERIC_CALIBRATE_DELAY
156 config ARCH_MAY_HAVE_PC_FDC
162 config NEED_DMA_MAP_STATE
165 config ARCH_HAS_DMA_SET_COHERENT_MASK
168 config GENERIC_ISA_DMA
174 config NEED_RET_TO_USER
182 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
183 default DRAM_BASE if REMAP_VECTORS_TO_RAM
186 The base address of exception vectors.
188 config ARM_PATCH_PHYS_VIRT
189 bool "Patch physical to virtual translations at runtime" if EMBEDDED
191 depends on !XIP_KERNEL && MMU
192 depends on !ARCH_REALVIEW || !SPARSEMEM
194 Patch phys-to-virt and virt-to-phys translation functions at
195 boot and module load time according to the position of the
196 kernel in system memory.
198 This can only be used with non-XIP MMU kernels where the base
199 of physical memory is at a 16MB boundary.
201 Only disable this option if you know that you do not require
202 this feature (eg, building a kernel for a single machine) and
203 you need to shrink the kernel to the minimal size.
205 config NEED_MACH_IO_H
208 Select this when mach/io.h is required to provide special
209 definitions for this platform. The need for mach/io.h should
210 be avoided when possible.
212 config NEED_MACH_MEMORY_H
215 Select this when mach/memory.h is required to provide special
216 definitions for this platform. The need for mach/memory.h should
217 be avoided when possible.
220 hex "Physical address of main memory" if MMU
221 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
222 default DRAM_BASE if !MMU
224 Please provide the physical address corresponding to the
225 location of main memory in your system.
231 source "init/Kconfig"
233 source "kernel/Kconfig.freezer"
238 bool "MMU-based Paged Memory Management Support"
241 Select if you want MMU-based virtualised addressing space
242 support by paged memory management. If unsure, say 'Y'.
245 # The "ARM system type" choice list is ordered alphabetically by option
246 # text. Please add new entries in the option alphabetic order.
249 prompt "ARM system type"
250 default ARCH_VERSATILE
253 bool "Altera SOCFPGA family"
254 select ARCH_WANT_OPTIONAL_GPIOLIB
262 select DW_APB_TIMER_OF
263 select GENERIC_CLOCKEVENTS
264 select GPIO_PL061 if GPIOLIB
269 This enables support for Altera SOCFPGA Cyclone V platform
271 config ARCH_INTEGRATOR
272 bool "ARM Ltd. Integrator family"
274 select ARCH_HAS_CPUFREQ
279 select GENERIC_CLOCKEVENTS
280 select PLAT_VERSATILE
281 select PLAT_VERSATILE_FPGA_IRQ
282 select NEED_MACH_IO_H
283 select NEED_MACH_MEMORY_H
285 select MULTI_IRQ_HANDLER
287 Support for ARM's Integrator platform.
290 bool "ARM Ltd. RealView family"
293 select HAVE_MACH_CLKDEV
295 select GENERIC_CLOCKEVENTS
296 select ARCH_WANT_OPTIONAL_GPIOLIB
297 select PLAT_VERSATILE
298 select PLAT_VERSATILE_CLOCK
299 select PLAT_VERSATILE_CLCD
300 select ARM_TIMER_SP804
301 select GPIO_PL061 if GPIOLIB
302 select NEED_MACH_MEMORY_H
304 This enables support for ARM Ltd RealView boards.
306 config ARCH_VERSATILE
307 bool "ARM Ltd. Versatile family"
311 select HAVE_MACH_CLKDEV
313 select GENERIC_CLOCKEVENTS
314 select ARCH_WANT_OPTIONAL_GPIOLIB
315 select NEED_MACH_IO_H if PCI
316 select PLAT_VERSATILE
317 select PLAT_VERSATILE_CLOCK
318 select PLAT_VERSATILE_CLCD
319 select PLAT_VERSATILE_FPGA_IRQ
320 select ARM_TIMER_SP804
322 This enables support for ARM Ltd Versatile board.
325 bool "ARM Ltd. Versatile Express family"
326 select ARCH_WANT_OPTIONAL_GPIOLIB
328 select ARM_TIMER_SP804
331 select GENERIC_CLOCKEVENTS
333 select HAVE_PATA_PLATFORM
336 select PLAT_VERSATILE
337 select PLAT_VERSATILE_CLCD
338 select REGULATOR_FIXED_VOLTAGE if REGULATOR
340 This enables support for the ARM Ltd Versatile Express boards.
344 select ARCH_REQUIRE_GPIOLIB
348 select NEED_MACH_IO_H if PCCARD
350 This enables support for systems based on Atmel
351 AT91RM9200 and AT91SAM9* processors.
354 bool "Broadcom BCMRING"
358 select ARM_TIMER_SP804
360 select GENERIC_CLOCKEVENTS
361 select ARCH_WANT_OPTIONAL_GPIOLIB
363 Support for Broadcom's BCMRing platform.
366 bool "Calxeda Highbank-based"
367 select ARCH_WANT_OPTIONAL_GPIOLIB
370 select ARM_TIMER_SP804
375 select GENERIC_CLOCKEVENTS
381 Support for the Calxeda Highbank SoC based boards.
384 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
386 select ARCH_USES_GETTIMEOFFSET
387 select NEED_MACH_MEMORY_H
389 Support for Cirrus Logic 711x/721x/731x based boards.
392 bool "Cavium Networks CNS3XXX family"
394 select GENERIC_CLOCKEVENTS
396 select MIGHT_HAVE_CACHE_L2X0
397 select MIGHT_HAVE_PCI
398 select PCI_DOMAINS if PCI
400 Support for Cavium Networks CNS3XXX platform.
403 bool "Cortina Systems Gemini"
405 select ARCH_REQUIRE_GPIOLIB
406 select ARCH_USES_GETTIMEOFFSET
408 Support for the Cortina Systems Gemini family SoCs
411 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
414 select ARCH_REQUIRE_GPIOLIB
415 select GENERIC_CLOCKEVENTS
417 select GENERIC_IRQ_CHIP
418 select MIGHT_HAVE_CACHE_L2X0
424 Support for CSR SiRFSoC ARM Cortex A9 Platform
431 select ARCH_USES_GETTIMEOFFSET
432 select NEED_MACH_IO_H
433 select NEED_MACH_MEMORY_H
435 This is an evaluation board for the StrongARM processor available
436 from Digital. It has limited hardware on-board, including an
437 Ethernet interface, two PCMCIA sockets, two serial ports and a
446 select ARCH_REQUIRE_GPIOLIB
447 select ARCH_HAS_HOLES_MEMORYMODEL
448 select ARCH_USES_GETTIMEOFFSET
449 select NEED_MACH_MEMORY_H
451 This enables support for the Cirrus EP93xx series of CPUs.
453 config ARCH_FOOTBRIDGE
457 select GENERIC_CLOCKEVENTS
459 select NEED_MACH_IO_H
460 select NEED_MACH_MEMORY_H
462 Support for systems based on the DC21285 companion chip
463 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
466 bool "Freescale MXC/iMX-based"
467 select GENERIC_CLOCKEVENTS
468 select ARCH_REQUIRE_GPIOLIB
471 select GENERIC_IRQ_CHIP
472 select MULTI_IRQ_HANDLER
476 Support for Freescale MXC/iMX-based family of processors
479 bool "Freescale MXS-based"
480 select GENERIC_CLOCKEVENTS
481 select ARCH_REQUIRE_GPIOLIB
485 select HAVE_CLK_PREPARE
489 Support for Freescale MXS-based family of processors
492 bool "Hilscher NetX based"
496 select GENERIC_CLOCKEVENTS
498 This enables support for systems based on the Hilscher NetX Soc
501 bool "Hynix HMS720x-based"
504 select ARCH_USES_GETTIMEOFFSET
506 This enables support for systems based on the Hynix HMS720x
514 select ARCH_SUPPORTS_MSI
516 select NEED_MACH_IO_H
517 select NEED_MACH_MEMORY_H
518 select NEED_RET_TO_USER
520 Support for Intel's IOP13XX (XScale) family of processors.
526 select NEED_MACH_IO_H
527 select NEED_RET_TO_USER
530 select ARCH_REQUIRE_GPIOLIB
532 Support for Intel's 80219 and IOP32X (XScale) family of
539 select NEED_MACH_IO_H
540 select NEED_RET_TO_USER
543 select ARCH_REQUIRE_GPIOLIB
545 Support for Intel's IOP33X (XScale) family of processors.
550 select ARCH_HAS_DMA_SET_COHERENT_MASK
553 select ARCH_REQUIRE_GPIOLIB
554 select GENERIC_CLOCKEVENTS
555 select MIGHT_HAVE_PCI
556 select NEED_MACH_IO_H
557 select DMABOUNCE if PCI
559 Support for Intel's IXP4XX (XScale) family of processors.
562 bool "Marvell SOCs with Device Tree support"
563 select GENERIC_CLOCKEVENTS
564 select MULTI_IRQ_HANDLER
567 select GENERIC_IRQ_CHIP
571 Support for the Marvell SoC Family with device tree support
577 select ARCH_REQUIRE_GPIOLIB
578 select GENERIC_CLOCKEVENTS
579 select NEED_MACH_IO_H
582 Support for the Marvell Dove SoC 88AP510
585 bool "Marvell Kirkwood"
588 select ARCH_REQUIRE_GPIOLIB
589 select GENERIC_CLOCKEVENTS
590 select NEED_MACH_IO_H
593 Support for the following Marvell Kirkwood series SoCs:
594 88F6180, 88F6192 and 88F6281.
600 select ARCH_REQUIRE_GPIOLIB
603 select USB_ARCH_HAS_OHCI
605 select GENERIC_CLOCKEVENTS
609 Support for the NXP LPC32XX family of processors
612 bool "Marvell MV78xx0"
615 select ARCH_REQUIRE_GPIOLIB
616 select GENERIC_CLOCKEVENTS
617 select NEED_MACH_IO_H
620 Support for the following Marvell MV78xx0 series SoCs:
628 select ARCH_REQUIRE_GPIOLIB
629 select GENERIC_CLOCKEVENTS
630 select NEED_MACH_IO_H
633 Support for the following Marvell Orion 5x series SoCs:
634 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
635 Orion-2 (5281), Orion-1-90 (6183).
638 bool "Marvell PXA168/910/MMP2"
640 select ARCH_REQUIRE_GPIOLIB
642 select GENERIC_CLOCKEVENTS
647 select GENERIC_ALLOCATOR
649 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
652 bool "Micrel/Kendin KS8695"
654 select ARCH_REQUIRE_GPIOLIB
655 select ARCH_USES_GETTIMEOFFSET
656 select NEED_MACH_MEMORY_H
658 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
659 System-on-Chip devices.
662 bool "Nuvoton W90X900 CPU"
664 select ARCH_REQUIRE_GPIOLIB
667 select GENERIC_CLOCKEVENTS
669 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
670 At present, the w90x900 has been renamed nuc900, regarding
671 the ARM series product line, you can login the following
672 link address to know more.
674 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
675 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
681 select GENERIC_CLOCKEVENTS
685 select MIGHT_HAVE_CACHE_L2X0
686 select NEED_MACH_IO_H if PCI
687 select ARCH_HAS_CPUFREQ
690 This enables support for NVIDIA Tegra based systems (Tegra APX,
691 Tegra 6xx and Tegra 2 series).
693 config ARCH_PICOXCELL
694 bool "Picochip picoXcell"
695 select ARCH_REQUIRE_GPIOLIB
696 select ARM_PATCH_PHYS_VIRT
700 select DW_APB_TIMER_OF
701 select GENERIC_CLOCKEVENTS
708 This enables support for systems based on the Picochip picoXcell
709 family of Femtocell devices. The picoxcell support requires device tree
713 bool "Philips Nexperia PNX4008 Mobile"
716 select ARCH_USES_GETTIMEOFFSET
718 This enables support for Philips PNX4008 mobile platform.
721 bool "PXA2xx/PXA3xx-based"
724 select ARCH_HAS_CPUFREQ
727 select ARCH_REQUIRE_GPIOLIB
728 select GENERIC_CLOCKEVENTS
733 select MULTI_IRQ_HANDLER
734 select ARM_CPU_SUSPEND if PM
737 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
742 select GENERIC_CLOCKEVENTS
743 select ARCH_REQUIRE_GPIOLIB
746 Support for Qualcomm MSM/QSD based systems. This runs on the
747 apps processor of the MSM/QSD and depends on a shared memory
748 interface to the modem processor which runs the baseband
749 stack and controls some vital subsystems
750 (clock and power control, etc).
753 bool "Renesas SH-Mobile / R-Mobile"
756 select HAVE_MACH_CLKDEV
758 select GENERIC_CLOCKEVENTS
759 select MIGHT_HAVE_CACHE_L2X0
762 select MULTI_IRQ_HANDLER
763 select PM_GENERIC_DOMAINS if PM
764 select NEED_MACH_MEMORY_H
766 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
772 select ARCH_MAY_HAVE_PC_FDC
773 select HAVE_PATA_PLATFORM
776 select ARCH_SPARSEMEM_ENABLE
777 select ARCH_USES_GETTIMEOFFSET
779 select NEED_MACH_IO_H
780 select NEED_MACH_MEMORY_H
782 On the Acorn Risc-PC, Linux can support the internal IDE disk and
783 CD-ROM interface, serial and parallel port, and the floppy drive.
790 select ARCH_SPARSEMEM_ENABLE
792 select ARCH_HAS_CPUFREQ
794 select GENERIC_CLOCKEVENTS
796 select ARCH_REQUIRE_GPIOLIB
798 select NEED_MACH_MEMORY_H
801 Support for StrongARM 11x0 based boards.
804 bool "Samsung S3C24XX SoCs"
806 select ARCH_HAS_CPUFREQ
809 select ARCH_USES_GETTIMEOFFSET
810 select HAVE_S3C2410_I2C if I2C
811 select HAVE_S3C_RTC if RTC_CLASS
812 select HAVE_S3C2410_WATCHDOG if WATCHDOG
813 select NEED_MACH_IO_H
815 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
816 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
817 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
818 Samsung SMDK2410 development board (and derivatives).
821 bool "Samsung S3C64XX"
829 select ARCH_USES_GETTIMEOFFSET
830 select ARCH_HAS_CPUFREQ
831 select ARCH_REQUIRE_GPIOLIB
832 select SAMSUNG_CLKSRC
833 select SAMSUNG_IRQ_VIC_TIMER
834 select S3C_GPIO_TRACK
836 select USB_ARCH_HAS_OHCI
837 select SAMSUNG_GPIOLIB_4BIT
838 select HAVE_S3C2410_I2C if I2C
839 select HAVE_S3C2410_WATCHDOG if WATCHDOG
841 Samsung S3C64XX series based systems
844 bool "Samsung S5P6440 S5P6450"
850 select HAVE_S3C2410_WATCHDOG if WATCHDOG
851 select GENERIC_CLOCKEVENTS
852 select HAVE_S3C2410_I2C if I2C
853 select HAVE_S3C_RTC if RTC_CLASS
855 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
859 bool "Samsung S5PC100"
864 select ARCH_USES_GETTIMEOFFSET
865 select HAVE_S3C2410_I2C if I2C
866 select HAVE_S3C_RTC if RTC_CLASS
867 select HAVE_S3C2410_WATCHDOG if WATCHDOG
869 Samsung S5PC100 series based systems
872 bool "Samsung S5PV210/S5PC110"
874 select ARCH_SPARSEMEM_ENABLE
875 select ARCH_HAS_HOLES_MEMORYMODEL
880 select ARCH_HAS_CPUFREQ
881 select GENERIC_CLOCKEVENTS
882 select HAVE_S3C2410_I2C if I2C
883 select HAVE_S3C_RTC if RTC_CLASS
884 select HAVE_S3C2410_WATCHDOG if WATCHDOG
885 select NEED_MACH_MEMORY_H
887 Samsung S5PV210/S5PC110 series based systems
890 bool "SAMSUNG EXYNOS"
892 select ARCH_SPARSEMEM_ENABLE
893 select ARCH_HAS_HOLES_MEMORYMODEL
897 select ARCH_HAS_CPUFREQ
898 select GENERIC_CLOCKEVENTS
899 select HAVE_S3C_RTC if RTC_CLASS
900 select HAVE_S3C2410_I2C if I2C
901 select HAVE_S3C2410_WATCHDOG if WATCHDOG
902 select NEED_MACH_MEMORY_H
904 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
913 select ARCH_USES_GETTIMEOFFSET
914 select NEED_MACH_MEMORY_H
915 select NEED_MACH_IO_H
917 Support for the StrongARM based Digital DNARD machine, also known
918 as "Shark" (<http://www.shark-linux.de/shark.html>).
921 bool "ST-Ericsson U300 Series"
927 select ARM_PATCH_PHYS_VIRT
929 select GENERIC_CLOCKEVENTS
933 select ARCH_REQUIRE_GPIOLIB
935 Support for ST-Ericsson U300 series mobile platforms.
938 bool "ST-Ericsson U8500 Series"
942 select GENERIC_CLOCKEVENTS
944 select ARCH_REQUIRE_GPIOLIB
945 select ARCH_HAS_CPUFREQ
947 select MIGHT_HAVE_CACHE_L2X0
949 Support for ST-Ericsson's Ux500 architecture
952 bool "STMicroelectronics Nomadik"
957 select GENERIC_CLOCKEVENTS
959 select MIGHT_HAVE_CACHE_L2X0
960 select ARCH_REQUIRE_GPIOLIB
962 Support for the Nomadik platform by ST-Ericsson
966 select GENERIC_CLOCKEVENTS
967 select ARCH_REQUIRE_GPIOLIB
971 select GENERIC_ALLOCATOR
972 select GENERIC_IRQ_CHIP
973 select ARCH_HAS_HOLES_MEMORYMODEL
975 Support for TI's DaVinci platform.
981 select ARCH_REQUIRE_GPIOLIB
982 select ARCH_HAS_CPUFREQ
984 select GENERIC_CLOCKEVENTS
985 select ARCH_HAS_HOLES_MEMORYMODEL
987 Support for TI's OMAP platform (OMAP1/2/3/4).
992 select ARCH_REQUIRE_GPIOLIB
996 select GENERIC_CLOCKEVENTS
999 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
1002 bool "VIA/WonderMedia 85xx"
1005 select ARCH_HAS_CPUFREQ
1006 select GENERIC_CLOCKEVENTS
1007 select ARCH_REQUIRE_GPIOLIB
1011 select CLKDEV_LOOKUP
1013 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1016 bool "Xilinx Zynq ARM Cortex A9 Platform"
1018 select GENERIC_CLOCKEVENTS
1019 select CLKDEV_LOOKUP
1023 select MIGHT_HAVE_CACHE_L2X0
1026 Support for Xilinx Zynq ARM Cortex A9 Platform
1030 # This is sorted alphabetically by mach-* pathname. However, plat-*
1031 # Kconfigs may be included either alphabetically (according to the
1032 # plat- suffix) or along side the corresponding mach-* source.
1034 source "arch/arm/mach-mvebu/Kconfig"
1036 source "arch/arm/mach-at91/Kconfig"
1038 source "arch/arm/mach-bcmring/Kconfig"
1040 source "arch/arm/mach-clps711x/Kconfig"
1042 source "arch/arm/mach-cns3xxx/Kconfig"
1044 source "arch/arm/mach-davinci/Kconfig"
1046 source "arch/arm/mach-dove/Kconfig"
1048 source "arch/arm/mach-ep93xx/Kconfig"
1050 source "arch/arm/mach-footbridge/Kconfig"
1052 source "arch/arm/mach-gemini/Kconfig"
1054 source "arch/arm/mach-h720x/Kconfig"
1056 source "arch/arm/mach-integrator/Kconfig"
1058 source "arch/arm/mach-iop32x/Kconfig"
1060 source "arch/arm/mach-iop33x/Kconfig"
1062 source "arch/arm/mach-iop13xx/Kconfig"
1064 source "arch/arm/mach-ixp4xx/Kconfig"
1066 source "arch/arm/mach-kirkwood/Kconfig"
1068 source "arch/arm/mach-ks8695/Kconfig"
1070 source "arch/arm/mach-msm/Kconfig"
1072 source "arch/arm/mach-mv78xx0/Kconfig"
1074 source "arch/arm/plat-mxc/Kconfig"
1076 source "arch/arm/mach-mxs/Kconfig"
1078 source "arch/arm/mach-netx/Kconfig"
1080 source "arch/arm/mach-nomadik/Kconfig"
1081 source "arch/arm/plat-nomadik/Kconfig"
1083 source "arch/arm/plat-omap/Kconfig"
1085 source "arch/arm/mach-omap1/Kconfig"
1087 source "arch/arm/mach-omap2/Kconfig"
1089 source "arch/arm/mach-orion5x/Kconfig"
1091 source "arch/arm/mach-pxa/Kconfig"
1092 source "arch/arm/plat-pxa/Kconfig"
1094 source "arch/arm/mach-mmp/Kconfig"
1096 source "arch/arm/mach-realview/Kconfig"
1098 source "arch/arm/mach-sa1100/Kconfig"
1100 source "arch/arm/plat-samsung/Kconfig"
1101 source "arch/arm/plat-s3c24xx/Kconfig"
1103 source "arch/arm/plat-spear/Kconfig"
1105 source "arch/arm/mach-s3c24xx/Kconfig"
1107 source "arch/arm/mach-s3c2412/Kconfig"
1108 source "arch/arm/mach-s3c2440/Kconfig"
1112 source "arch/arm/mach-s3c64xx/Kconfig"
1115 source "arch/arm/mach-s5p64x0/Kconfig"
1117 source "arch/arm/mach-s5pc100/Kconfig"
1119 source "arch/arm/mach-s5pv210/Kconfig"
1121 source "arch/arm/mach-exynos/Kconfig"
1123 source "arch/arm/mach-shmobile/Kconfig"
1125 source "arch/arm/mach-tegra/Kconfig"
1127 source "arch/arm/mach-u300/Kconfig"
1129 source "arch/arm/mach-ux500/Kconfig"
1131 source "arch/arm/mach-versatile/Kconfig"
1133 source "arch/arm/mach-vexpress/Kconfig"
1134 source "arch/arm/plat-versatile/Kconfig"
1136 source "arch/arm/mach-w90x900/Kconfig"
1138 # Definitions to make life easier
1144 select GENERIC_CLOCKEVENTS
1149 select GENERIC_IRQ_CHIP
1156 config PLAT_VERSATILE
1159 config ARM_TIMER_SP804
1162 select HAVE_SCHED_CLOCK
1164 source arch/arm/mm/Kconfig
1168 default 16 if ARCH_EP93XX
1172 bool "Enable iWMMXt support"
1173 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1174 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1176 Enable support for iWMMXt context switching at run time if
1177 running on a CPU that supports it.
1181 depends on CPU_XSCALE
1185 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1186 (!ARCH_OMAP3 || OMAP3_EMU)
1190 config MULTI_IRQ_HANDLER
1193 Allow each machine to specify it's own IRQ handler at run time.
1196 source "arch/arm/Kconfig-nommu"
1199 config ARM_ERRATA_326103
1200 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1203 Executing a SWP instruction to read-only memory does not set bit 11
1204 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1205 treat the access as a read, preventing a COW from occurring and
1206 causing the faulting task to livelock.
1208 config ARM_ERRATA_411920
1209 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1210 depends on CPU_V6 || CPU_V6K
1212 Invalidation of the Instruction Cache operation can
1213 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1214 It does not affect the MPCore. This option enables the ARM Ltd.
1215 recommended workaround.
1217 config ARM_ERRATA_430973
1218 bool "ARM errata: Stale prediction on replaced interworking branch"
1221 This option enables the workaround for the 430973 Cortex-A8
1222 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1223 interworking branch is replaced with another code sequence at the
1224 same virtual address, whether due to self-modifying code or virtual
1225 to physical address re-mapping, Cortex-A8 does not recover from the
1226 stale interworking branch prediction. This results in Cortex-A8
1227 executing the new code sequence in the incorrect ARM or Thumb state.
1228 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1229 and also flushes the branch target cache at every context switch.
1230 Note that setting specific bits in the ACTLR register may not be
1231 available in non-secure mode.
1233 config ARM_ERRATA_458693
1234 bool "ARM errata: Processor deadlock when a false hazard is created"
1237 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1238 erratum. For very specific sequences of memory operations, it is
1239 possible for a hazard condition intended for a cache line to instead
1240 be incorrectly associated with a different cache line. This false
1241 hazard might then cause a processor deadlock. The workaround enables
1242 the L1 caching of the NEON accesses and disables the PLD instruction
1243 in the ACTLR register. Note that setting specific bits in the ACTLR
1244 register may not be available in non-secure mode.
1246 config ARM_ERRATA_460075
1247 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1250 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1251 erratum. Any asynchronous access to the L2 cache may encounter a
1252 situation in which recent store transactions to the L2 cache are lost
1253 and overwritten with stale memory contents from external memory. The
1254 workaround disables the write-allocate mode for the L2 cache via the
1255 ACTLR register. Note that setting specific bits in the ACTLR register
1256 may not be available in non-secure mode.
1258 config ARM_ERRATA_742230
1259 bool "ARM errata: DMB operation may be faulty"
1260 depends on CPU_V7 && SMP
1262 This option enables the workaround for the 742230 Cortex-A9
1263 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1264 between two write operations may not ensure the correct visibility
1265 ordering of the two writes. This workaround sets a specific bit in
1266 the diagnostic register of the Cortex-A9 which causes the DMB
1267 instruction to behave as a DSB, ensuring the correct behaviour of
1270 config ARM_ERRATA_742231
1271 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1272 depends on CPU_V7 && SMP
1274 This option enables the workaround for the 742231 Cortex-A9
1275 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1276 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1277 accessing some data located in the same cache line, may get corrupted
1278 data due to bad handling of the address hazard when the line gets
1279 replaced from one of the CPUs at the same time as another CPU is
1280 accessing it. This workaround sets specific bits in the diagnostic
1281 register of the Cortex-A9 which reduces the linefill issuing
1282 capabilities of the processor.
1284 config PL310_ERRATA_588369
1285 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1286 depends on CACHE_L2X0
1288 The PL310 L2 cache controller implements three types of Clean &
1289 Invalidate maintenance operations: by Physical Address
1290 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1291 They are architecturally defined to behave as the execution of a
1292 clean operation followed immediately by an invalidate operation,
1293 both performing to the same memory location. This functionality
1294 is not correctly implemented in PL310 as clean lines are not
1295 invalidated as a result of these operations.
1297 config ARM_ERRATA_720789
1298 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1301 This option enables the workaround for the 720789 Cortex-A9 (prior to
1302 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1303 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1304 As a consequence of this erratum, some TLB entries which should be
1305 invalidated are not, resulting in an incoherency in the system page
1306 tables. The workaround changes the TLB flushing routines to invalidate
1307 entries regardless of the ASID.
1309 config PL310_ERRATA_727915
1310 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1311 depends on CACHE_L2X0
1313 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1314 operation (offset 0x7FC). This operation runs in background so that
1315 PL310 can handle normal accesses while it is in progress. Under very
1316 rare circumstances, due to this erratum, write data can be lost when
1317 PL310 treats a cacheable write transaction during a Clean &
1318 Invalidate by Way operation.
1320 config ARM_ERRATA_743622
1321 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1324 This option enables the workaround for the 743622 Cortex-A9
1325 (r2p*) erratum. Under very rare conditions, a faulty
1326 optimisation in the Cortex-A9 Store Buffer may lead to data
1327 corruption. This workaround sets a specific bit in the diagnostic
1328 register of the Cortex-A9 which disables the Store Buffer
1329 optimisation, preventing the defect from occurring. This has no
1330 visible impact on the overall performance or power consumption of the
1333 config ARM_ERRATA_751472
1334 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1337 This option enables the workaround for the 751472 Cortex-A9 (prior
1338 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1339 completion of a following broadcasted operation if the second
1340 operation is received by a CPU before the ICIALLUIS has completed,
1341 potentially leading to corrupted entries in the cache or TLB.
1343 config PL310_ERRATA_753970
1344 bool "PL310 errata: cache sync operation may be faulty"
1345 depends on CACHE_PL310
1347 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1349 Under some condition the effect of cache sync operation on
1350 the store buffer still remains when the operation completes.
1351 This means that the store buffer is always asked to drain and
1352 this prevents it from merging any further writes. The workaround
1353 is to replace the normal offset of cache sync operation (0x730)
1354 by another offset targeting an unmapped PL310 register 0x740.
1355 This has the same effect as the cache sync operation: store buffer
1356 drain and waiting for all buffers empty.
1358 config ARM_ERRATA_754322
1359 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1362 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1363 r3p*) erratum. A speculative memory access may cause a page table walk
1364 which starts prior to an ASID switch but completes afterwards. This
1365 can populate the micro-TLB with a stale entry which may be hit with
1366 the new ASID. This workaround places two dsb instructions in the mm
1367 switching code so that no page table walks can cross the ASID switch.
1369 config ARM_ERRATA_754327
1370 bool "ARM errata: no automatic Store Buffer drain"
1371 depends on CPU_V7 && SMP
1373 This option enables the workaround for the 754327 Cortex-A9 (prior to
1374 r2p0) erratum. The Store Buffer does not have any automatic draining
1375 mechanism and therefore a livelock may occur if an external agent
1376 continuously polls a memory location waiting to observe an update.
1377 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1378 written polling loops from denying visibility of updates to memory.
1380 config ARM_ERRATA_364296
1381 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1382 depends on CPU_V6 && !SMP
1384 This options enables the workaround for the 364296 ARM1136
1385 r0p2 erratum (possible cache data corruption with
1386 hit-under-miss enabled). It sets the undocumented bit 31 in
1387 the auxiliary control register and the FI bit in the control
1388 register, thus disabling hit-under-miss without putting the
1389 processor into full low interrupt latency mode. ARM11MPCore
1392 config ARM_ERRATA_764369
1393 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1394 depends on CPU_V7 && SMP
1396 This option enables the workaround for erratum 764369
1397 affecting Cortex-A9 MPCore with two or more processors (all
1398 current revisions). Under certain timing circumstances, a data
1399 cache line maintenance operation by MVA targeting an Inner
1400 Shareable memory region may fail to proceed up to either the
1401 Point of Coherency or to the Point of Unification of the
1402 system. This workaround adds a DSB instruction before the
1403 relevant cache maintenance functions and sets a specific bit
1404 in the diagnostic control register of the SCU.
1406 config PL310_ERRATA_769419
1407 bool "PL310 errata: no automatic Store Buffer drain"
1408 depends on CACHE_L2X0
1410 On revisions of the PL310 prior to r3p2, the Store Buffer does
1411 not automatically drain. This can cause normal, non-cacheable
1412 writes to be retained when the memory system is idle, leading
1413 to suboptimal I/O performance for drivers using coherent DMA.
1414 This option adds a write barrier to the cpu_idle loop so that,
1415 on systems with an outer cache, the store buffer is drained
1420 source "arch/arm/common/Kconfig"
1430 Find out whether you have ISA slots on your motherboard. ISA is the
1431 name of a bus system, i.e. the way the CPU talks to the other stuff
1432 inside your box. Other bus systems are PCI, EISA, MicroChannel
1433 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1434 newer boards don't support it. If you have ISA, say Y, otherwise N.
1436 # Select ISA DMA controller support
1441 # Select ISA DMA interface
1446 bool "PCI support" if MIGHT_HAVE_PCI
1448 Find out whether you have a PCI motherboard. PCI is the name of a
1449 bus system, i.e. the way the CPU talks to the other stuff inside
1450 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1451 VESA. If you have PCI, say Y, otherwise N.
1457 config PCI_NANOENGINE
1458 bool "BSE nanoEngine PCI support"
1459 depends on SA1100_NANOENGINE
1461 Enable PCI on the BSE nanoEngine board.
1466 # Select the host bridge type
1467 config PCI_HOST_VIA82C505
1469 depends on PCI && ARCH_SHARK
1472 config PCI_HOST_ITE8152
1474 depends on PCI && MACH_ARMCORE
1478 source "drivers/pci/Kconfig"
1480 source "drivers/pcmcia/Kconfig"
1484 menu "Kernel Features"
1489 This option should be selected by machines which have an SMP-
1492 The only effect of this option is to make the SMP-related
1493 options available to the user for configuration.
1496 bool "Symmetric Multi-Processing"
1497 depends on CPU_V6K || CPU_V7
1498 depends on GENERIC_CLOCKEVENTS
1501 select USE_GENERIC_SMP_HELPERS
1502 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1504 This enables support for systems with more than one CPU. If you have
1505 a system with only one CPU, like most personal computers, say N. If
1506 you have a system with more than one CPU, say Y.
1508 If you say N here, the kernel will run on single and multiprocessor
1509 machines, but will use only one CPU of a multiprocessor machine. If
1510 you say Y here, the kernel will run on many, but not all, single
1511 processor machines. On a single processor machine, the kernel will
1512 run faster if you say N here.
1514 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1515 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1516 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1518 If you don't know what to do here, say N.
1521 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1522 depends on EXPERIMENTAL
1523 depends on SMP && !XIP_KERNEL
1526 SMP kernels contain instructions which fail on non-SMP processors.
1527 Enabling this option allows the kernel to modify itself to make
1528 these instructions safe. Disabling it allows about 1K of space
1531 If you don't know what to do here, say Y.
1533 config ARM_CPU_TOPOLOGY
1534 bool "Support cpu topology definition"
1535 depends on SMP && CPU_V7
1538 Support ARM cpu topology definition. The MPIDR register defines
1539 affinity between processors which is then used to describe the cpu
1540 topology of an ARM System.
1543 bool "Multi-core scheduler support"
1544 depends on ARM_CPU_TOPOLOGY
1546 Multi-core scheduler support improves the CPU scheduler's decision
1547 making when dealing with multi-core CPU chips at a cost of slightly
1548 increased overhead in some places. If unsure say N here.
1551 bool "SMT scheduler support"
1552 depends on ARM_CPU_TOPOLOGY
1554 Improves the CPU scheduler's decision making when dealing with
1555 MultiThreading at a cost of slightly increased overhead in some
1556 places. If unsure say N here.
1561 This option enables support for the ARM system coherency unit
1563 config ARM_ARCH_TIMER
1564 bool "Architected timer support"
1567 This option enables support for the ARM architected timer
1573 This options enables support for the ARM timer and watchdog unit
1576 prompt "Memory split"
1579 Select the desired split between kernel and user memory.
1581 If you are not absolutely sure what you are doing, leave this
1585 bool "3G/1G user/kernel split"
1587 bool "2G/2G user/kernel split"
1589 bool "1G/3G user/kernel split"
1594 default 0x40000000 if VMSPLIT_1G
1595 default 0x80000000 if VMSPLIT_2G
1599 int "Maximum number of CPUs (2-32)"
1605 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1606 depends on SMP && HOTPLUG && EXPERIMENTAL
1608 Say Y here to experiment with turning CPUs off and on. CPUs
1609 can be controlled through /sys/devices/system/cpu.
1612 bool "Use local timer interrupts"
1615 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1617 Enable support for local timers on SMP platforms, rather then the
1618 legacy IPI broadcast method. Local timers allows the system
1619 accounting to be spread across the timer interval, preventing a
1620 "thundering herd" at every timer tick.
1624 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1625 default 355 if ARCH_U8500
1626 default 264 if MACH_H4700
1627 default 512 if SOC_OMAP5
1628 default 288 if ARCH_VT8500
1631 Maximum number of GPIOs in the system.
1633 If unsure, leave the default value.
1635 source kernel/Kconfig.preempt
1639 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1640 ARCH_S5PV210 || ARCH_EXYNOS4
1641 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1642 default AT91_TIMER_HZ if ARCH_AT91
1643 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1646 config THUMB2_KERNEL
1647 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1648 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1650 select ARM_ASM_UNIFIED
1653 By enabling this option, the kernel will be compiled in
1654 Thumb-2 mode. A compiler/assembler that understand the unified
1655 ARM-Thumb syntax is needed.
1659 config THUMB2_AVOID_R_ARM_THM_JUMP11
1660 bool "Work around buggy Thumb-2 short branch relocations in gas"
1661 depends on THUMB2_KERNEL && MODULES
1664 Various binutils versions can resolve Thumb-2 branches to
1665 locally-defined, preemptible global symbols as short-range "b.n"
1666 branch instructions.
1668 This is a problem, because there's no guarantee the final
1669 destination of the symbol, or any candidate locations for a
1670 trampoline, are within range of the branch. For this reason, the
1671 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1672 relocation in modules at all, and it makes little sense to add
1675 The symptom is that the kernel fails with an "unsupported
1676 relocation" error when loading some modules.
1678 Until fixed tools are available, passing
1679 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1680 code which hits this problem, at the cost of a bit of extra runtime
1681 stack usage in some cases.
1683 The problem is described in more detail at:
1684 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1686 Only Thumb-2 kernels are affected.
1688 Unless you are sure your tools don't have this problem, say Y.
1690 config ARM_ASM_UNIFIED
1694 bool "Use the ARM EABI to compile the kernel"
1696 This option allows for the kernel to be compiled using the latest
1697 ARM ABI (aka EABI). This is only useful if you are using a user
1698 space environment that is also compiled with EABI.
1700 Since there are major incompatibilities between the legacy ABI and
1701 EABI, especially with regard to structure member alignment, this
1702 option also changes the kernel syscall calling convention to
1703 disambiguate both ABIs and allow for backward compatibility support
1704 (selected with CONFIG_OABI_COMPAT).
1706 To use this you need GCC version 4.0.0 or later.
1709 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1710 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1713 This option preserves the old syscall interface along with the
1714 new (ARM EABI) one. It also provides a compatibility layer to
1715 intercept syscalls that have structure arguments which layout
1716 in memory differs between the legacy ABI and the new ARM EABI
1717 (only for non "thumb" binaries). This option adds a tiny
1718 overhead to all syscalls and produces a slightly larger kernel.
1719 If you know you'll be using only pure EABI user space then you
1720 can say N here. If this option is not selected and you attempt
1721 to execute a legacy ABI binary then the result will be
1722 UNPREDICTABLE (in fact it can be predicted that it won't work
1723 at all). If in doubt say Y.
1725 config ARCH_HAS_HOLES_MEMORYMODEL
1728 config ARCH_SPARSEMEM_ENABLE
1731 config ARCH_SPARSEMEM_DEFAULT
1732 def_bool ARCH_SPARSEMEM_ENABLE
1734 config ARCH_SELECT_MEMORY_MODEL
1735 def_bool ARCH_SPARSEMEM_ENABLE
1737 config HAVE_ARCH_PFN_VALID
1738 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1741 bool "High Memory Support"
1744 The address space of ARM processors is only 4 Gigabytes large
1745 and it has to accommodate user address space, kernel address
1746 space as well as some memory mapped IO. That means that, if you
1747 have a large amount of physical memory and/or IO, not all of the
1748 memory can be "permanently mapped" by the kernel. The physical
1749 memory that is not permanently mapped is called "high memory".
1751 Depending on the selected kernel/user memory split, minimum
1752 vmalloc space and actual amount of RAM, you may not need this
1753 option which should result in a slightly faster kernel.
1758 bool "Allocate 2nd-level pagetables from highmem"
1761 config HW_PERF_EVENTS
1762 bool "Enable hardware performance counter support for perf events"
1763 depends on PERF_EVENTS && CPU_HAS_PMU
1766 Enable hardware performance counter support for perf events. If
1767 disabled, perf events will use software events only.
1771 config FORCE_MAX_ZONEORDER
1772 int "Maximum zone order" if ARCH_SHMOBILE
1773 range 11 64 if ARCH_SHMOBILE
1774 default "9" if SA1111
1777 The kernel memory allocator divides physically contiguous memory
1778 blocks into "zones", where each zone is a power of two number of
1779 pages. This option selects the largest power of two that the kernel
1780 keeps in the memory allocator. If you need to allocate very large
1781 blocks of physically contiguous memory, then you may need to
1782 increase this value.
1784 This config option is actually maximum order plus one. For example,
1785 a value of 11 means that the largest free memory block is 2^10 pages.
1788 bool "Timer and CPU usage LEDs"
1789 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1790 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1791 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1792 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1793 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1794 ARCH_AT91 || ARCH_DAVINCI || \
1795 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1797 If you say Y here, the LEDs on your machine will be used
1798 to provide useful information about your current system status.
1800 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1801 be able to select which LEDs are active using the options below. If
1802 you are compiling a kernel for the EBSA-110 or the LART however, the
1803 red LED will simply flash regularly to indicate that the system is
1804 still functional. It is safe to say Y here if you have a CATS
1805 system, but the driver will do nothing.
1808 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1809 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1810 || MACH_OMAP_PERSEUS2
1812 depends on !GENERIC_CLOCKEVENTS
1813 default y if ARCH_EBSA110
1815 If you say Y here, one of the system LEDs (the green one on the
1816 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1817 will flash regularly to indicate that the system is still
1818 operational. This is mainly useful to kernel hackers who are
1819 debugging unstable kernels.
1821 The LART uses the same LED for both Timer LED and CPU usage LED
1822 functions. You may choose to use both, but the Timer LED function
1823 will overrule the CPU usage LED.
1826 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1828 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1829 || MACH_OMAP_PERSEUS2
1832 If you say Y here, the red LED will be used to give a good real
1833 time indication of CPU usage, by lighting whenever the idle task
1834 is not currently executing.
1836 The LART uses the same LED for both Timer LED and CPU usage LED
1837 functions. You may choose to use both, but the Timer LED function
1838 will overrule the CPU usage LED.
1840 config ALIGNMENT_TRAP
1842 depends on CPU_CP15_MMU
1843 default y if !ARCH_EBSA110
1844 select HAVE_PROC_CPU if PROC_FS
1846 ARM processors cannot fetch/store information which is not
1847 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1848 address divisible by 4. On 32-bit ARM processors, these non-aligned
1849 fetch/store instructions will be emulated in software if you say
1850 here, which has a severe performance impact. This is necessary for
1851 correct operation of some network protocols. With an IP-only
1852 configuration it is safe to say N, otherwise say Y.
1854 config UACCESS_WITH_MEMCPY
1855 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1856 depends on MMU && EXPERIMENTAL
1857 default y if CPU_FEROCEON
1859 Implement faster copy_to_user and clear_user methods for CPU
1860 cores where a 8-word STM instruction give significantly higher
1861 memory write throughput than a sequence of individual 32bit stores.
1863 A possible side effect is a slight increase in scheduling latency
1864 between threads sharing the same address space if they invoke
1865 such copy operations with large buffers.
1867 However, if the CPU data cache is using a write-allocate mode,
1868 this option is unlikely to provide any performance gain.
1872 prompt "Enable seccomp to safely compute untrusted bytecode"
1874 This kernel feature is useful for number crunching applications
1875 that may need to compute untrusted bytecode during their
1876 execution. By using pipes or other transports made available to
1877 the process as file descriptors supporting the read/write
1878 syscalls, it's possible to isolate those applications in
1879 their own address space using seccomp. Once seccomp is
1880 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1881 and the task is only allowed to execute a few safe syscalls
1882 defined by each seccomp mode.
1884 config CC_STACKPROTECTOR
1885 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1886 depends on EXPERIMENTAL
1888 This option turns on the -fstack-protector GCC feature. This
1889 feature puts, at the beginning of functions, a canary value on
1890 the stack just before the return address, and validates
1891 the value just before actually returning. Stack based buffer
1892 overflows (that need to overwrite this return address) now also
1893 overwrite the canary, which gets detected and the attack is then
1894 neutralized via a kernel panic.
1895 This feature requires gcc version 4.2 or above.
1897 config DEPRECATED_PARAM_STRUCT
1898 bool "Provide old way to pass kernel parameters"
1900 This was deprecated in 2001 and announced to live on for 5 years.
1901 Some old boot loaders still use this way.
1908 bool "Flattened Device Tree support"
1910 select OF_EARLY_FLATTREE
1913 Include support for flattened device tree machine descriptions.
1915 # Compressed boot loader in ROM. Yes, we really want to ask about
1916 # TEXT and BSS so we preserve their values in the config files.
1917 config ZBOOT_ROM_TEXT
1918 hex "Compressed ROM boot loader base address"
1921 The physical address at which the ROM-able zImage is to be
1922 placed in the target. Platforms which normally make use of
1923 ROM-able zImage formats normally set this to a suitable
1924 value in their defconfig file.
1926 If ZBOOT_ROM is not enabled, this has no effect.
1928 config ZBOOT_ROM_BSS
1929 hex "Compressed ROM boot loader BSS address"
1932 The base address of an area of read/write memory in the target
1933 for the ROM-able zImage which must be available while the
1934 decompressor is running. It must be large enough to hold the
1935 entire decompressed kernel plus an additional 128 KiB.
1936 Platforms which normally make use of ROM-able zImage formats
1937 normally set this to a suitable value in their defconfig file.
1939 If ZBOOT_ROM is not enabled, this has no effect.
1942 bool "Compressed boot loader in ROM/flash"
1943 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1945 Say Y here if you intend to execute your compressed kernel image
1946 (zImage) directly from ROM or flash. If unsure, say N.
1949 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1950 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1951 default ZBOOT_ROM_NONE
1953 Include experimental SD/MMC loading code in the ROM-able zImage.
1954 With this enabled it is possible to write the ROM-able zImage
1955 kernel image to an MMC or SD card and boot the kernel straight
1956 from the reset vector. At reset the processor Mask ROM will load
1957 the first part of the ROM-able zImage which in turn loads the
1958 rest the kernel image to RAM.
1960 config ZBOOT_ROM_NONE
1961 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1963 Do not load image from SD or MMC
1965 config ZBOOT_ROM_MMCIF
1966 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1968 Load image from MMCIF hardware block.
1970 config ZBOOT_ROM_SH_MOBILE_SDHI
1971 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1973 Load image from SDHI hardware block
1977 config ARM_APPENDED_DTB
1978 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1979 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1981 With this option, the boot code will look for a device tree binary
1982 (DTB) appended to zImage
1983 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1985 This is meant as a backward compatibility convenience for those
1986 systems with a bootloader that can't be upgraded to accommodate
1987 the documented boot protocol using a device tree.
1989 Beware that there is very little in terms of protection against
1990 this option being confused by leftover garbage in memory that might
1991 look like a DTB header after a reboot if no actual DTB is appended
1992 to zImage. Do not leave this option active in a production kernel
1993 if you don't intend to always append a DTB. Proper passing of the
1994 location into r2 of a bootloader provided DTB is always preferable
1997 config ARM_ATAG_DTB_COMPAT
1998 bool "Supplement the appended DTB with traditional ATAG information"
1999 depends on ARM_APPENDED_DTB
2001 Some old bootloaders can't be updated to a DTB capable one, yet
2002 they provide ATAGs with memory configuration, the ramdisk address,
2003 the kernel cmdline string, etc. Such information is dynamically
2004 provided by the bootloader and can't always be stored in a static
2005 DTB. To allow a device tree enabled kernel to be used with such
2006 bootloaders, this option allows zImage to extract the information
2007 from the ATAG list and store it at run time into the appended DTB.
2010 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2011 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2013 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2014 bool "Use bootloader kernel arguments if available"
2016 Uses the command-line options passed by the boot loader instead of
2017 the device tree bootargs property. If the boot loader doesn't provide
2018 any, the device tree bootargs property will be used.
2020 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2021 bool "Extend with bootloader kernel arguments"
2023 The command-line arguments provided by the boot loader will be
2024 appended to the the device tree bootargs property.
2029 string "Default kernel command string"
2032 On some architectures (EBSA110 and CATS), there is currently no way
2033 for the boot loader to pass arguments to the kernel. For these
2034 architectures, you should supply some command-line options at build
2035 time by entering them here. As a minimum, you should specify the
2036 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2039 prompt "Kernel command line type" if CMDLINE != ""
2040 default CMDLINE_FROM_BOOTLOADER
2042 config CMDLINE_FROM_BOOTLOADER
2043 bool "Use bootloader kernel arguments if available"
2045 Uses the command-line options passed by the boot loader. If
2046 the boot loader doesn't provide any, the default kernel command
2047 string provided in CMDLINE will be used.
2049 config CMDLINE_EXTEND
2050 bool "Extend bootloader kernel arguments"
2052 The command-line arguments provided by the boot loader will be
2053 appended to the default kernel command string.
2055 config CMDLINE_FORCE
2056 bool "Always use the default kernel command string"
2058 Always use the default kernel command string, even if the boot
2059 loader passes other arguments to the kernel.
2060 This is useful if you cannot or don't want to change the
2061 command-line options your boot loader passes to the kernel.
2065 bool "Kernel Execute-In-Place from ROM"
2066 depends on !ZBOOT_ROM && !ARM_LPAE
2068 Execute-In-Place allows the kernel to run from non-volatile storage
2069 directly addressable by the CPU, such as NOR flash. This saves RAM
2070 space since the text section of the kernel is not loaded from flash
2071 to RAM. Read-write sections, such as the data section and stack,
2072 are still copied to RAM. The XIP kernel is not compressed since
2073 it has to run directly from flash, so it will take more space to
2074 store it. The flash address used to link the kernel object files,
2075 and for storing it, is configuration dependent. Therefore, if you
2076 say Y here, you must know the proper physical address where to
2077 store the kernel image depending on your own flash memory usage.
2079 Also note that the make target becomes "make xipImage" rather than
2080 "make zImage" or "make Image". The final kernel binary to put in
2081 ROM memory will be arch/arm/boot/xipImage.
2085 config XIP_PHYS_ADDR
2086 hex "XIP Kernel Physical Location"
2087 depends on XIP_KERNEL
2088 default "0x00080000"
2090 This is the physical address in your flash memory the kernel will
2091 be linked for and stored to. This address is dependent on your
2095 bool "Kexec system call (EXPERIMENTAL)"
2096 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2098 kexec is a system call that implements the ability to shutdown your
2099 current kernel, and to start another kernel. It is like a reboot
2100 but it is independent of the system firmware. And like a reboot
2101 you can start any kernel with it, not just Linux.
2103 It is an ongoing process to be certain the hardware in a machine
2104 is properly shutdown, so do not be surprised if this code does not
2105 initially work for you. It may help to enable device hotplugging
2109 bool "Export atags in procfs"
2113 Should the atags used to boot the kernel be exported in an "atags"
2114 file in procfs. Useful with kexec.
2117 bool "Build kdump crash kernel (EXPERIMENTAL)"
2118 depends on EXPERIMENTAL
2120 Generate crash dump after being started by kexec. This should
2121 be normally only set in special crash dump kernels which are
2122 loaded in the main kernel with kexec-tools into a specially
2123 reserved region and then later executed after a crash by
2124 kdump/kexec. The crash dump kernel must be compiled to a
2125 memory address not used by the main kernel
2127 For more details see Documentation/kdump/kdump.txt
2129 config AUTO_ZRELADDR
2130 bool "Auto calculation of the decompressed kernel image address"
2131 depends on !ZBOOT_ROM && !ARCH_U300
2133 ZRELADDR is the physical address where the decompressed kernel
2134 image will be placed. If AUTO_ZRELADDR is selected, the address
2135 will be determined at run-time by masking the current IP with
2136 0xf8000000. This assumes the zImage being placed in the first 128MB
2137 from start of memory.
2141 menu "CPU Power Management"
2145 source "drivers/cpufreq/Kconfig"
2148 tristate "CPUfreq driver for i.MX CPUs"
2149 depends on ARCH_MXC && CPU_FREQ
2150 select CPU_FREQ_TABLE
2152 This enables the CPUfreq driver for i.MX CPUs.
2154 config CPU_FREQ_SA1100
2157 config CPU_FREQ_SA1110
2160 config CPU_FREQ_INTEGRATOR
2161 tristate "CPUfreq driver for ARM Integrator CPUs"
2162 depends on ARCH_INTEGRATOR && CPU_FREQ
2165 This enables the CPUfreq driver for ARM Integrator CPUs.
2167 For details, take a look at <file:Documentation/cpu-freq>.
2173 depends on CPU_FREQ && ARCH_PXA && PXA25x
2175 select CPU_FREQ_TABLE
2176 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2181 Internal configuration node for common cpufreq on Samsung SoC
2183 config CPU_FREQ_S3C24XX
2184 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2185 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2188 This enables the CPUfreq driver for the Samsung S3C24XX family
2191 For details, take a look at <file:Documentation/cpu-freq>.
2195 config CPU_FREQ_S3C24XX_PLL
2196 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2197 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2199 Compile in support for changing the PLL frequency from the
2200 S3C24XX series CPUfreq driver. The PLL takes time to settle
2201 after a frequency change, so by default it is not enabled.
2203 This also means that the PLL tables for the selected CPU(s) will
2204 be built which may increase the size of the kernel image.
2206 config CPU_FREQ_S3C24XX_DEBUG
2207 bool "Debug CPUfreq Samsung driver core"
2208 depends on CPU_FREQ_S3C24XX
2210 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2212 config CPU_FREQ_S3C24XX_IODEBUG
2213 bool "Debug CPUfreq Samsung driver IO timing"
2214 depends on CPU_FREQ_S3C24XX
2216 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2218 config CPU_FREQ_S3C24XX_DEBUGFS
2219 bool "Export debugfs for CPUFreq"
2220 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2222 Export status information via debugfs.
2226 source "drivers/cpuidle/Kconfig"
2230 menu "Floating point emulation"
2232 comment "At least one emulation must be selected"
2235 bool "NWFPE math emulation"
2236 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2238 Say Y to include the NWFPE floating point emulator in the kernel.
2239 This is necessary to run most binaries. Linux does not currently
2240 support floating point hardware so you need to say Y here even if
2241 your machine has an FPA or floating point co-processor podule.
2243 You may say N here if you are going to load the Acorn FPEmulator
2244 early in the bootup.
2247 bool "Support extended precision"
2248 depends on FPE_NWFPE
2250 Say Y to include 80-bit support in the kernel floating-point
2251 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2252 Note that gcc does not generate 80-bit operations by default,
2253 so in most cases this option only enlarges the size of the
2254 floating point emulator without any good reason.
2256 You almost surely want to say N here.
2259 bool "FastFPE math emulation (EXPERIMENTAL)"
2260 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2262 Say Y here to include the FAST floating point emulator in the kernel.
2263 This is an experimental much faster emulator which now also has full
2264 precision for the mantissa. It does not support any exceptions.
2265 It is very simple, and approximately 3-6 times faster than NWFPE.
2267 It should be sufficient for most programs. It may be not suitable
2268 for scientific calculations, but you have to check this for yourself.
2269 If you do not feel you need a faster FP emulation you should better
2273 bool "VFP-format floating point maths"
2274 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2276 Say Y to include VFP support code in the kernel. This is needed
2277 if your hardware includes a VFP unit.
2279 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2280 release notes and additional status information.
2282 Say N if your target does not have VFP hardware.
2290 bool "Advanced SIMD (NEON) Extension support"
2291 depends on VFPv3 && CPU_V7
2293 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2298 menu "Userspace binary formats"
2300 source "fs/Kconfig.binfmt"
2303 tristate "RISC OS personality"
2306 Say Y here to include the kernel code necessary if you want to run
2307 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2308 experimental; if this sounds frightening, say N and sleep in peace.
2309 You can also say M here to compile this support as a module (which
2310 will be called arthur).
2314 menu "Power management options"
2316 source "kernel/power/Kconfig"
2318 config ARCH_SUSPEND_POSSIBLE
2319 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2320 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2321 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2324 config ARM_CPU_SUSPEND
2329 source "net/Kconfig"
2331 source "drivers/Kconfig"
2335 source "arch/arm/Kconfig.debug"
2337 source "security/Kconfig"
2339 source "crypto/Kconfig"
2341 source "lib/Kconfig"