arch/alpha/kernel/sys_noritake.c

   1 /*
   2  *      linux/arch/alpha/kernel/sys_noritake.c
   3  *
   4  *      Copyright (C) 1995 David A Rusling
   5  *      Copyright (C) 1996 Jay A Estabrook
   6  *      Copyright (C) 1998, 1999 Richard Henderson
   7  *
   8  * Code supporting the NORITAKE (AlphaServer 1000A),
   9  * CORELLE (AlphaServer 800), and ALCOR Primo (AlphaStation 600A).
  10  */
  11
  12 #include <linux/config.h>
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/mm.h>
  16 #include <linux/sched.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19 #include <linux/bitops.h>
  20
  21 #include <asm/ptrace.h>
  22 #include <asm/system.h>
  23 #include <asm/dma.h>
  24 #include <asm/irq.h>
  25 #include <asm/mmu_context.h>
  26 #include <asm/io.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/core_apecs.h>
  29 #include <asm/core_cia.h>
  30 #include <asm/tlbflush.h>
  31
  32 #include "proto.h"
  33 #include "irq_impl.h"
  34 #include "pci_impl.h"
  35 #include "machvec_impl.h"
  36
  37 /* Note mask bit is true for ENABLED irqs.  */
  38 static int cached_irq_mask;
  39
  40 static inline void
  41 noritake_update_irq_hw(int irq, int mask)
  42 {
  43         int port = 0x54a;
  44         if (irq >= 32) {
  45             mask >>= 16;
  46             port = 0x54c;
  47         }
  48         outw(mask, port);
  49 }
  50
  51 static void
  52 noritake_enable_irq(unsigned int irq)
  53 {
  54         noritake_update_irq_hw(irq, cached_irq_mask |= 1 << (irq - 16));
  55 }
  56
  57 static void
  58 noritake_disable_irq(unsigned int irq)
  59 {
  60         noritake_update_irq_hw(irq, cached_irq_mask &= ~(1 << (irq - 16)));
  61 }
  62
  63 static unsigned int
  64 noritake_startup_irq(unsigned int irq)
  65 {
  66         noritake_enable_irq(irq);
  67         return 0;
  68 }
  69
  70 static struct hw_interrupt_type noritake_irq_type = {
  71         .typename       = "NORITAKE",
  72         .startup        = noritake_startup_irq,
  73         .shutdown       = noritake_disable_irq,
  74         .enable         = noritake_enable_irq,
  75         .disable        = noritake_disable_irq,
  76         .ack            = noritake_disable_irq,
  77         .end            = noritake_enable_irq,
  78 };
  79
  80 static void
  81 noritake_device_interrupt(unsigned long vector, struct pt_regs *regs)
  82 {
  83         unsigned long pld;
  84         unsigned int i;
  85
  86         /* Read the interrupt summary registers of NORITAKE */
  87         pld = (((unsigned long) inw(0x54c) << 32)
  88                | ((unsigned long) inw(0x54a) << 16)
  89                | ((unsigned long) inb(0xa0) << 8)
  90                | inb(0x20));
  91
  92         /*
  93          * Now for every possible bit set, work through them and call
  94          * the appropriate interrupt handler.
  95          */
  96         while (pld) {
  97                 i = ffz(~pld);
  98                 pld &= pld - 1; /* clear least bit set */
  99                 if (i < 16) {
 100                         isa_device_interrupt(vector, regs);
 101                 } else {
 102                         handle_irq(i, regs);
 103                 }
 104         }
 105 }
 106
 107 static void
 108 noritake_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
 109 {
 110         int irq;
 111
 112         irq = (vector - 0x800) >> 4;
 113
 114         /*
 115          * I really hate to do this, too, but the NORITAKE SRM console also
 116          * reports PCI vectors *lower* than I expected from the bit numbers
 117          * in the documentation.
 118          * But I really don't want to change the fixup code for allocation
 119          * of IRQs, nor the alpha_irq_mask maintenance stuff, both of which
 120          * look nice and clean now.
 121          * So, here's this additional grotty hack... :-(
 122          */
 123         if (irq >= 16)
 124                 irq = irq + 1;
 125
 126         handle_irq(irq, regs);
 127 }
 128
 129 static void __init
 130 noritake_init_irq(void)
 131 {
 132         long i;
 133
 134         if (alpha_using_srm)
 135                 alpha_mv.device_interrupt = noritake_srm_device_interrupt;
 136
 137         outw(0, 0x54a);
 138         outw(0, 0x54c);
 139
 140         for (i = 16; i < 48; ++i) {
 141                 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
 142                 irq_desc[i].handler = &noritake_irq_type;
 143         }
 144
 145         init_i8259a_irqs();
 146         common_init_isa_dma();
 147 }
 148
 149
 150 /*
 151  * PCI Fixup configuration.
 152  *
 153  * Summary @ 0x542, summary register #1:
 154  * Bit      Meaning
 155  * 0        All valid ints from summary regs 2 & 3
 156  * 1        QLOGIC ISP1020A SCSI
 157  * 2        Interrupt Line A from slot 0
 158  * 3        Interrupt Line B from slot 0
 159  * 4        Interrupt Line A from slot 1
 160  * 5        Interrupt line B from slot 1
 161  * 6        Interrupt Line A from slot 2
 162  * 7        Interrupt Line B from slot 2
 163  * 8        Interrupt Line A from slot 3
 164  * 9        Interrupt Line B from slot 3
 165  *10        Interrupt Line A from slot 4
 166  *11        Interrupt Line B from slot 4
 167  *12        Interrupt Line A from slot 5
 168  *13        Interrupt Line B from slot 5
 169  *14        Interrupt Line A from slot 6
 170  *15        Interrupt Line B from slot 6
 171  *
 172  * Summary @ 0x544, summary register #2:
 173  * Bit      Meaning
 174  * 0        OR of all unmasked ints in SR #2
 175  * 1        OR of secondary bus ints
 176  * 2        Interrupt Line C from slot 0
 177  * 3        Interrupt Line D from slot 0
 178  * 4        Interrupt Line C from slot 1
 179  * 5        Interrupt line D from slot 1
 180  * 6        Interrupt Line C from slot 2
 181  * 7        Interrupt Line D from slot 2
 182  * 8        Interrupt Line C from slot 3
 183  * 9        Interrupt Line D from slot 3
 184  *10        Interrupt Line C from slot 4
 185  *11        Interrupt Line D from slot 4
 186  *12        Interrupt Line C from slot 5
 187  *13        Interrupt Line D from slot 5
 188  *14        Interrupt Line C from slot 6
 189  *15        Interrupt Line D from slot 6
 190  *
 191  * The device to slot mapping looks like:
 192  *
 193  * Slot     Device
 194  *  7       Intel PCI-EISA bridge chip
 195  *  8       DEC PCI-PCI bridge chip
 196  * 11       PCI on board slot 0
 197  * 12       PCI on board slot 1
 198  * 13       PCI on board slot 2
 199  *
 200  *
 201  * This two layered interrupt approach means that we allocate IRQ 16 and
 202  * above for PCI interrupts.  The IRQ relates to which bit the interrupt
 203  * comes in on.  This makes interrupt processing much easier.
 204  */
 205
 206 static int __init
 207 noritake_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 208 {
 209         static char irq_tab[15][5] __initdata = {
 210                 /*INT    INTA   INTB   INTC   INTD */
 211                 /* note: IDSELs 16, 17, and 25 are CORELLE only */
 212                 { 16+1,  16+1,  16+1,  16+1,  16+1},  /* IdSel 16,  QLOGIC */
 213                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 17, S3 Trio64 */
 214                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 18,  PCEB */
 215                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 19,  PPB  */
 216                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 20,  ???? */
 217                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 21,  ???? */
 218                 { 16+2,  16+2,  16+3,  32+2,  32+3},  /* IdSel 22,  slot 0 */
 219                 { 16+4,  16+4,  16+5,  32+4,  32+5},  /* IdSel 23,  slot 1 */
 220                 { 16+6,  16+6,  16+7,  32+6,  32+7},  /* IdSel 24,  slot 2 */
 221                 { 16+8,  16+8,  16+9,  32+8,  32+9},  /* IdSel 25,  slot 3 */
 222                 /* The following 5 are actually on PCI bus 1, which is
 223                    across the built-in bridge of the NORITAKE only.  */
 224                 { 16+1,  16+1,  16+1,  16+1,  16+1},  /* IdSel 16,  QLOGIC */
 225                 { 16+8,  16+8,  16+9,  32+8,  32+9},  /* IdSel 17,  slot 3 */
 226                 {16+10, 16+10, 16+11, 32+10, 32+11},  /* IdSel 18,  slot 4 */
 227                 {16+12, 16+12, 16+13, 32+12, 32+13},  /* IdSel 19,  slot 5 */
 228                 {16+14, 16+14, 16+15, 32+14, 32+15},  /* IdSel 20,  slot 6 */
 229         };
 230         const long min_idsel = 5, max_idsel = 19, irqs_per_slot = 5;
 231         return COMMON_TABLE_LOOKUP;
 232 }
 233
 234 static u8 __init
 235 noritake_swizzle(struct pci_dev *dev, u8 *pinp)
 236 {
 237         int slot, pin = *pinp;
 238
 239         if (dev->bus->number == 0) {
 240                 slot = PCI_SLOT(dev->devfn);
 241         }
 242         /* Check for the built-in bridge */
 243         else if (PCI_SLOT(dev->bus->self->devfn) == 8) {
 244                 slot = PCI_SLOT(dev->devfn) + 15; /* WAG! */
 245         }
 246         else
 247         {
 248                 /* Must be a card-based bridge.  */
 249                 do {
 250                         if (PCI_SLOT(dev->bus->self->devfn) == 8) {
 251                                 slot = PCI_SLOT(dev->devfn) + 15;
 252                                 break;
 253                         }
 254                         pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)) ;
 255
 256                         /* Move up the chain of bridges.  */
 257                         dev = dev->bus->self;
 258                         /* Slot of the next bridge.  */
 259                         slot = PCI_SLOT(dev->devfn);
 260                 } while (dev->bus->self);
 261         }
 262         *pinp = pin;
 263         return slot;
 264 }
 265
 266 #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
 267 static void
 268 noritake_apecs_machine_check(unsigned long vector, unsigned long la_ptr,
 269                              struct pt_regs * regs)
 270 {
 271 #define MCHK_NO_DEVSEL 0x205U
 272 #define MCHK_NO_TABT 0x204U
 273
 274         struct el_common *mchk_header;
 275         unsigned int code;
 276
 277         mchk_header = (struct el_common *)la_ptr;
 278
 279         /* Clear the error before any reporting.  */
 280         mb();
 281         mb(); /* magic */
 282         draina();
 283         apecs_pci_clr_err();
 284         wrmces(0x7);
 285         mb();
 286
 287         code = mchk_header->code;
 288         process_mcheck_info(vector, la_ptr, regs, "NORITAKE APECS",
 289                             (mcheck_expected(0)
 290                              && (code == MCHK_NO_DEVSEL
 291                                  || code == MCHK_NO_TABT)));
 292 }
 293 #endif
 294
 295
 296 /*
 297  * The System Vectors
 298  */
 299
 300 #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
 301 struct alpha_machine_vector noritake_mv __initmv = {
 302         .vector_name            = "Noritake",
 303         DO_EV4_MMU,
 304         DO_DEFAULT_RTC,
 305         DO_APECS_IO,
 306         .machine_check          = noritake_apecs_machine_check,
 307         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 308         .min_io_address         = EISA_DEFAULT_IO_BASE,
 309         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 310
 311         .nr_irqs                = 48,
 312         .device_interrupt       = noritake_device_interrupt,
 313
 314         .init_arch              = apecs_init_arch,
 315         .init_irq               = noritake_init_irq,
 316         .init_rtc               = common_init_rtc,
 317         .init_pci               = common_init_pci,
 318         .pci_map_irq            = noritake_map_irq,
 319         .pci_swizzle            = noritake_swizzle,
 320 };
 321 ALIAS_MV(noritake)
 322 #endif
 323
 324 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PRIMO)
 325 struct alpha_machine_vector noritake_primo_mv __initmv = {
 326         .vector_name            = "Noritake-Primo",
 327         DO_EV5_MMU,
 328         DO_DEFAULT_RTC,
 329         DO_CIA_IO,
 330         .machine_check          = cia_machine_check,
 331         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 332         .min_io_address         = EISA_DEFAULT_IO_BASE,
 333         .min_mem_address        = CIA_DEFAULT_MEM_BASE,
 334
 335         .nr_irqs                = 48,
 336         .device_interrupt       = noritake_device_interrupt,
 337
 338         .init_arch              = cia_init_arch,
 339         .init_irq               = noritake_init_irq,
 340         .init_rtc               = common_init_rtc,
 341         .init_pci               = cia_init_pci,
 342         .kill_arch              = cia_kill_arch,
 343         .pci_map_irq            = noritake_map_irq,
 344         .pci_swizzle            = noritake_swizzle,
 345 };
 346 ALIAS_MV(noritake_primo)
 347 #endif