3 This document describes the Linux kernel Makefiles.
10 --- 3.1 Goal definitions
11 --- 3.2 Built-in object goals - obj-y
12 --- 3.3 Loadable module goals - obj-m
13 --- 3.4 Objects which export symbols
14 --- 3.5 Library file goals - lib-y
15 --- 3.6 Descending down in directories
16 --- 3.7 Compilation flags
17 --- 3.8 Command line dependency
18 --- 3.9 Dependency tracking
19 --- 3.10 Special Rules
20 --- 3.11 $(CC) support functions
21 --- 3.12 $(LD) support functions
23 === 4 Host Program support
24 --- 4.1 Simple Host Program
25 --- 4.2 Composite Host Programs
26 --- 4.3 Defining shared libraries
27 --- 4.4 Using C++ for host programs
28 --- 4.5 Controlling compiler options for host programs
29 --- 4.6 When host programs are actually built
30 --- 4.7 Using hostprogs-$(CONFIG_FOO)
32 === 5 Kbuild clean infrastructure
34 === 6 Architecture Makefiles
35 --- 6.1 Set variables to tweak the build to the architecture
36 --- 6.2 Add prerequisites to archprepare:
37 --- 6.3 List directories to visit when descending
38 --- 6.4 Architecture-specific boot images
39 --- 6.5 Building non-kbuild targets
40 --- 6.6 Commands useful for building a boot image
41 --- 6.7 Custom kbuild commands
42 --- 6.8 Preprocessing linker scripts
44 === 7 Kbuild syntax for exported headers
48 --- 7.4 unifdef-y (deprecated)
50 === 8 Kbuild Variables
51 === 9 Makefile language
57 The Makefiles have five parts:
59 Makefile the top Makefile.
60 .config the kernel configuration file.
61 arch/$(ARCH)/Makefile the arch Makefile.
62 scripts/Makefile.* common rules etc. for all kbuild Makefiles.
63 kbuild Makefiles there are about 500 of these.
65 The top Makefile reads the .config file, which comes from the kernel
66 configuration process.
68 The top Makefile is responsible for building two major products: vmlinux
69 (the resident kernel image) and modules (any module files).
70 It builds these goals by recursively descending into the subdirectories of
71 the kernel source tree.
72 The list of subdirectories which are visited depends upon the kernel
73 configuration. The top Makefile textually includes an arch Makefile
74 with the name arch/$(ARCH)/Makefile. The arch Makefile supplies
75 architecture-specific information to the top Makefile.
77 Each subdirectory has a kbuild Makefile which carries out the commands
78 passed down from above. The kbuild Makefile uses information from the
79 .config file to construct various file lists used by kbuild to build
80 any built-in or modular targets.
82 scripts/Makefile.* contains all the definitions/rules etc. that
83 are used to build the kernel based on the kbuild makefiles.
88 People have four different relationships with the kernel Makefiles.
90 *Users* are people who build kernels. These people type commands such as
91 "make menuconfig" or "make". They usually do not read or edit
92 any kernel Makefiles (or any other source files).
94 *Normal developers* are people who work on features such as device
95 drivers, file systems, and network protocols. These people need to
96 maintain the kbuild Makefiles for the subsystem they are
97 working on. In order to do this effectively, they need some overall
98 knowledge about the kernel Makefiles, plus detailed knowledge about the
99 public interface for kbuild.
101 *Arch developers* are people who work on an entire architecture, such
102 as sparc or ia64. Arch developers need to know about the arch Makefile
103 as well as kbuild Makefiles.
105 *Kbuild developers* are people who work on the kernel build system itself.
106 These people need to know about all aspects of the kernel Makefiles.
108 This document is aimed towards normal developers and arch developers.
111 === 3 The kbuild files
113 Most Makefiles within the kernel are kbuild Makefiles that use the
114 kbuild infrastructure. This chapter introduces the syntax used in the
116 The preferred name for the kbuild files are 'Makefile' but 'Kbuild' can
117 be used and if both a 'Makefile' and a 'Kbuild' file exists, then the 'Kbuild'
120 Section 3.1 "Goal definitions" is a quick intro, further chapters provide
121 more details, with real examples.
123 --- 3.1 Goal definitions
125 Goal definitions are the main part (heart) of the kbuild Makefile.
126 These lines define the files to be built, any special compilation
127 options, and any subdirectories to be entered recursively.
129 The most simple kbuild makefile contains one line:
134 This tells kbuild that there is one object in that directory, named
135 foo.o. foo.o will be built from foo.c or foo.S.
137 If foo.o shall be built as a module, the variable obj-m is used.
138 Therefore the following pattern is often used:
141 obj-$(CONFIG_FOO) += foo.o
143 $(CONFIG_FOO) evaluates to either y (for built-in) or m (for module).
144 If CONFIG_FOO is neither y nor m, then the file will not be compiled
147 --- 3.2 Built-in object goals - obj-y
149 The kbuild Makefile specifies object files for vmlinux
150 in the $(obj-y) lists. These lists depend on the kernel
153 Kbuild compiles all the $(obj-y) files. It then calls
154 "$(LD) -r" to merge these files into one built-in.o file.
155 built-in.o is later linked into vmlinux by the parent Makefile.
157 The order of files in $(obj-y) is significant. Duplicates in
158 the lists are allowed: the first instance will be linked into
159 built-in.o and succeeding instances will be ignored.
161 Link order is significant, because certain functions
162 (module_init() / __initcall) will be called during boot in the
163 order they appear. So keep in mind that changing the link
164 order may e.g. change the order in which your SCSI
165 controllers are detected, and thus your disks are renumbered.
168 #drivers/isdn/i4l/Makefile
169 # Makefile for the kernel ISDN subsystem and device drivers.
170 # Each configuration option enables a list of files.
171 obj-$(CONFIG_ISDN) += isdn.o
172 obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o
174 --- 3.3 Loadable module goals - obj-m
176 $(obj-m) specify object files which are built as loadable
179 A module may be built from one source file or several source
180 files. In the case of one source file, the kbuild makefile
181 simply adds the file to $(obj-m).
184 #drivers/isdn/i4l/Makefile
185 obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o
187 Note: In this example $(CONFIG_ISDN_PPP_BSDCOMP) evaluates to 'm'
189 If a kernel module is built from several source files, you specify
190 that you want to build a module in the same way as above; however,
191 kbuild needs to know which object files you want to build your
192 module from, so you have to tell it by setting a $(<module_name>-y)
196 #drivers/isdn/i4l/Makefile
197 obj-$(CONFIG_ISDN_I4L) += isdn.o
198 isdn-y := isdn_net_lib.o isdn_v110.o isdn_common.o
200 In this example, the module name will be isdn.o. Kbuild will
201 compile the objects listed in $(isdn-y) and then run
202 "$(LD) -r" on the list of these files to generate isdn.o.
204 Due to kbuild recognizing $(<module_name>-y) for composite objects,
205 you can use the value of a CONFIG_ symbol to optionally include an
206 object file as part of a composite object.
210 obj-$(CONFIG_EXT2_FS) += ext2.o
211 ext2-y := balloc.o dir.o file.o ialloc.o inode.o ioctl.o \
212 namei.o super.o symlink.o
213 ext2-$(CONFIG_EXT2_FS_XATTR) += xattr.o xattr_user.o \
216 In this example, xattr.o, xattr_user.o and xattr_trusted.o are only
217 part of the composite object ext2.o if $(CONFIG_EXT2_FS_XATTR)
220 Note: Of course, when you are building objects into the kernel,
221 the syntax above will also work. So, if you have CONFIG_EXT2_FS=y,
222 kbuild will build an ext2.o file for you out of the individual
223 parts and then link this into built-in.o, as you would expect.
225 --- 3.4 Objects which export symbols
227 No special notation is required in the makefiles for
228 modules exporting symbols.
230 --- 3.5 Library file goals - lib-y
232 Objects listed with obj-* are used for modules, or
233 combined in a built-in.o for that specific directory.
234 There is also the possibility to list objects that will
235 be included in a library, lib.a.
236 All objects listed with lib-y are combined in a single
237 library for that directory.
238 Objects that are listed in obj-y and additionally listed in
239 lib-y will not be included in the library, since they will
240 be accessible anyway.
241 For consistency, objects listed in lib-m will be included in lib.a.
243 Note that the same kbuild makefile may list files to be built-in
244 and to be part of a library. Therefore the same directory
245 may contain both a built-in.o and a lib.a file.
248 #arch/i386/lib/Makefile
249 lib-y := checksum.o delay.o
251 This will create a library lib.a based on checksum.o and delay.o.
252 For kbuild to actually recognize that there is a lib.a being built,
253 the directory shall be listed in libs-y.
254 See also "6.3 List directories to visit when descending".
256 Use of lib-y is normally restricted to lib/ and arch/*/lib.
258 --- 3.6 Descending down in directories
260 A Makefile is only responsible for building objects in its own
261 directory. Files in subdirectories should be taken care of by
262 Makefiles in these subdirs. The build system will automatically
263 invoke make recursively in subdirectories, provided you let it know of
266 To do so, obj-y and obj-m are used.
267 ext2 lives in a separate directory, and the Makefile present in fs/
268 tells kbuild to descend down using the following assignment.
272 obj-$(CONFIG_EXT2_FS) += ext2/
274 If CONFIG_EXT2_FS is set to either 'y' (built-in) or 'm' (modular)
275 the corresponding obj- variable will be set, and kbuild will descend
276 down in the ext2 directory.
277 Kbuild only uses this information to decide that it needs to visit
278 the directory, it is the Makefile in the subdirectory that
279 specifies what is modules and what is built-in.
281 It is good practice to use a CONFIG_ variable when assigning directory
282 names. This allows kbuild to totally skip the directory if the
283 corresponding CONFIG_ option is neither 'y' nor 'm'.
285 --- 3.7 Compilation flags
287 ccflags-y, asflags-y and ldflags-y
288 The three flags listed above applies only to the kbuild makefile
289 where they are assigned. They are used for all the normal
290 cc, as and ld invocation happenign during a recursive build.
291 Note: Flags with the same behaviour were previously named:
292 EXTRA_CFLAGS, EXTRA_AFLAGS and EXTRA_LDFLAGS.
293 They are yet supported but their use are deprecated.
295 ccflags-y specifies options for compiling C files with $(CC).
298 # drivers/sound/emu10k1/Makefile
299 ccflags-y += -I$(obj)
300 ccflags-$(DEBUG) += -DEMU10K1_DEBUG
303 This variable is necessary because the top Makefile owns the
304 variable $(KBUILD_CFLAGS) and uses it for compilation flags for the
307 asflags-y is a similar string for per-directory options
308 when compiling assembly language source.
311 #arch/x86_64/kernel/Makefile
312 asflags-y := -traditional
315 ldflags-y is a string for per-directory options to $(LD).
318 #arch/m68k/fpsp040/Makefile
321 subdir-ccflags-y, subdir-asflags-y
322 The two flags listed above are similar to ccflags-y and as-falgs-y.
323 The difference is that the subdir- variants has effect for the kbuild
324 file where tey are present and all subdirectories.
325 Options specified using subdir-* are added to the commandline before
326 the options specified using the non-subdir variants.
329 subdir-ccflags-y := -Werror
333 CFLAGS_$@ and AFLAGS_$@ only apply to commands in current
336 $(CFLAGS_$@) specifies per-file options for $(CC). The $@
337 part has a literal value which specifies the file that it is for.
340 # drivers/scsi/Makefile
341 CFLAGS_aha152x.o = -DAHA152X_STAT -DAUTOCONF
342 CFLAGS_gdth.o = # -DDEBUG_GDTH=2 -D__SERIAL__ -D__COM2__ \
344 CFLAGS_seagate.o = -DARBITRATE -DPARITY -DSEAGATE_USE_ASM
346 These three lines specify compilation flags for aha152x.o,
347 gdth.o, and seagate.o
349 $(AFLAGS_$@) is a similar feature for source files in assembly
353 # arch/arm/kernel/Makefile
354 AFLAGS_head-armv.o := -DTEXTADDR=$(TEXTADDR) -traditional
355 AFLAGS_head-armo.o := -DTEXTADDR=$(TEXTADDR) -traditional
357 --- 3.9 Dependency tracking
359 Kbuild tracks dependencies on the following:
360 1) All prerequisite files (both *.c and *.h)
361 2) CONFIG_ options used in all prerequisite files
362 3) Command-line used to compile target
364 Thus, if you change an option to $(CC) all affected files will
367 --- 3.10 Special Rules
369 Special rules are used when the kbuild infrastructure does
370 not provide the required support. A typical example is
371 header files generated during the build process.
372 Another example are the architecture-specific Makefiles which
373 need special rules to prepare boot images etc.
375 Special rules are written as normal Make rules.
376 Kbuild is not executing in the directory where the Makefile is
377 located, so all special rules shall provide a relative
378 path to prerequisite files and target files.
380 Two variables are used when defining special rules:
383 $(src) is a relative path which points to the directory
384 where the Makefile is located. Always use $(src) when
385 referring to files located in the src tree.
388 $(obj) is a relative path which points to the directory
389 where the target is saved. Always use $(obj) when
390 referring to generated files.
393 #drivers/scsi/Makefile
394 $(obj)/53c8xx_d.h: $(src)/53c7,8xx.scr $(src)/script_asm.pl
395 $(CPP) -DCHIP=810 - < $< | ... $(src)/script_asm.pl
397 This is a special rule, following the normal syntax
399 The target file depends on two prerequisite files. References
400 to the target file are prefixed with $(obj), references
401 to prerequisites are referenced with $(src) (because they are not
405 echoing information to user in a rule is often a good practice
406 but when execution "make -s" one does not expect to see any output
407 except for warnings/errors.
408 To support this kbuild define $(kecho) which will echo out the
409 text following $(kecho) to stdout except if "make -s" is used.
412 #arch/blackfin/boot/Makefile
413 $(obj)/vmImage: $(obj)/vmlinux.gz
414 $(call if_changed,uimage)
415 @$(kecho) 'Kernel: $@ is ready'
418 --- 3.11 $(CC) support functions
420 The kernel may be built with several different versions of
421 $(CC), each supporting a unique set of features and options.
422 kbuild provide basic support to check for valid options for $(CC).
423 $(CC) is usually the gcc compiler, but other alternatives are
427 as-option is used to check if $(CC) -- when used to compile
428 assembler (*.S) files -- supports the given option. An optional
429 second option may be specified if the first option is not supported.
433 cflags-y += $(call as-option,-Wa$(comma)-isa=$(isa-y),)
435 In the above example, cflags-y will be assigned the option
436 -Wa$(comma)-isa=$(isa-y) if it is supported by $(CC).
437 The second argument is optional, and if supplied will be used
438 if first argument is not supported.
441 cc-ldoption is used to check if $(CC) when used to link object files
442 supports the given option. An optional second option may be
443 specified if first option are not supported.
446 #arch/i386/kernel/Makefile
447 vsyscall-flags += $(call cc-ldoption, -Wl$(comma)--hash-style=sysv)
449 In the above example, vsyscall-flags will be assigned the option
450 -Wl$(comma)--hash-style=sysv if it is supported by $(CC).
451 The second argument is optional, and if supplied will be used
452 if first argument is not supported.
455 as-instr checks if the assembler reports a specific instruction
456 and then outputs either option1 or option2
457 C escapes are supported in the test instruction
458 Note: as-instr-option uses KBUILD_AFLAGS for $(AS) options
461 cc-option is used to check if $(CC) supports a given option, and not
462 supported to use an optional second option.
466 cflags-y += $(call cc-option,-march=pentium-mmx,-march=i586)
468 In the above example, cflags-y will be assigned the option
469 -march=pentium-mmx if supported by $(CC), otherwise -march=i586.
470 The second argument to cc-option is optional, and if omitted,
471 cflags-y will be assigned no value if first option is not supported.
472 Note: cc-option uses KBUILD_CFLAGS for $(CC) options
475 cc-option-yn is used to check if gcc supports a given option
476 and return 'y' if supported, otherwise 'n'.
480 biarch := $(call cc-option-yn, -m32)
481 aflags-$(biarch) += -a32
482 cflags-$(biarch) += -m32
484 In the above example, $(biarch) is set to y if $(CC) supports the -m32
485 option. When $(biarch) equals 'y', the expanded variables $(aflags-y)
486 and $(cflags-y) will be assigned the values -a32 and -m32,
488 Note: cc-option-yn uses KBUILD_CFLAGS for $(CC) options
491 gcc versions >= 3.0 changed the type of options used to specify
492 alignment of functions, loops etc. $(cc-option-align), when used
493 as prefix to the align options, will select the right prefix:
495 cc-option-align = -malign
497 cc-option-align = -falign
500 KBUILD_CFLAGS += $(cc-option-align)-functions=4
502 In the above example, the option -falign-functions=4 is used for
503 gcc >= 3.00. For gcc < 3.00, -malign-functions=4 is used.
504 Note: cc-option-align uses KBUILD_CFLAGS for $(CC) options
507 cc-version returns a numerical version of the $(CC) compiler version.
508 The format is <major><minor> where both are two digits. So for example
509 gcc 3.41 would return 0341.
510 cc-version is useful when a specific $(CC) version is faulty in one
511 area, for example -mregparm=3 was broken in some gcc versions
512 even though the option was accepted by gcc.
516 cflags-y += $(shell \
517 if [ $(call cc-version) -ge 0300 ] ; then \
518 echo "-mregparm=3"; fi ;)
520 In the above example, -mregparm=3 is only used for gcc version greater
521 than or equal to gcc 3.0.
524 cc-ifversion tests the version of $(CC) and equals last argument if
525 version expression is true.
528 #fs/reiserfs/Makefile
529 ccflags-y := $(call cc-ifversion, -lt, 0402, -O1)
531 In this example, ccflags-y will be assigned the value -O1 if the
532 $(CC) version is less than 4.2.
533 cc-ifversion takes all the shell operators:
534 -eq, -ne, -lt, -le, -gt, and -ge
535 The third parameter may be a text as in this example, but it may also
536 be an expanded variable or a macro.
539 cc-fullversion is useful when the exact version of gcc is needed.
540 One typical use-case is when a specific GCC version is broken.
541 cc-fullversion points out a more specific version than cc-version does.
544 #arch/powerpc/Makefile
545 $(Q)if test "$(call cc-fullversion)" = "040200" ; then \
546 echo -n '*** GCC-4.2.0 cannot compile the 64-bit powerpc ' ; \
550 In this example for a specific GCC version the build will error out explaining
551 to the user why it stops.
554 cc-cross-prefix is used to check if there exists a $(CC) in path with
555 one of the listed prefixes. The first prefix where there exist a
556 prefix$(CC) in the PATH is returned - and if no prefix$(CC) is found
557 then nothing is returned.
558 Additional prefixes are separated by a single space in the
559 call of cc-cross-prefix.
560 This functionality is useful for architecture Makefiles that try
561 to set CROSS_COMPILE to well-known values but may have several
562 values to select between.
563 It is recommended only to try to set CROSS_COMPILE if it is a cross
564 build (host arch is different from target arch). And if CROSS_COMPILE
565 is already set then leave it with the old value.
569 ifneq ($(SUBARCH),$(ARCH))
570 ifeq ($(CROSS_COMPILE),)
571 CROSS_COMPILE := $(call cc-cross-prefix, m68k-linux-gnu-)
575 --- 3.12 $(LD) support functions
578 ld-option is used to check if $(LD) supports the supplied option.
579 ld-option takes two options as arguments.
580 The second argument is an optional option that can be used if the
581 first option is not supported by $(LD).
585 LDFLAGS_vmlinux += $(call really-ld-option, -X)
588 === 4 Host Program support
590 Kbuild supports building executables on the host for use during the
592 Two steps are required in order to use a host executable.
594 The first step is to tell kbuild that a host program exists. This is
595 done utilising the variable hostprogs-y.
597 The second step is to add an explicit dependency to the executable.
598 This can be done in two ways. Either add the dependency in a rule,
599 or utilise the variable $(always).
600 Both possibilities are described in the following.
602 --- 4.1 Simple Host Program
604 In some cases there is a need to compile and run a program on the
605 computer where the build is running.
606 The following line tells kbuild that the program bin2hex shall be
607 built on the build host.
610 hostprogs-y := bin2hex
612 Kbuild assumes in the above example that bin2hex is made from a single
613 c-source file named bin2hex.c located in the same directory as
616 --- 4.2 Composite Host Programs
618 Host programs can be made up based on composite objects.
619 The syntax used to define composite objects for host programs is
620 similar to the syntax used for kernel objects.
621 $(<executable>-objs) lists all objects used to link the final
625 #scripts/lxdialog/Makefile
626 hostprogs-y := lxdialog
627 lxdialog-objs := checklist.o lxdialog.o
629 Objects with extension .o are compiled from the corresponding .c
630 files. In the above example, checklist.c is compiled to checklist.o
631 and lxdialog.c is compiled to lxdialog.o.
632 Finally, the two .o files are linked to the executable, lxdialog.
633 Note: The syntax <executable>-y is not permitted for host-programs.
635 --- 4.3 Defining shared libraries
637 Objects with extension .so are considered shared libraries, and
638 will be compiled as position independent objects.
639 Kbuild provides support for shared libraries, but the usage
641 In the following example the libkconfig.so shared library is used
642 to link the executable conf.
645 #scripts/kconfig/Makefile
647 conf-objs := conf.o libkconfig.so
648 libkconfig-objs := expr.o type.o
650 Shared libraries always require a corresponding -objs line, and
651 in the example above the shared library libkconfig is composed by
652 the two objects expr.o and type.o.
653 expr.o and type.o will be built as position independent code and
654 linked as a shared library libkconfig.so. C++ is not supported for
657 --- 4.4 Using C++ for host programs
659 kbuild offers support for host programs written in C++. This was
660 introduced solely to support kconfig, and is not recommended
664 #scripts/kconfig/Makefile
666 qconf-cxxobjs := qconf.o
668 In the example above the executable is composed of the C++ file
669 qconf.cc - identified by $(qconf-cxxobjs).
671 If qconf is composed by a mixture of .c and .cc files, then an
672 additional line can be used to identify this.
675 #scripts/kconfig/Makefile
677 qconf-cxxobjs := qconf.o
678 qconf-objs := check.o
680 --- 4.5 Controlling compiler options for host programs
682 When compiling host programs, it is possible to set specific flags.
683 The programs will always be compiled utilising $(HOSTCC) passed
684 the options specified in $(HOSTCFLAGS).
685 To set flags that will take effect for all host programs created
686 in that Makefile, use the variable HOST_EXTRACFLAGS.
689 #scripts/lxdialog/Makefile
690 HOST_EXTRACFLAGS += -I/usr/include/ncurses
692 To set specific flags for a single file the following construction
696 #arch/ppc64/boot/Makefile
697 HOSTCFLAGS_piggyback.o := -DKERNELBASE=$(KERNELBASE)
699 It is also possible to specify additional options to the linker.
702 #scripts/kconfig/Makefile
703 HOSTLOADLIBES_qconf := -L$(QTDIR)/lib
705 When linking qconf, it will be passed the extra option
708 --- 4.6 When host programs are actually built
710 Kbuild will only build host-programs when they are referenced
712 This is possible in two ways:
714 (1) List the prerequisite explicitly in a special rule.
717 #drivers/pci/Makefile
718 hostprogs-y := gen-devlist
719 $(obj)/devlist.h: $(src)/pci.ids $(obj)/gen-devlist
720 ( cd $(obj); ./gen-devlist ) < $<
722 The target $(obj)/devlist.h will not be built before
723 $(obj)/gen-devlist is updated. Note that references to
724 the host programs in special rules must be prefixed with $(obj).
727 When there is no suitable special rule, and the host program
728 shall be built when a makefile is entered, the $(always)
729 variable shall be used.
732 #scripts/lxdialog/Makefile
733 hostprogs-y := lxdialog
734 always := $(hostprogs-y)
736 This will tell kbuild to build lxdialog even if not referenced in
739 --- 4.7 Using hostprogs-$(CONFIG_FOO)
741 A typical pattern in a Kbuild file looks like this:
745 hostprogs-$(CONFIG_KALLSYMS) += kallsyms
747 Kbuild knows about both 'y' for built-in and 'm' for module.
748 So if a config symbol evaluate to 'm', kbuild will still build
749 the binary. In other words, Kbuild handles hostprogs-m exactly
750 like hostprogs-y. But only hostprogs-y is recommended to be used
751 when no CONFIG symbols are involved.
753 === 5 Kbuild clean infrastructure
755 "make clean" deletes most generated files in the obj tree where the kernel
756 is compiled. This includes generated files such as host programs.
757 Kbuild knows targets listed in $(hostprogs-y), $(hostprogs-m), $(always),
758 $(extra-y) and $(targets). They are all deleted during "make clean".
759 Files matching the patterns "*.[oas]", "*.ko", plus some additional files
760 generated by kbuild are deleted all over the kernel src tree when
761 "make clean" is executed.
763 Additional files can be specified in kbuild makefiles by use of $(clean-files).
766 #drivers/pci/Makefile
767 clean-files := devlist.h classlist.h
769 When executing "make clean", the two files "devlist.h classlist.h" will
770 be deleted. Kbuild will assume files to be in same relative directory as the
771 Makefile except if an absolute path is specified (path starting with '/').
773 To delete a directory hierarchy use:
776 #scripts/package/Makefile
777 clean-dirs := $(objtree)/debian/
779 This will delete the directory debian, including all subdirectories.
780 Kbuild will assume the directories to be in the same relative path as the
781 Makefile if no absolute path is specified (path does not start with '/').
783 Usually kbuild descends down in subdirectories due to "obj-* := dir/",
784 but in the architecture makefiles where the kbuild infrastructure
785 is not sufficient this sometimes needs to be explicit.
788 #arch/i386/boot/Makefile
789 subdir- := compressed/
791 The above assignment instructs kbuild to descend down in the
792 directory compressed/ when "make clean" is executed.
794 To support the clean infrastructure in the Makefiles that builds the
795 final bootimage there is an optional target named archclean:
800 $(Q)$(MAKE) $(clean)=arch/i386/boot
802 When "make clean" is executed, make will descend down in arch/i386/boot,
803 and clean as usual. The Makefile located in arch/i386/boot/ may use
804 the subdir- trick to descend further down.
806 Note 1: arch/$(ARCH)/Makefile cannot use "subdir-", because that file is
807 included in the top level makefile, and the kbuild infrastructure
808 is not operational at that point.
810 Note 2: All directories listed in core-y, libs-y, drivers-y and net-y will
811 be visited during "make clean".
813 === 6 Architecture Makefiles
815 The top level Makefile sets up the environment and does the preparation,
816 before starting to descend down in the individual directories.
817 The top level makefile contains the generic part, whereas
818 arch/$(ARCH)/Makefile contains what is required to set up kbuild
819 for said architecture.
820 To do so, arch/$(ARCH)/Makefile sets up a number of variables and defines
823 When kbuild executes, the following steps are followed (roughly):
824 1) Configuration of the kernel => produce .config
825 2) Store kernel version in include/linux/version.h
826 3) Symlink include/asm to include/asm-$(ARCH)
827 4) Updating all other prerequisites to the target prepare:
828 - Additional prerequisites are specified in arch/$(ARCH)/Makefile
829 5) Recursively descend down in all directories listed in
830 init-* core* drivers-* net-* libs-* and build all targets.
831 - The values of the above variables are expanded in arch/$(ARCH)/Makefile.
832 6) All object files are then linked and the resulting file vmlinux is
833 located at the root of the obj tree.
834 The very first objects linked are listed in head-y, assigned by
835 arch/$(ARCH)/Makefile.
836 7) Finally, the architecture-specific part does any required post processing
837 and builds the final bootimage.
838 - This includes building boot records
839 - Preparing initrd images and the like
842 --- 6.1 Set variables to tweak the build to the architecture
844 LDFLAGS Generic $(LD) options
846 Flags used for all invocations of the linker.
847 Often specifying the emulation is sufficient.
851 LDFLAGS := -m elf_s390
852 Note: ldflags-y can be used to further customise
853 the flags used. See chapter 3.7.
855 LDFLAGS_MODULE Options for $(LD) when linking modules
857 LDFLAGS_MODULE is used to set specific flags for $(LD) when
858 linking the .ko files used for modules.
859 Default is "-r", for relocatable output.
861 LDFLAGS_vmlinux Options for $(LD) when linking vmlinux
863 LDFLAGS_vmlinux is used to specify additional flags to pass to
864 the linker when linking the final vmlinux image.
865 LDFLAGS_vmlinux uses the LDFLAGS_$@ support.
869 LDFLAGS_vmlinux := -e stext
871 OBJCOPYFLAGS objcopy flags
873 When $(call if_changed,objcopy) is used to translate a .o file,
874 the flags specified in OBJCOPYFLAGS will be used.
875 $(call if_changed,objcopy) is often used to generate raw binaries on
880 OBJCOPYFLAGS := -O binary
882 #arch/s390/boot/Makefile
883 $(obj)/image: vmlinux FORCE
884 $(call if_changed,objcopy)
886 In this example, the binary $(obj)/image is a binary version of
887 vmlinux. The usage of $(call if_changed,xxx) will be described later.
889 KBUILD_AFLAGS $(AS) assembler flags
891 Default value - see top level Makefile
892 Append or modify as required per architecture.
895 #arch/sparc64/Makefile
896 KBUILD_AFLAGS += -m64 -mcpu=ultrasparc
898 KBUILD_CFLAGS $(CC) compiler flags
900 Default value - see top level Makefile
901 Append or modify as required per architecture.
903 Often, the KBUILD_CFLAGS variable depends on the configuration.
907 cflags-$(CONFIG_M386) += -march=i386
908 KBUILD_CFLAGS += $(cflags-y)
910 Many arch Makefiles dynamically run the target C compiler to
911 probe supported options:
916 cflags-$(CONFIG_MPENTIUMII) += $(call cc-option,\
917 -march=pentium2,-march=i686)
919 # Disable unit-at-a-time mode ...
920 KBUILD_CFLAGS += $(call cc-option,-fno-unit-at-a-time)
924 The first example utilises the trick that a config option expands
925 to 'y' when selected.
927 CFLAGS_KERNEL $(CC) options specific for built-in
929 $(CFLAGS_KERNEL) contains extra C compiler flags used to compile
930 resident kernel code.
932 CFLAGS_MODULE $(CC) options specific for modules
934 $(CFLAGS_MODULE) contains extra C compiler flags used to compile code
935 for loadable kernel modules.
938 --- 6.2 Add prerequisites to archprepare:
940 The archprepare: rule is used to list prerequisites that need to be
941 built before starting to descend down in the subdirectories.
942 This is usually used for header files containing assembler constants.
946 archprepare: maketools
948 In this example, the file target maketools will be processed
949 before descending down in the subdirectories.
950 See also chapter XXX-TODO that describe how kbuild supports
951 generating offset header files.
954 --- 6.3 List directories to visit when descending
956 An arch Makefile cooperates with the top Makefile to define variables
957 which specify how to build the vmlinux file. Note that there is no
958 corresponding arch-specific section for modules; the module-building
959 machinery is all architecture-independent.
962 head-y, init-y, core-y, libs-y, drivers-y, net-y
964 $(head-y) lists objects to be linked first in vmlinux.
965 $(libs-y) lists directories where a lib.a archive can be located.
966 The rest list directories where a built-in.o object file can be
969 $(init-y) objects will be located after $(head-y).
970 Then the rest follows in this order:
971 $(core-y), $(libs-y), $(drivers-y) and $(net-y).
973 The top level Makefile defines values for all generic directories,
974 and arch/$(ARCH)/Makefile only adds architecture-specific directories.
977 #arch/sparc64/Makefile
978 core-y += arch/sparc64/kernel/
979 libs-y += arch/sparc64/prom/ arch/sparc64/lib/
980 drivers-$(CONFIG_OPROFILE) += arch/sparc64/oprofile/
983 --- 6.4 Architecture-specific boot images
985 An arch Makefile specifies goals that take the vmlinux file, compress
986 it, wrap it in bootstrapping code, and copy the resulting files
987 somewhere. This includes various kinds of installation commands.
988 The actual goals are not standardized across architectures.
990 It is common to locate any additional processing in a boot/
991 directory below arch/$(ARCH)/.
993 Kbuild does not provide any smart way to support building a
994 target specified in boot/. Therefore arch/$(ARCH)/Makefile shall
995 call make manually to build a target in boot/.
997 The recommended approach is to include shortcuts in
998 arch/$(ARCH)/Makefile, and use the full path when calling down
999 into the arch/$(ARCH)/boot/Makefile.
1003 boot := arch/i386/boot
1005 $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
1007 "$(Q)$(MAKE) $(build)=<dir>" is the recommended way to invoke
1008 make in a subdirectory.
1010 There are no rules for naming architecture-specific targets,
1011 but executing "make help" will list all relevant targets.
1012 To support this, $(archhelp) must be defined.
1017 echo '* bzImage - Image (arch/$(ARCH)/boot/bzImage)'
1020 When make is executed without arguments, the first goal encountered
1021 will be built. In the top level Makefile the first goal present
1023 An architecture shall always, per default, build a bootable image.
1024 In "make help", the default goal is highlighted with a '*'.
1025 Add a new prerequisite to all: to select a default goal different
1032 When "make" is executed without arguments, bzImage will be built.
1034 --- 6.5 Building non-kbuild targets
1038 extra-y specify additional targets created in the current
1039 directory, in addition to any targets specified by obj-*.
1041 Listing all targets in extra-y is required for two purposes:
1042 1) Enable kbuild to check changes in command lines
1043 - When $(call if_changed,xxx) is used
1044 2) kbuild knows what files to delete during "make clean"
1047 #arch/i386/kernel/Makefile
1048 extra-y := head.o init_task.o
1050 In this example, extra-y is used to list object files that
1051 shall be built, but shall not be linked as part of built-in.o.
1054 --- 6.6 Commands useful for building a boot image
1056 Kbuild provides a few macros that are useful when building a
1061 if_changed is the infrastructure used for the following commands.
1064 target: source(s) FORCE
1065 $(call if_changed,ld/objcopy/gzip)
1067 When the rule is evaluated, it is checked to see if any files
1068 need an update, or the command line has changed since the last
1069 invocation. The latter will force a rebuild if any options
1070 to the executable have changed.
1071 Any target that utilises if_changed must be listed in $(targets),
1072 otherwise the command line check will fail, and the target will
1074 Assignments to $(targets) are without $(obj)/ prefix.
1075 if_changed may be used in conjunction with custom commands as
1076 defined in 6.7 "Custom kbuild commands".
1078 Note: It is a typical mistake to forget the FORCE prerequisite.
1079 Another common pitfall is that whitespace is sometimes
1080 significant; for instance, the below will fail (note the extra space
1082 target: source(s) FORCE
1083 #WRONG!# $(call if_changed, ld/objcopy/gzip)
1086 Link target. Often, LDFLAGS_$@ is used to set specific options to ld.
1089 Copy binary. Uses OBJCOPYFLAGS usually specified in
1090 arch/$(ARCH)/Makefile.
1091 OBJCOPYFLAGS_$@ may be used to set additional options.
1094 Compress target. Use maximum compression to compress target.
1097 #arch/i386/boot/Makefile
1098 LDFLAGS_bootsect := -Ttext 0x0 -s --oformat binary
1099 LDFLAGS_setup := -Ttext 0x0 -s --oformat binary -e begtext
1101 targets += setup setup.o bootsect bootsect.o
1102 $(obj)/setup $(obj)/bootsect: %: %.o FORCE
1103 $(call if_changed,ld)
1105 In this example, there are two possible targets, requiring different
1106 options to the linker. The linker options are specified using the
1107 LDFLAGS_$@ syntax - one for each potential target.
1108 $(targets) are assigned all potential targets, by which kbuild knows
1109 the targets and will:
1110 1) check for commandline changes
1111 2) delete target during make clean
1113 The ": %: %.o" part of the prerequisite is a shorthand that
1114 free us from listing the setup.o and bootsect.o files.
1115 Note: It is a common mistake to forget the "target :=" assignment,
1116 resulting in the target file being recompiled for no
1120 --- 6.7 Custom kbuild commands
1122 When kbuild is executing with KBUILD_VERBOSE=0, then only a shorthand
1123 of a command is normally displayed.
1124 To enable this behaviour for custom commands kbuild requires
1125 two variables to be set:
1126 quiet_cmd_<command> - what shall be echoed
1127 cmd_<command> - the command to execute
1131 quiet_cmd_image = BUILD $@
1132 cmd_image = $(obj)/tools/build $(BUILDFLAGS) \
1133 $(obj)/vmlinux.bin > $@
1136 $(obj)/bzImage: $(obj)/vmlinux.bin $(obj)/tools/build FORCE
1137 $(call if_changed,image)
1138 @echo 'Kernel: $@ is ready'
1140 When updating the $(obj)/bzImage target, the line
1142 BUILD arch/i386/boot/bzImage
1144 will be displayed with "make KBUILD_VERBOSE=0".
1147 --- 6.8 Preprocessing linker scripts
1149 When the vmlinux image is built, the linker script
1150 arch/$(ARCH)/kernel/vmlinux.lds is used.
1151 The script is a preprocessed variant of the file vmlinux.lds.S
1152 located in the same directory.
1153 kbuild knows .lds files and includes a rule *lds.S -> *lds.
1156 #arch/i386/kernel/Makefile
1157 always := vmlinux.lds
1160 export CPPFLAGS_vmlinux.lds += -P -C -U$(ARCH)
1162 The assignment to $(always) is used to tell kbuild to build the
1164 The assignment to $(CPPFLAGS_vmlinux.lds) tells kbuild to use the
1165 specified options when building the target vmlinux.lds.
1167 When building the *.lds target, kbuild uses the variables:
1168 KBUILD_CPPFLAGS : Set in top-level Makefile
1169 cppflags-y : May be set in the kbuild makefile
1170 CPPFLAGS_$(@F) : Target specific flags.
1171 Note that the full filename is used in this
1174 The kbuild infrastructure for *lds file are used in several
1175 architecture-specific files.
1177 === 7 Kbuild syntax for exported headers
1179 The kernel include a set of headers that is exported to userspace.
1180 Many headers can be exported as-is but other headers requires a
1181 minimal pre-processing before they are ready for user-space.
1182 The pre-processing does:
1183 - drop kernel specific annotations
1184 - drop include of compiler.h
1185 - drop all sections that is kernel internat (guarded by ifdef __KERNEL__)
1187 Each relevant directory contain a file name "Kbuild" which specify the
1188 headers to be exported.
1189 See subsequent chapter for the syntax of the Kbuild file.
1193 header-y specify header files to be exported.
1196 #include/linux/Kbuild
1198 header-y += aio_abi.h
1200 The convention is to list one file per line and
1201 preferably in alphabetic order.
1203 header-y also specify which subdirectories to visit.
1204 A subdirectory is identified by a trailing '/' which
1205 can be seen in the example above for the usb subdirectory.
1207 Subdirectories are visited before their parent directories.
1211 objhdr-y specifies generated files to be exported.
1212 Generated files are special as they need to be looked
1213 up in another directory when doing 'make O=...' builds.
1216 #include/linux/Kbuild
1217 objhdr-y += version.h
1219 --- 7.3 destination-y
1221 When an architecture have a set of exported headers that needs to be
1222 exported to a different directory destination-y is used.
1223 destination-y specify the destination directory for all exported
1224 headers in the file where it is present.
1227 #arch/xtensa/platforms/s6105/include/platform/Kbuild
1228 destination-y := include/linux
1230 In the example above all exported headers in the Kbuild file
1231 will be located in the directory "include/linux" when exported.
1234 --- 7.4 unifdef-y (deprecated)
1236 unifdef-y is deprecated. A direct replacement is header-y.
1239 === 8 Kbuild Variables
1241 The top Makefile exports the following variables:
1243 VERSION, PATCHLEVEL, SUBLEVEL, EXTRAVERSION
1245 These variables define the current kernel version. A few arch
1246 Makefiles actually use these values directly; they should use
1247 $(KERNELRELEASE) instead.
1249 $(VERSION), $(PATCHLEVEL), and $(SUBLEVEL) define the basic
1250 three-part version number, such as "2", "4", and "0". These three
1251 values are always numeric.
1253 $(EXTRAVERSION) defines an even tinier sublevel for pre-patches
1254 or additional patches. It is usually some non-numeric string
1255 such as "-pre4", and is often blank.
1259 $(KERNELRELEASE) is a single string such as "2.4.0-pre4", suitable
1260 for constructing installation directory names or showing in
1261 version strings. Some arch Makefiles use it for this purpose.
1265 This variable defines the target architecture, such as "i386",
1266 "arm", or "sparc". Some kbuild Makefiles test $(ARCH) to
1267 determine which files to compile.
1269 By default, the top Makefile sets $(ARCH) to be the same as the
1270 host system architecture. For a cross build, a user may
1271 override the value of $(ARCH) on the command line:
1278 This variable defines a place for the arch Makefiles to install
1279 the resident kernel image and System.map file.
1280 Use this for architecture-specific install targets.
1282 INSTALL_MOD_PATH, MODLIB
1284 $(INSTALL_MOD_PATH) specifies a prefix to $(MODLIB) for module
1285 installation. This variable is not defined in the Makefile but
1286 may be passed in by the user if desired.
1288 $(MODLIB) specifies the directory for module installation.
1289 The top Makefile defines $(MODLIB) to
1290 $(INSTALL_MOD_PATH)/lib/modules/$(KERNELRELEASE). The user may
1291 override this value on the command line if desired.
1295 If this variable is specified, will cause modules to be stripped
1296 after they are installed. If INSTALL_MOD_STRIP is '1', then the
1297 default option --strip-debug will be used. Otherwise,
1298 INSTALL_MOD_STRIP will used as the option(s) to the strip command.
1301 === 9 Makefile language
1303 The kernel Makefiles are designed to be run with GNU Make. The Makefiles
1304 use only the documented features of GNU Make, but they do use many
1307 GNU Make supports elementary list-processing functions. The kernel
1308 Makefiles use a novel style of list building and manipulation with few
1311 GNU Make has two assignment operators, ":=" and "=". ":=" performs
1312 immediate evaluation of the right-hand side and stores an actual string
1313 into the left-hand side. "=" is like a formula definition; it stores the
1314 right-hand side in an unevaluated form and then evaluates this form each
1315 time the left-hand side is used.
1317 There are some cases where "=" is appropriate. Usually, though, ":="
1318 is the right choice.
1322 Original version made by Michael Elizabeth Chastain, <mailto:mec@shout.net>
1323 Updates by Kai Germaschewski <kai@tp1.ruhr-uni-bochum.de>
1324 Updates by Sam Ravnborg <sam@ravnborg.org>
1325 Language QA by Jan Engelhardt <jengelh@gmx.de>
1329 - Describe how kbuild supports shipped files with _shipped.
1330 - Generating offset header files.
1331 - Add more variables to section 7?