| 1 | /* |
| 2 | * include/linux/fsl_devices.h |
| 3 | * |
| 4 | * Definitions for any platform device related flags or structures for |
| 5 | * Freescale processor devices |
| 6 | * |
| 7 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> |
| 8 | * |
| 9 | * Copyright 2004,2012 Freescale Semiconductor, Inc |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify it |
| 12 | * under the terms of the GNU General Public License as published by the |
| 13 | * Free Software Foundation; either version 2 of the License, or (at your |
| 14 | * option) any later version. |
| 15 | */ |
| 16 | |
| 17 | #ifndef _FSL_DEVICE_H_ |
| 18 | #define _FSL_DEVICE_H_ |
| 19 | |
| 20 | #define FSL_UTMI_PHY_DLY 10 /*As per P1010RM, delay for UTMI |
| 21 | PHY CLK to become stable - 10ms*/ |
| 22 | #define FSL_USB_PHY_CLK_TIMEOUT 10000 /* uSec */ |
| 23 | |
| 24 | #include <linux/types.h> |
| 25 | |
| 26 | /* |
| 27 | * Some conventions on how we handle peripherals on Freescale chips |
| 28 | * |
| 29 | * unique device: a platform_device entry in fsl_plat_devs[] plus |
| 30 | * associated device information in its platform_data structure. |
| 31 | * |
| 32 | * A chip is described by a set of unique devices. |
| 33 | * |
| 34 | * Each sub-arch has its own master list of unique devices and |
| 35 | * enumerates them by enum fsl_devices in a sub-arch specific header |
| 36 | * |
| 37 | * The platform data structure is broken into two parts. The |
| 38 | * first is device specific information that help identify any |
| 39 | * unique features of a peripheral. The second is any |
| 40 | * information that may be defined by the board or how the device |
| 41 | * is connected externally of the chip. |
| 42 | * |
| 43 | * naming conventions: |
| 44 | * - platform data structures: <driver>_platform_data |
| 45 | * - platform data device flags: FSL_<driver>_DEV_<FLAG> |
| 46 | * - platform data board flags: FSL_<driver>_BRD_<FLAG> |
| 47 | * |
| 48 | */ |
| 49 | |
| 50 | enum fsl_usb2_controller_ver { |
| 51 | FSL_USB_VER_NONE = -1, |
| 52 | FSL_USB_VER_OLD = 0, |
| 53 | FSL_USB_VER_1_6 = 1, |
| 54 | FSL_USB_VER_2_2 = 2, |
| 55 | FSL_USB_VER_2_4 = 3, |
| 56 | FSL_USB_VER_2_5 = 4, |
| 57 | }; |
| 58 | |
| 59 | enum fsl_usb2_operating_modes { |
| 60 | FSL_USB2_MPH_HOST, |
| 61 | FSL_USB2_DR_HOST, |
| 62 | FSL_USB2_DR_DEVICE, |
| 63 | FSL_USB2_DR_OTG, |
| 64 | }; |
| 65 | |
| 66 | enum fsl_usb2_phy_modes { |
| 67 | FSL_USB2_PHY_NONE, |
| 68 | FSL_USB2_PHY_ULPI, |
| 69 | FSL_USB2_PHY_UTMI, |
| 70 | FSL_USB2_PHY_UTMI_WIDE, |
| 71 | FSL_USB2_PHY_SERIAL, |
| 72 | FSL_USB2_PHY_UTMI_DUAL, |
| 73 | }; |
| 74 | |
| 75 | struct clk; |
| 76 | struct platform_device; |
| 77 | |
| 78 | struct fsl_usb2_platform_data { |
| 79 | /* board specific information */ |
| 80 | enum fsl_usb2_controller_ver controller_ver; |
| 81 | enum fsl_usb2_operating_modes operating_mode; |
| 82 | enum fsl_usb2_phy_modes phy_mode; |
| 83 | unsigned int port_enables; |
| 84 | unsigned int workaround; |
| 85 | |
| 86 | int (*init)(struct platform_device *); |
| 87 | void (*exit)(struct platform_device *); |
| 88 | void __iomem *regs; /* ioremap'd register base */ |
| 89 | struct clk *clk; |
| 90 | unsigned power_budget; /* hcd->power_budget */ |
| 91 | unsigned big_endian_mmio:1; |
| 92 | unsigned big_endian_desc:1; |
| 93 | unsigned es:1; /* need USBMODE:ES */ |
| 94 | unsigned le_setup_buf:1; |
| 95 | unsigned have_sysif_regs:1; |
| 96 | unsigned invert_drvvbus:1; |
| 97 | unsigned invert_pwr_fault:1; |
| 98 | |
| 99 | unsigned suspended:1; |
| 100 | unsigned already_suspended:1; |
| 101 | unsigned has_fsl_erratum_a007792:1; |
| 102 | unsigned has_fsl_erratum_a005275:1; |
| 103 | unsigned has_fsl_erratum_a005697:1; |
| 104 | unsigned check_phy_clk_valid:1; |
| 105 | |
| 106 | /* register save area for suspend/resume */ |
| 107 | u32 pm_command; |
| 108 | u32 pm_status; |
| 109 | u32 pm_intr_enable; |
| 110 | u32 pm_frame_index; |
| 111 | u32 pm_segment; |
| 112 | u32 pm_frame_list; |
| 113 | u32 pm_async_next; |
| 114 | u32 pm_configured_flag; |
| 115 | u32 pm_portsc; |
| 116 | u32 pm_usbgenctrl; |
| 117 | }; |
| 118 | |
| 119 | /* Flags in fsl_usb2_mph_platform_data */ |
| 120 | #define FSL_USB2_PORT0_ENABLED 0x00000001 |
| 121 | #define FSL_USB2_PORT1_ENABLED 0x00000002 |
| 122 | |
| 123 | #define FLS_USB2_WORKAROUND_ENGCM09152 (1 << 0) |
| 124 | |
| 125 | struct spi_device; |
| 126 | |
| 127 | struct fsl_spi_platform_data { |
| 128 | u32 initial_spmode; /* initial SPMODE value */ |
| 129 | s16 bus_num; |
| 130 | unsigned int flags; |
| 131 | #define SPI_QE_CPU_MODE (1 << 0) /* QE CPU ("PIO") mode */ |
| 132 | #define SPI_CPM_MODE (1 << 1) /* CPM/QE ("DMA") mode */ |
| 133 | #define SPI_CPM1 (1 << 2) /* SPI unit is in CPM1 block */ |
| 134 | #define SPI_CPM2 (1 << 3) /* SPI unit is in CPM2 block */ |
| 135 | #define SPI_QE (1 << 4) /* SPI unit is in QE block */ |
| 136 | /* board specific information */ |
| 137 | u16 max_chipselect; |
| 138 | void (*cs_control)(struct spi_device *spi, bool on); |
| 139 | u32 sysclk; |
| 140 | }; |
| 141 | |
| 142 | struct mpc8xx_pcmcia_ops { |
| 143 | void(*hw_ctrl)(int slot, int enable); |
| 144 | int(*voltage_set)(int slot, int vcc, int vpp); |
| 145 | }; |
| 146 | |
| 147 | /* Returns non-zero if the current suspend operation would |
| 148 | * lead to a deep sleep (i.e. power removed from the core, |
| 149 | * instead of just the clock). |
| 150 | */ |
| 151 | #if defined(CONFIG_PPC_83xx) && defined(CONFIG_SUSPEND) |
| 152 | int fsl_deep_sleep(void); |
| 153 | #else |
| 154 | static inline int fsl_deep_sleep(void) { return 0; } |
| 155 | #endif |
| 156 | |
| 157 | #endif /* _FSL_DEVICE_H_ */ |